ESE370: Circuit-Level Modeling, Design, and Optimization ...ese370/fall2015/handouts/lec27.pdf ·...

ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems

Lec 27: November 11, 2015 RAM Core Pt 2

Penn ESE 370 Fall 2015 – Khanna (adapted from CMOS VLSI DESIGN, DM Harris)

Outline

!  Multiported SRAM !  Serial Access Memories !  DRAM

2 Penn ESE 370 Fall 2015 - Khanna

Reminder: 6T SRAM Cell

!  Cell size accounts for most of array size "  Reduce cell size at expense of complexity

!  6T SRAM Cell "  Used in most commercial chips "  Data stored in cross-coupled inverters

!  Read: "  Precharge BL, BL’ "  Raise WL

!  Write: "  Drive data onto BL, BL’ "  Raise WL

3

bit bit_b

word

Penn ESE 370 Fall 2015 - Khanna

BL BL’ WL

Multiple Ports

!  We have considered single-ported SRAM "  One read or one write on each cycle

!  Multiported SRAM are needed for register files !  Examples:

"  Pipelined ALU register file: "  add r1,r2,r3 "  R3#R1+R2 "  Requires two

reads and one write


Dual-Ported SRAM

!  Simple dual-ported SRAM "  Two independent single-ended reads "  Or one differential write

5

bit bit_b

wordBwordA


Dual-Ported SRAM

!  Simple dual-ported SRAM "  Two independent single-ended reads "  Or one differential write

!  Do two reads and one write by time multiplexing "  Read during ph1, write during ph2

6

bit bit_b

wordBwordA


Multi-Ported SRAM

!  Adding more access transistors hurts read stability !  Multiported SRAM isolates reads from state node !  Single-ended bitlines save area


Serial Access Memories

!  Serial access memories do not use an address "  Shift Registers "  Tapped Delay Lines "  Serial In Parallel Out (SIPO) "  Parallel In Serial Out (PISO) "  Queues (FIFO, LIFO)


Shift Register

!  Shift registers store and delay data !  Simple design: cascade of registers

9

clk

Din Dout8


Denser Shift Registers

!  Flip-flops aren’t very area-efficient !  For large shift registers, keep data in SRAM instead !  Move read/write pointers to RAM rather than data

"  Initialize read address to first entry, write to last "  Increment address on each cycle

10

Din

Dout

clk

counter counter

reset

00...00

11...11

readaddr

writeaddr

dual-portedSRAM


Serial In Parallel Out

!  1-bit shift register reads in serial data "  After N steps, presents N-bit parallel output

11

clk

P0 P1 P2 P3

Sin


Parallel In Serial Out

!  Load all N bits in parallel when shift = 0 "  Then shift one bit out per cycle

12

clkshift/load

P0 P1 P2 P3

Sout


Queues

!  Queues allow data to be read and written at different rates.

!  Read and write each use their own clock, data !  Queue indicates whether it is full or empty !  Build with SRAM and read/write counters

(pointers)

13

Queue

WriteClk

WriteData

FULL

ReadClk

ReadData

EMPTY


FIFO, LIFO Queues

!  First In First Out (FIFO) "  Initialize read and write pointers to first element "  Queue is EMPTY "  On write, increment write pointer "  If write almost catches read, Queue is FULL "  On read, increment read pointer

!  Last In First Out (LIFO) "  Also called a stack "  Use a single stack pointer for read and write


DRAM

!  Smaller than SRAM !  Require data refresh to compensate for leakage

Penn ESE 370 Fall 2015 - Khanna 15

3-Transistor DRAM Cell

M2M1

BL1

WWL

BL2

M3

RWL

CS

X

WWL

RWL

X

BL1

BL2

VDD-VT

ΔV

VDD

VDD-VT

No constraints on device ratiosReads are non-destructiveValue stored at node X when writing a “1” = VWWL-VTn


Charge Sharing

!  Initially "  A @ 1V "  B @ 0V

!  Close switch !  Voltage at A?


Charge Sharing

Initially "  A @ 1V "  B @ 0V

!  QA=1V*C1=C1 Close switch !  Qtot=Vfinal*(C1+C0) !  Charge conservation

"  QA=Qtot

!  C1=Vfinal*(C1+C0)

18

€

Vfinal =C1

C1+C0Penn ESE 370 Fall 2015 - Khanna

1-Transistor DRAM Cell

CSM1

BL

WL

CBL

WL

X

BL

VDD−VT

VDD/2

VDD

GND

Write "1" Read "1"

sensingVDD/2

ΔV VBL VPRE– VBIT VPRE–( )CS

CS CBL+------------------------= =

Write: CS is charged or discharged by asserting WL and BL.Read: Charge redistribution takes places between bit line and storage capacitance

Voltage swing is small; typically around 250 mV.


DRAM Cell Observations

1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out.

DRAM memory cells are single ended in contrast to SRAM cells.

The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation.

Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design.

When writing a “1” into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than VDD.

Admin

!  Project 2 out later today !  Friday lecture

"  Detailed periphery circuits

!  Monday in Detkin Lab


ESE370: Circuit-Level Modeling, Design, and Optimization ...ese370/fall2015/handouts/lec27.pdf ·...

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