ES6425 Digital Media Processor 2 ESS Technology, Inc. Data...

ESS Technology, Inc.

ESS Technology, Inc.

PRELIMINARY ES6425Digital Media Processor 2

Data Sheet

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DESCRIPTION

The ES6425 Digital Media Processor 2 (DMP2) is a highperformance single-chip audio/video decoder for a wideser ies o f app l i ca t ions such as ne tworked o rnon-networked/flash memory media players. This secondgeneration of Digital Media Processor has an enhancedperformance engine to decode MPEG-4 video at D1resolution with state-of-the-art progressive scanNTSC/PAL video encoder for bri l l iant and sharp,flicker-free output to the video display.

At the heart of the ES6425 is the ESS proprietaryProgrammable Multimedia Processor core consisting of32-bit RISC and 64-bit DSP processors that enablesimultaneous parallel execution of system commands andspecialized multimedia decoding tasks. The ES6425includes a memory controller which interfaces to 8-bit or16-bit DRAM with up to 128-Mb capacity.

The ES6425 performs video processing to providehigh-resolution display of MPEG-1, MPEG-2, andMPEG-4 videos and JPEG photos. The integratedNTSC/PAL TV-encoder provides composite, S-video, andYUV outputs. The ES6425 includes an On-Screen-Display(OSD) controller to provide a user friendly setup menu toenable or modify the various audio decoding and videodisplay features. A CCIR656/601 digital video output portis also present.

The ES6425 also performs audio processing for CD-DA,MP3, AAC, and WMA playback along with a 7-bandgraphic equalizer. The ES6425 has a multi-channel audioserial port compliant to I2S format for interfacing to anexternal audio DAC and ADC. An S/PDIF output port isalso integrated for transmitting digital audio streams.

A 16-bit host interface present in the ES6425 connects tomany different storage solutions including CompactFlash, Smart Media, xD-Picture Card, and IDE harddrives. Similarly, a serial interface is built-in to interface toSD, XD, MultiMediaCard, and Memory Stickdevices.

The ES6425 is available in an industry-standard 208-pinPlastic Quad Flat Pack (PQFP) device package.

FEATURES • Single-chip digital audio and video decoder and

processor.

• MPEG-4 Advanced Simple Profile* at full screen D1 video playback (playability is dependent on memory card bandwidth).

• MPEG-2 video playback (playability is dependent on memory card bandwidth).

• MPEG-1 video playback.

• Motion JPEG playback.

• JPEG photo playback.

• Progressive JPEG photo playback.

• MP3 music playback.

• WMA music playback (Microsoft license required).

• ESS Music Slideshow.

• S/PDIF digital audio output.

• AAC audio decode and playback.

• Integrated NTSC/PAL encoder with pixel adaptive de-interlacer and five 10-bit 54 MHz video DACs.

• High-quality progressive scan video output for flicker-freevideo display.

• Simultaneous Composite, S-Video, and YUV outputs.

• CCIR656/601 YUV 4:2:2 output.

• On-Screen-Display controller with 3-bit blending to provide 256 colors display.

• Integrated I2S serial port for up to 5.1 channel audio output and stereo input.

• Direct interface for IDE devices and flash memory cards including CF, MS, MS Pro, SD, XD, MMC, and SM.

• DRAM memory controller with interface to 8-bit or 16-bit SDRAM for up to 16 MB of memory.

• 16-bit SRAM interface for connecting to boot EPROM or flash memory.

• Lead-free leads using 98%-Sn/2%-Cu or 98%-Sn/2%-Biavailable with ES6425FF (see soldering requirement onpage 67).

SAM0530-082704 1

ES6425 DATA SHEET

FEATURES

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LICENSING REQUIREMENTS

Depending on the features implemented, you may berequired to apply for a l icense with the followingorganizations:

Compact Flash:

www.compactflash.org

SmartMedia:

www.ssfdc.or.jp

SD:

www.sdcard.org

Memory Stick:

www.memorystick.org

xD-Picture Card:

www.xd-picture.com

WMA Decode:

www.microsoft.com

MPEG-4 Decode:

www.mpegla.com

AAC Decode:

www.vialicensing.com

MultiMediaCard:

www.mmca.org

2 SAM0530-082704 ESS Technology, Inc.

http://www.compactflash.org

http://www.ssfdc.or.jp

http://www.sdcard.org

http://www.memorystick.org

http://www.xd-picture.com

http://www.microsoft.com

http://www.mpegla.com

http://www.vialicensing.com

http://www.mmca.org

ES6425 DATA SHEET

CONTENTS

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CONTENTSDESCRIPTION .............................................................. 1

FEATURES ................................................................... 1

CONTENTS ................................................................... 3

FIGURES ....................................................................... 4

TABLES ......................................................................... 4

ES6425 PINOUT DIAGRAM ......................................... 5

ES6425 PIN DESCRIPTION ......................................... 6

ES6425 DEVICE INTERFACES .................................. 12

SYSTEM BLOCK DIAGRAM ....................................... 16

FUNCTIONAL DESCRIPTION .................................... 17

ES6425 Device Architecture .................................. 17ESS RISC Processor ........................................ 17PMP Operation .................................................. 17RISC Core ......................................................... 18SIMD DSP ......................................................... 18Cache Line Operation ....................................... 18RISC Interrupts .................................................. 18

Command Queue and Video Processor ................. 19Command Queue .............................................. 19Video Processor ................................................ 19

DMA Controller ....................................................... 19

Transport Stream Parser ........................................ 20Output CRT Controller ....................................... 20Video MPEG Decoder ....................................... 20

NTSC/PAL Video Encoder ..................................... 20Progressive Scan .............................................. 21On-Screen Display Controller ............................ 21

Device Interfaces .................................................... 21Audio Interface .................................................. 21Host Interface .................................................... 21Memory Interface .............................................. 22

SDRAM Considerations ............................... 22SDRAM Address Mapping ........................... 22SDRAM Configuration Requirements .......... 22

Storage Device Interfaces ................................. 23ATA/IDE Interface ........................................ 23Compact Flash Interface .............................. 23Memory Stick Interface ................................ 24Memory Stick Addressing ............................ 24

System SRAM Interface .................................... 24TDM Interface .................................................... 25

Vacuum Fluorescent Display Controller Interface ..........................................................25

Video Interface ...................................................25Video Display Output .........................................25Video Bus ..........................................................25Video Post-Processing ......................................26Video Timing ......................................................26

REGISTERS ................................................................27

Host Interface Host Side Registers .........................27

Video Interface Registers ........................................28Video Output Registers ......................................28On-Screen Display Controller Registers ............32Digital Video Encoder Registers ........................33VFD Interface Registers ....................................35

Host Interface RISC Side Registers ........................36

Host Interface RISC-SRAM Interface Registers .....38

Bus Controller Registers .........................................39Bus Controller (SIMD DSP) Registers ...............39Bus Controller (Memory Controller) Registers ...40Bus Controller (Command Queue) Registers ....41

Audio Interface Registers ........................................41S/PDIF Interface Registers ................................43

ES6425 TIMING DIAGRAMS .......................................44

Audio Interface Timing ............................................44

Clock Interface Timing ............................................46

Compact Flash Interface Timing .............................47

Host Interface Timing ..............................................49

Memory Stick Interface Timing ...............................51

SDRAM Interface Timing ........................................52

SRAM Interface Timing ...........................................57

TDM Interface Timing .............................................59

Video Interface Timing ............................................60

ELECTRICAL SPECIFICATIONS ................................65

Absolute Maximum Ratings ....................................65

Recommended Operating Conditions .....................65

Power Dissipation ...................................................65

DC Electrical Characteristics ..................................65

AC Electrical Characteristics ...................................66

MECHANICAL DIMENSIONS ......................................67

ORDERING INFORMATION ........................................68

Other DMP Processors ...........................................68

ESS Technology, Inc. SAM0530-082704 3

ES6425 DATA SHEET

FIGURES

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FIGURES

Figure 1 ES6425 Device Pinout .................................5Figure 2 ES6425 System Block Diagram .................16Figure 3 ES6425 Block Diagram ..............................17Figure 4 ESS RISC Block Diagram ..........................18Figure 5 Basic Memory Stick Hardware Interfaces ..24Figure 6 Video Output Timing ...................................25Figure 7 Video Post-Processing ...............................26Figure 8 Horizontal Video Timing .............................26Figure 9 Vertical Video Timing .................................26Figure 10 Right Justified Mode / 16-Bit Cycle Frame /

16-Bit Data Frame / MSB First ................44Figure 11 Right Justified Mode / 24-Bit Cycle Frame /

16-Bit Data Frame / MSB First ................44Figure 12 Right Justified Mode / 32-Bit Cycle Frame /

24-Bit Data Frame / LSB First .................44Figure 13 Left Justified Mode / 32-Bit Cycle Frame /

24-Bit Data Frame / MSB First ................45Figure 14 I2S Mode ....................................................45Figure 15 Audio Master, Pixel, Doubled Pixel, and

TDM Clock Timing ...................................46Figure 16 Compact Flash True IDE Mode I/O Read

Timing ......................................................47Figure 17 Compact Flash True IDE Mode I/O Write

Timing ......................................................48Figure 18 Host Bus Read Timing ................................49

Figure 19 Host Bus Write Timing ............................... 50Figure 20 Memory Stick Read Timing ........................ 51Figure 21 Memory Stick Write Timing ........................ 51Figure 22 SDRAM Random Column Read Timing ..... 52Figure 23 SDRAM Random Column Write Timing ..... 53Figure 24 SDRAM Random Row Read Timing .......... 54Figure 25 SDRAM Random Row Write Timing .......... 55Figure 26 ES6425 SDRAM Read and Write .............. 56Figure 27 SRAM Read Timing ................................... 57Figure 28 SRAM Write Timing .................................... 58Figure 29 TDM Interface Timing ................................ 59Figure 30 NTSC Timing ............................................. 60Figure 31 PAL Timing ................................................. 60Figure 32 NTSC Closed Captioning Timing ............... 61Figure 33 PAL Teletext / Vertical Blanking Interval

Timing ..................................................... 61Figure 34 NTSC Composite (VDAC) Line Output

Waveform ............................................... 62Figure 35 PAL Composite (VDAC) Line Output

Waveform ............................................... 62Figure 36 Luma (YDAC) Line Output Waveform ........ 63Figure 37 Chroma (CDAC) Line Output Waveform .... 63Figure 38 Sync and Pixel Clock Timings .................... 64Figure 39 208-pin Plastic Quad Flat Package

(PQFP) .................................................... 67

TABLES

Table 1 ES6425 Pin Description . . . . . . . . . . . . . . 6Table 2 ES6425 Device Interfaces . . . . . . . . . . . 12Table 3 ESS RISC Interrupts . . . . . . . . . . . . . . . . 18Table 4 Typical SDRAM Configurations . . . . . . . 22Table 5 SDRAM Configurations and Signal Pins . 22Table 6 Packet Commands for ATAPI Devices . . 23Table 7 CF-ATA Command Set . . . . . . . . . . . . . . 24Table 8 ESS RISC Clock Relationship to Pixel

Clocks . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 9 External Memory Width Selection Options . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 10 Hex Values for Wait States . . . . . . . . . . . . 39Table 11 SDRAM Interface Timing . . . . . . . . . . . . . 56Table 12 SDRAM Read and Write Timing . . . . . . . . 56Table 13 DC Electrical Characteristics . . . . . . . . . . 65Table 14 Video DAC DC Electrical Characteristics . 66Table 15 Video DAC AC Electrical Characteristics . 66Table 16 VFD Interface Characteristics . . . . . . . . .66

Note: (*) MPEG-4 Advanced Simple Profile without hardware Q-PEL and Global Motion Compensation(GMC).


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ES6425 DATA SHEET

ES6425 PINOUT DIAGRAM

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ES6425 PINOUT DIAGRAM

The device pinout for the ES6425 is shown in Figure 1. Thepound symbol (#) denotes an active-low signal.

Figure 1 ES6425 Device Pinout

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

53 54 55 56 57 58 59 60 61

62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99100101102103104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208

LCS1#

LOE#

LD0VSS

LCS3#LCS2#

I2CDATA/AUX0

LA21

LA20

RE

SE

T#

VE

E

NC

HIO

CS

16#/

AU

X3[

4]

HA

1/A

UX

4[3]

VS

S

HA

0/A

UX

4[2]

HW

R#/

AU

X4[

5]H

RD

#/A

UX

4[6]

HD

4/A

UX

1[4]

HD

5/A

UX

1[5]

HD

6/A

UX

1[6]

/VFD

_DO

UT

HD

2/A

UX

1[2]

HD

3/A

UX

1[3]

VE

E

VCC

DB8

VC

C

DB5

DB9

DCS0#

VC

CV

SS

TSD

0/S

EL_

PLL

0

TSD

1/S

EL_

PLL

1

TDM

FSTD

MC

LKTD

MD

R

TDM

TS

C#

TWS

/SE

L_P

LL2

VE

ELA

4LA

5LA

6LA

7LA

8LA

9V

SS

VC

CLA

10LA

11LA

12LA

13LA

14LA

15LA

16V

SS

VE

ELA

17LA

18LA

19

TDM

DX

/RS

EL

VS

S

TSD

2

SP

DIF

/SE

L_P

LL3

NC

VS

S

MC

LKTB

CK

VEE

VEE

AVS

S

VSS

DQM

RS

DR

WS

RB

CK

CA

MIN

3X

INX

OU

TAV

EE

DSCK

VSS

DB15

DB13

DB11

DB1

VSS

DMBS1

DRAS#

DOE#/DSCK_EN

VEE

DMA9

DMA7

VSS

DMA5

DMA3

VEE

DCS1#

DB14

DB12

DB10

DB0

VEE

DMBS0

DWE#

DCAS#

VSS

DMA8

DMA6

VEE

DMA4

DMA2

VSS

DB7DB6VSS

DB4DB3DB2

DMA11DMA10

DMA1DMA0

HC

S3F

X3#

/AU

X3[

6]H

CS

1FX

#/A

UX

3[7]

VS

SH

IOR

DY

/AU

X3[

3]

VS

SH

D13

/AU

X2[

5]H

D12

/AU

X2[

4]H

D11

/AU

X2[

3]H

D10

/AU

X2[

2]H

D9/

AU

X2[

1]H

D8/

AU

X2[

0]/V

FD_C

LK

VS

S

HIR

Q/A

UX

4[7]

HR

ST#

/AU

X3[

5]

HR

RQ

#/A

UX

4[0]

/CA

MIN

2H

WR

Q#/

AU

X4[

1]H

D15

/AU

X2[

7]/IR

HD

14/A

UX

2[6]

VC

C

HD

7/A

UX

1[7]

/VFD

_DIN

HD

1/A

UX

1[1]

HD

0/A

UX

1[0]

VC

CV

SS

HS

YN

C#/

AU

X3[

0]/C

AM

IN7

PC

LK2X

SC

N/C

AM

IN4

YU

V7/

PIX

OU

T7Y

UV

6/V

DA

C/P

IXO

UT6

PC

LKQ

SC

N/A

UX

3[2]

/CA

MIN

5V

SY

NC

#/A

UX

3[1]

/CA

MIN

6

YU

V5/

YD

AC

/PIX

OU

T5A

DV

SS

AD

VE

EY

UV

4/R

SE

T/P

IXO

UT4

YU

V3/

CO

MP

/PIX

OU

T3

YU

V2/

CD

AC

/PIX

OU

T2Y

UV

1/V

RE

F/P

IXO

UT1

YU

V0/

UD

AC

/PIX

OU

T0D

CLK

VE

E

AUX7AUX6

VEE

LD1LD2

LA3

LD12VEE

HA2/AUX4[4]VEE

VEE

LD3

LD5

LD9

LD13

LWRHL#

CAMIN1

I2C_CLK/AUX1

IORD#/AUX3

LD4

LD6

LD10

LD14

VSS

LA0

IOW#/AUX2

AUX4

VEE

LD7

LD11

LD15

VEE

LA1

VSS

AUX5

VSS

LD8

VSS

LWRLL#

CAMIN0

LA2

VSSVCC

LCS0#/PIXOUT_CLK

VSS

ES6425

SS Technology, Inc. SAM0530-082704 5

ES6425 DATA SHEET

ES6425 PIN DESCRIPTION

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ES6425 PIN DESCRIPTIONTable 1 lists the pin descriptions for the ES6425. Thepound symbol (#) denotes an active-low signal.

Table 1 ES6425 Pin Description

Name Pin Numbers I/O Definition

VEE

1,18, 27, 59, 68, 75, 92, 99, 104, 130,

148, 157, 159, 164, 183, 193, 201

P I/O power supply.

LA[21:0]2-7, 10-16, 19-23,

204-207O RISC port address bus.

VSS

8, 17, 26, 34, 43, 60, 67, 76, 84, 91, 98, 103, 120, 129, 138, 147, 156, 163, 171, 177, 184, 192,

200, 208

G Ground.

VCC9, 35, 44, 83, 121,

139, 172I Core power supply.

RESET# 24 I Reset input (active-low); (5V tolerant input).

TDMDX

25

O TDM transmit data.

RSEL

I LCS3 ROM Boot Data Width Select. Strapped to VCC or ground via 4.7-kΩresistor; read during reset.

TDMDR 28 I TDM receive data; (5V tolerant input).

TDMCLK 29 I TDM clock; (5V tolerant input).

TDMFS 30 I TDM frame sync; (5V tolerant input).

TDMTSC# 31 O TDM output enable (active-low).

TWS

32

O Audio transmit frame sync.

SEL_PLL2 I

System and DSCK output clock frequency selection is made at the rising edge ofRESET#. The matrix below lists the available clock frequencies and theirrespective PLL bit settings. Pull up to VCC via 4.7-kΩ resistor for properoperation; read during reset.

RSEL Selection

0 16-bit ROM

1 8-bit ROM

SEL_PLL2 SEL_PLL1 SEL_PLL0 Clock Type

0 0 0 DCLK x 4.25

0 0 1 Reserved

0 1 0 Bypass mode

0 1 1 DCLK x 3.75

1 0 0 DCLK x 4.5

1 0 1 Reserved

1 1 0 DCLK x 3.5

1 1 1 DCLK x 4


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TSD033

O Audio transmit serial data output 0.

SEL_PLL0 I Pull up to VCC via 4.7-kΩ resistor for proper operation; read during reset.

TSD136

O Audio transmit serial data output 1.

SEL_PLL1 I Pull up to VCC via 4.7-kΩ resistor for proper operation; read during reset.

TSD2 37 O Audio transmit serial data output 2. This pin must be pulled down to VSS via a 4.7-kΩ resistor for proper operation.

MCLK 39 I/O Audio master clock for audio DAC.

TBCK 40 I/O Audio transmit bit clock. TBCK is an input during reset and subsequently is programmed as an output via the AUDIOXMT register (addr 0x2000D00Ch, bit 4).

SPDIF41

O S/PDIF output.

SEL_PLL3 I Pull down to ground via 4.7-kΩ resistor for proper operation; read during reset.

NC 38, 42 — No connect.

RSD 45 I Audio receive serial data; (5V tolerant input).

RWS 46 I Audio receive frame sync; (5V tolerant input).

RBCK 47 I Audio receive bit clock; (5V tolerant input).

CAMIN3 48 I Camera and YUV input 3.

XIN 49 I 27-MHz crystal input.

XOUT 50 O 27-MHz crystal output.

AVEE 51 P Analog power for PLL.

AVSS 52 G Analog ground for PLL.

DMA[11:0] 53-58, 61-66 O DRAM address bus.

DCAS# 69 O DRAM column address strobe (active-low).

DOE#70

O DRAM output enable (active-low).

DSCK_EN O DRAM clock enable.

DWE# 71 O DRAM write enable (active-low).

DRAS# 72 O DRAM row address strobe (active-low).

DMBS0 73 O SDRAM bank select 0.

DMBS1 74 O SDRAM bank select 1.

DB[15:0] 77-82, 85-90, 93-96 I/O DRAM data bus.

DCS[1:0]# 97,100 O SDRAM chip select (active-low).

DQM 101 O Data input/output mask.

DSCK 102 O Output clock to SDRAM.

DCLK 105 I Clock input to PLL; (5V tolerant input).

Table 1 ES6425 Pin Description (Continued)



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UDAC 106

O Video DAC output:

Y: Luma component for YUV and Y/C processing.C: Chrominance signal for Y/C processing.U: Chrominance component signal for YUV mode.V: Chrominance component signal for YUV mode.

YUV0 O YUV pixel 0 output data.

PIXOUT0 O CCIR656 output pixel 0.

VREF

107

I Internal voltage reference to DAC. Bypass to ground with 0.1-µF capacitor.



CDAC

108

O Chrominance signal for Y/C processing display.



COMP

109

I Compensation input. Bypass to ADVEE with 0.1-µF capacitor.



RSET

110

I DAC current adjustment resistor input.



ADVEE 111 P Analog power.

ADVSS 112 G Analog ground for video DAC.



ValueDAC V

(pin 114)DAC Y

(pin 113)DAC C

(pin 108)DAC U

(pin 106)

0 CVBS1 Y N/A C

1 CVBS1 Y CVBS2 C

2 N/A Y N/A C

3 CVBS1 N/A CVBS2 N/A

4 CVBS1 N/A N/A N/A

5 CVBS1 Y Pr Pb

6 N/A Y Pr Pb

7 SYNC G R B

8 CHROMA Y Pr Pb

9 CVBS1 G R B

10 CVBS1 G B R

11 SYNC G B R

12 N/A Y Pb Pr

13 CVBS1 Y Pb Pr


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YDAC

113

O Luma component for Y/C processing display.



VDAC

114

O Video DAC output. Refer to description and matrix for UDAC pin 106.



YUV7115

O YUV pixel 7 output data.


PCLK2XSCN116

I/O 27-MHz video pixel clock.

CAMIN4 I Camera and YUV input 4.

PCLKQSCN

117

O 13.5-MHz video output pixel clock.

AUX3[2] I/O Aux3 data I/O; (5V tolerant input).

CAMIN5 I Camera and YUV input 5

VSYNC#

118

I/O Vertical sync (active-low); (5V tolerant input).



HSYNC#

119

I/O Horizontal sync (active-low); (5V tolerant input).



HD[5:0]122-127

I/O Host data bus; (5V tolerant input).

AUX1[5:0] I/O Aux1 data I/O; (5V tolerant input).

HD6

128



VFD_DOUT O VFD data output.

HD7

131



VFD_DIN I VFD data input.

HD8

132



VFD_CLK I VFD clock.

HD9133



HD10134






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HD11135



HD12136



HD13137



HD14140



HD15

141


AUX2[7] I/O Aux2 data I/O 7; (5V tolerant input).

IR I IR remote control; (5V tolerant input).

HWRQ#142

O Host write request (active-low).


HRRQ#

143

O Host read request (active-low).



HIRQ144

O Host interrupt.


HRST#145

O Host reset (active-low).


HIORDY146

I Host I/O ready.


HWR#149

O Host write (active-low).


HRD#150

O Host read (active-low).


HIOCS16#

151

I Device 16 bit data transfer (active-low).


CAMCLK I Camera and YUV port pixel clock.

HCS1FX#152

O Host select 1 (active-low).


HCS3FX#153

O Host select 3 (active-low).





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HA[2:0]154, 155, 158

I/O Host address bus.

AUX4[4:2] I/O Aux4 data I/Os 2, 3, and 4; (5V tolerant input).

AUX0160

I/O Auxiliary port 0 (open collector); (5V tolerant input).

I2CDATA I/O I2C data I/O; (5V tolerant input).

AUX1161

I/O Auxiliary port 1 (open collector); (5V tolerant input).

I2C_CLK I/O I2C clock I/O; (5V tolerant input).

IOW#162

O I/O write strobe (LCS1) (active-low).

AUX2 I/O Auxiliary port 2; (5V tolerant input).

IOR#165

O I/O read strobe (LCS1) (active-low).

AUX3 I/O Auxiliary port 3; (5V tolerant input).

AUX4-7 166-169 I/O Auxiliary ports 4-7; (5V tolerant input).

LOE# 170 O RISC port output enable (active-low).

LCS0#173

O RISC port chip select 0 (active-low).

PIXOUT_CLK O CCIR656 output pixel clock.

LCS[3:1]# 174-176 O RISC port chip select [3:1] (active-low).

LD[15:0]178-182, 185-191,

194-197I/O RISC port data bus; (5V tolerant input).

LWRLL# 198 O RISC port low-byte write enable (active-low).

LWRHL# 199 O RISC port high-byte write enable (active-low).






ES6425 DATA SHEET

ES6425 DEVICE INTERFACES

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Table 2 lists the device interfaces for the ES6425. Thepound symbol (#) denotes an active-low signal.

Table 2 ES6425 Device Interfaces


Audio Port Interface

32 O Audio transmit frame sync output (TWS).

33, 36 O Audio transmit serial data outputs (TSD0, 1).

37 O Audio transmit serial data output 2 (TSD2). This pin must be pulled down to VSS via a 4.7-kΩ resistor for proper operation.

39 I/O Audio DAC master clock (MCLK).

40 I/O Audio transmit bit clock output (TBCK). TBCK is an input during reset and subsequently is programmed as an output via the AUDIOXMT register (addr 0x2000D00Ch, bit 4).

41 O Sony/Philips Digital Interface audio output (SPDIF).

45 I Audio receive serial data input (RSD); (5V tolerant input).

46 I Audio receive frame sync input (RWS); (5V tolerant input).

47 I Audio receive bit clock input (RBCK); (5V tolerant input).

Auxiliary Port Interface

Basic Auxiliary Port160, 161 I/O Open collectors (AUX0, 1); (5V tolerant input).

162, 165-169 I/O Primary auxiliary port I/Os (AUX2-7); (5V tolerant input).

Auxiliary Port 1 122-128, 131 I/O Auxiliary port 1 data bus I/Os (AUX1[7:0]); (5V tolerant input).

Auxiliary Port 2132-137, 140, 141

I/O Auxiliary port 2 data bus I/Os (AUX2[7:0]); (5V tolerant input).

Auxiliary Port 3117-119, 145, 146, 151-153

I/O Auxiliary port 3 data bus I/Os (AUX3[7:0]); (5V tolerant input).

Auxiliary Port 4142-144, 149, 150, 154, 155,

158I/O Auxiliary port 4 data bus I/Os (AUX4[7:0]); (5V tolerant input).

Camera Port Interface

48 I Camera and YUV input 3 (CAMIN3).

116-119 I Camera and YUV inputs [7:4] (CAMIN[7:4]).

143 I Camera and YUV input 2 (CAMIN2).

151 I Camera and YUV port pixel clock (CAMCLK).

202, 203 I Camera and YUV inputs [1:0] (CAMIN[1:0]).

TDM Interface

25 O Transmit data output (TDMDX).

28 I Receive data input (TDMDR); (5V tolerant input).

29 I Clock input (TDMCLK); (5V tolerant input).

30 I Frame sync input (TDMFS); (5V tolerant input).

31 O Output enable (TDMTSC#).

Video DAC Interface

106 O Chrominance component signal (UDAC) for YUV mode.

108 O Chrominance component signal (CDAC) for Y/C processing.

113 O Luma component signal (YDAC) for YUV mode and Y/C processing.

114 O Composite component signal (VDAC) for YUV mode.


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Compact Flash Interface

122-128, 131-137, 140,

141I/O Host data bus (HD[15:0]).

142 O Host write request output (HWRQ#).

143 O Host read request output (HRRQ#).

144 I/O Aux4 data I/O 0 (AUX4[0]).

145 O Host reset (HRST#).

146 I Host I/O ready input (HIORDY).

149 I/O Host write I/O (HWR#).

150 O Host read output (HRD#).

151 I Host device 16-bit data transfer input (HIOCS16#).

152 O Host chip select output 1 (HCS1FX#).


154, 155, 158 I/O Host address bus (HA[2:0]).

Clock Interfaceand Reset

24 I System reset (RESET#); (5V tolerant input).

29 I TDM clock (TDMCLK); (5V tolerant input).

32, 33, 36, 41 I Clock frequency select PLL outputs (SEL_PLL[3:0]).

39 I/O Audio DAC master clock (MCLK).

40 O Audio transmit bit clock (TBCK).

47 I Audio receive bit clock (RBCK); (5V tolerant input).

49 I 27-MHz crystal clock input (XIN).

50 O 27-MHz crystal clock output (XOUT).

102 O Output clock (DSCK) to SDRAM.

105 I Clock input (DCLK) to PLL; (5V tolerant input).

116 O 27-MHz video pixel clock output (PCLK2XSCN).

117 O 13.5-MHz video pixel clock output (PCLKQSCN).

132 I VFD clock (VFD_CLK).

161 I/O I2C bus clock (I2C_CLK); (5V tolerant input).

Display Interface

106-110, 113-115 O Pixel data outputs (YUV[7:0]).

116 O 27-MHz video pixel clock output (PCLK2XSCN).

117 O 13.5-MHz video pixel clock output (PCLKQSCN).

118 I/O Vertical sync (VSYNC#); (5V tolerant input).

119 I/O Horizontal sync (HSYNC#); (5V tolerant input).

CCIR656 Output PortInterface

106-110, 113-115 I/O CCIR656 output pixels [7:0]; (PIXOUT[7:0]).

173 I/O CCIR656 output pixel clock (PIXOUT_CLK).

Table 2 ES6425 Device Interfaces (Continued)



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EPROM/Flash ROM and RISC Port Interface

2-7, 10-16, 19-23, 204-207

O RISC port address bus (LA[21:0]) to EPROM or Flash memory.

25 I LCS3 ROM boot data width select input (RSEL).

170 O RISC port output enable (LOE#) to EPROM and Flash memory.

173-176 O RISC port chip select outputs (LCS[3:0]) to EPROM or Flash memory.

178-182, 185-191, 194-197

I/ORISC port data bus (LD[15:0]) to EPROM or Flash memory; (5V tolerant input).

198 ORISC port low-byte write enable output (LWRLL#) to EPROM or Flashmemory.

199 ORISC port high-byte write enable output (LWRHL#) to EPROM or Flashmemory.

Filter and Reference Voltage Interface

107 I Video DAC reference voltage input (VREF).

109 I Compensation input (COMP).

Front Panel Display Interface

128 I Front panel data output (VFD_DOUT) to LED display.

131 I Front panel data input (VFD_DIN) to LED display.

132 I Front panel clock (VFD_CLK).

141 I Infrared remote control input (IR); (5V tolerant input).

Host Interface

122-128, 131-137,140, 141

I/O Host data bus (HD[15:0]); (5V tolerant input).

142 O Host write request output (HWRQ#).

143 O Host read request output (HRRQ#).

144 I/O Host interrupt I/O (HIRQ).

145 O Host reset (HRST#).

146 I Host I/O ready input (HIORDY).

149 I/O Host write I/O (HWR#).

150 O Host read output (HRD#).

151 I Host device 16-bit data transfer input (HIOCS16#).



154, 155, 158 I/O Host address bus (HA[2:0]).

I2C Bus Interface160 I/O I2C data I/O (I2C_DATA); (5V tolerant input).

161 I/O I2C clock I/O (I2C_CLK); (5V tolerant input).

IDE Interface



162 I/O I/O write strobe output (IOW#).

165 I/O I/O read strobe output (IOR#).

Memory Stick Interface

117 I/O Aux3 I/O 2 (AUX3[2]) for Memory Stick Serial Clock.

118 I/O Aux3 I/O 1 (AUX3[1]) for Memory Stick Bus State.

119 I/O Aux3 I/O 0 (AUX3[0]) for Memory Stick Card Detect.

142 I/O Aux4 I/O 1 (AUX4[1]) for Memory Stick Serial Data I/O.




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Power and Ground

1, 18, 27, 59, 68, 75, 92, 99, 104, 130, 148, 157, 159, 164, 183,

193, 201

P I/O power supply (VEE).

8, 17, 26, 34, 43, 60, 67, 76, 84, 91,

98, 103, 120, 129, 138, 147, 156, 163, 171, 177, 184, 192,

200, 208

G Ground (VSS).

9, 35, 44, 83, 121, 139, 172

P Core power supply (VCC).

51 P PLL analog power supply (AVEE).

52 G PLL analog ground (AVSS).

112 G Video DAC analog ground (ADVSS).

SD Card Interface

117 I/O Aux3 I/O 2 (AUX3[2]) for SD Card Detect.

118 I/O Aux3 I/O 1 (AUX3[1]) for SD Command.

119 I/O Aux3 I/O 0 (AUX3[0]) to SD Clock.

136, 137, 140, 141

I/O Host data bus I/O (HD[15:12]) for SD Data Bus.

142 O Host write request (HWRQ#) for SD Write Protect.

Smart Media (SM) Card Interface

117 I/O Aux3 I/O 2 (AUX3[2]) for Smart Media Card Enable.

118 I/O Aux3 I/O 1 (AUX3[1]) for Smart Media Card Detect.

132-141 I/O Host data bus (HD[15:8]) to Smart Media Data Bus 7:0.

142 O Host write request (HWRQ#) for Smart Media Card Ready.

150 I/O Host read output (HRD#) for Smart Media Read Enable.

155 I/O Aux4 I/O 3 (AUX4[3]) for Smart Media Address Latch Enable.

158 I/O Aux4 I/O 4 (AUX4[4]) for Smart Media Write Protect.

SDRAM Interface

53-58, 61-66 O DMA address bus (DMA[11:0]).

69 O Memory column address strobe output (DCAS#).

70 O Memory output enable (DOE#); memory clock enable output (DSCK_EN).

71 O Memory write enable output (DWE#).

72 O Memory row address strobe output (DRAS#).

73 O Memory bank select 0 output (DMBS0).

74 O Memory bank select 1 output (DMBS1).

77-82, 85-90, 93-96

I/O Memory data bus (DB[15:0]).

97, 100 O SDRAM chip select outputs (DCS[1:0]#).

101 O Memory data I/O mask output (DQM).

102 O Output clock to SDRAM (DSCK).

Miscellaneous38, 42, 48, 202, 203

— No connect.




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SYSTEM BLOCK DIAGRAM

A sample system block diagram for the ES6425 board design isshown in Figure 2.

Figure 2 ES6425 System Block Diagram

SDRAM(4/16 MB)

AudioDAC

Speakers

EEPROM IR Remote

Video

IDE HDDMemory Cards

ROM/Flash(1 MB)

DMP2ES6425

802.11x, Ethernet

A/V ReceiverS/PDIF

AudioADC


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Figure 3 shows the internal block diagram for the ES6425digital media processor.

Figure 3 ES6425 Block Diagram

ES6425 Device Architecture

The ES6425 device architecture includes a RISCprocessor, CRT controller, transport stream parser, videoencoder, dedicated SRAM and DRAM DMA controllers,on-screen display (OSD) controller, and SIMD DSP.

ESS RISC ProcessorEmbedded in the ES6425 is the 32-bit data pipelined ESSRISC processor, with a combined 16 kb instruction anddata cache subsystem. For applications involving anexternal host processor the communication between a

host processor and the ES6425 is handled by a hostinterface module. The host interface can also be used forhigh speed data input and output.

PMP OperationThe Programmable Multimedia Processor (PMP) core isconsists of the ESS RISC core and the video processorcore. The ESS RISC core and the video processor operatein parallel and have separate data paths and data buses.The data paths and data buses are interconnected by theinternal circuitry in the device architecture.

HuffmanDecoder

SIMDDSP

32-Bit

Serial Audio

Processor

Interface

RISC

16 K Cache

Gateway

+

DMAController

RAM

ROM

Host/ATAPIInterface

Transport

TDMInterface

RSDRWS

RBCKSPDIFTBCKMCLK

TSD[2:0]TWS

TDMCLKTDMDRTDMDXTDMFS

TDMTSC#

HIORDY

HCS[1,3]FX#

HA[2:0]

HIOCS16#

HWR#

HD[15:0]

HRDQ#HWRQ#

HIRQ#HRST#

HRD#DCAS#

DSCK_EN

DQMDCS#[1:0]DMA[11:0]DWE#DOE#DRAS#[2:0]DB[I5:0]

DSCK

CDACVDACUDAC

YDAC

VSYNC#HSYNC#

SRAM/ROMInterface

GPIO

LOE#

LA[21:0]

LD[15:0]LCS#[3:0]

LWRHL#LWRLL#

DRAMInterface

TV-Encoder

Controller

OSDDisplay

IOR#IOW#

PCLK2XSCNPCLKQSCNYUV[7:0]


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RISC CoreThe ESS RISC core can either work alone or with anexternal DSP to supervise the operation of both theinternal SRAM and DRAM DMA controllers. Duringencoding operations, the ESS RISC core can retrievecompressed video data and weave it with audio data toform an output compressed bit stream if the related DMAcontroller does not do so. During decoding operations, theESS RISC core separates and processes the incomingaudio and video data from the bit stream.

The ESS RISC core contains a program count unit,instruction decode unit, execution unit, and register file inits architecture. The program count unit generates aninstruction address signal that identifies the location of a32-bit program instruction. Program instructions, typicallyload and store instructions, include source and destinationinformation, which are passed on to the instruction decodeunit.

The instruction decode unit typically generates specificsignals which select their targeted registers in the registerfile. The decoded instruction has its data sent to theprogram count unit, where it is incremented to the nextdata instruction, or, in the case of a branch instruction,changes the data if a branch condition is met.

The execution unit contains a shifter, an arithmetic logicunit, and a multiplier/divider. The execution unit generatessignal outputs from the respective data signals found inthe register file. These outputs, in turn, are either re-storedin the register file, or asserted as address signals for loadand store operations.

SIMD DSPDuring decoding operations, the SIMD DSP relies on itssoftware to decompress the video data before storing it inmemory. Once the decompressed data has been stored inthe memory, the DRAM DMA controller transfers it to thevideo output interface for final playback to the externalvideo monitor. The ESS RISC processor instruction anddata cache subsystem is organized as a two-way setassociative. On a cache load-miss and write-miss, thecache lines are allocated into the cache memory.

Cache Line OperationBefore cache line operation, the writeback operation maybe performed if the cache content and main memorycontents are different. The ESS RISC performs all powermanagement and system configuration functions for theES6425, as shown in the block diagram in Figure 4.

Figure 4 ESS RISC Block DiagramThe Programmable Multimedia Processor (PMP) coreincludes the proprietary single instruction, multiple data(SIMD) DSP, which can handle four 16-bit-wide datastreams. Also included in the device architecture are ascreen display controller, a digital video encoder with fourDACs, a video input block, video system interfaces, FIFOsand DMA controllers.

The PMP core resource can be accessed only from theESS RISC core. Together, the ESS RISC and the videoprocessor cores form ESS Technology’s field-proven PMPengine.

RISC InterruptsTwelve events can cause interrupts to the ESS RISC.Each event has a status bit to indicate the occurrence ofthe event and an enable bit to mask it from interrupting theESS RISC. Table 3 lists all of the ESS RISC interrupts andthe conditions that cause them.

Table 3 ESS RISC Interrupts

Interrupt GroupCaused ByCondition

How To Clear

Video IRQ

0 Video line number equals value in’videoirq’register

RISC EPROM and SRAM wait states

Timer 0 Timer register wraps from 3FFFFh to 00000h

Writing1 to ‘clrirq’ register bit 3

BCDW 0 DMA Bus Controller Data is waiting to be read after DBUSREAD command

Reading the ‘rlatch’ register

Cmd Empty

0 DMA Bus Controller Command Queue goes empty

Writing a command to ‘cmdque’

H En Idle 1 Huffman Encoder state machine goes idle

Writing 1 to ‘clrirq’ register bit 2

H De Idle 1 Huffman Decoder state machine goes idle

Writing 1 to ‘clrirq’ registerbit 1

Multiplier/Divider Unit

ExecutionUnit

InstructionCache

Data Cache(Writeback)

CacheControl

MemoryInterface

Pwr Mgmt

Timers

To LocalIntDBus


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Command Queue and Video Processor

Command QueueThe command queue module controls the video processormodule. The command queue allows the RISC to bedecoupled from the video processor module by building acommand list of instructions used to control its operation.The command list includes instructions for handling videoprocessor DMA, data transfers, send and receiveinstructions, and waits to receive the current status of thevideo processor.

The depth of the command queue is approximately 64entries. When the command queue is setting up DMAs forthe video processor, the command queue automaticallywrites to DMA channel 0 of the Bus Controller. TheBUSCON_CMDQUE_VPDMASETUP register acceptsthe video processor DMA access requests being routed tothe command queue and prioritizes them in the respectiveorder received. The incoming commands are alwaysexecuted in the order they are written to the queue by the

RISC. Both requests for 7-bit values of delta-Y longwords(DELY[6:0]) and 9-bit values of delta-X scan lines(DELX[8:0]) are processed.

The BUSCON_CMDQUE_VPDMAADDR register storesthe DMA addresses of the incoming commands so that thecommand can be decoded when execution takes place.

The BUSCON_CMDQUE_STATUS register constantlymonitors the status of the command queue. The commandqueue of the ES6425 receives its DMA inputs from two ofthe three key bus controller registers.

Video ProcessorThe video processor consists of a programmable SIMDengine and 2 kb of internal cache memory. The videoprocessor module performs instruction processing for fourtypes of instructions:

• memory instructions

• conditional branch instructions

• compute instructions

• compute immediate instructions.

The video processor executes macroblock level tasks,such as predictive coding, motion estimation, and motioncompensation. The video processor can also be used fora wide range of time-critical signal processing tasks,including audio decoding and both video pre-processingand post-processing.

The video processor enables the ES6425 to performarbitrary vertical filtering and scaling of outgoing video.The video processor is controlled by 32-bit and 16-bit widedual issue micro-instructions. Commonly used microcodesubroutines are stored in 8 kB of internal microcode ROM,while less frequently used microcode segments can bedownloaded on demand to 2 kB of internal microcodeRAM.

DMA Controller

The DMA bus controller is controlled by the videoprocessor and controls multiple DMA channels for thetransfer of 32-bit data between:

• video data bus and memory

• video decoder and memory

• ESS RISC and memory

• ESS RISC and video data bus.

Writes from the ESS RISC to the video processorcommand bus are also performed by the DMA buscontroller, along with waits on status readback from thevideo processor status bus. A separate DMA channel isused for memory refresh. To improve memory bandwidthutilization, internal gateway FIFOs are used extensively.

Data Transfer

1 Either Host-to-RISC Data TRE or RISC-to-Host DW (Host can select)

TRE cleared when RISC reads data; DW cleared when RISC writes data

Block Done

1 After DMA controller has read six blocks of RLAs from VP to DRAM

Write any data to ‘clrhmade’ register

Cmd Half-Empty

2 DMA Bus Controller Command Queue is less than or equal to half full

Write commands to ‘cmdque’ so queue becomes over half full

Debug 2 DEBUGIRQ pin goes high

DEBUGIRQ pin goes low

FIFO Level

2 Either Encoder Output FIFO or Decoder Input FIFO reach certain fullness

Writing 1 to bit 8 of ‘mipctlreg’ register

Host to RISC

2 Host sets Host-to-RISC interrupt bit 7 of ‘HostControl0’ register (Host address 2)

Writing 1 to bit 0 of ‘mipctlreg’ register

Table 3 ESS RISC Interrupts (Continued)

Interrupt GroupCaused ByCondition

How To Clear


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The DMA controller includes two registers in the devicearchitecture that interface directly to the video processor.The BUSCON_VP_CONTROL register performs all videoprocessor m ic rocode load ing and rese t . TheBUSCON_VP_STAT register provides the status of theinternal command queue of the video processor whilemonitoring the status of all sequencing, data transfers andI/O states.

Transport Stream Parser

The ES6425 incorporates a micro-programmable systemdemultiplexer capable of handling MPEG-1 systemstream, MPEG-2 program stream, MPEG-2 transportstream, and other proprietary system multiplexes. Thetransport mechanism contains a 32-entry packet ID tableand satisfies the transport requirements of the DVBstandard.

The transport stream parser performs parsing of allpacketized elementary streams (PESs) and selects thedestinations for all of the audio and video elements in agiven bit stream for processing by the ESS RISC engine.Each PES has a packet ID (PID) table, which includes a4-bit destination field.

The transport stream parser determines the destination ofthe elements so that the ESS RISC engine knows whereto send the final data output after processing. Afterprocessing, the transport stream parser also performsdata flushing of all the buffer FIFOs in the device.

Output CRT ControllerThe video output timing of the ES6425 is controlled by apixel clock and the horizontal and vertical sync signals.Pixels are clocked out of the ES6425 by the pixel clock.The sync signals determine when the active video data istransferred.

Video MPEG DecoderThe ES6425 MPEG decoder module performs bothMPEG-1, MPEG-2, and MPEG-4 decoding. A high-speedHuffman engine decodes the MPEG Variable LengthCodes (VLC), using built-in MPEG-1 and MPEG-2 VLCtables. A programmable RAM-based table controlsautomatic switching from one VLC table to the next.

During decoding, the ESS RISC processor parses theMPEG data all the way down to the macroblock level. Aspecial start code search engine is used to locate the nextMPEG start code. The macroblock address increments,macroblock mode, and motion vectors, which are encodedin VLC, are read from the non-Run Length Amplitude(NRLA) FIFO, one of the two FIFOs of the Huffmanengine. RLA data that constitutes the DCT coefficients aredirectly transferred to the SIMD DSP.

The RISC processor then orchestrates the transfer ofprediction macro block data to the SIMD DSP and theexecution of various SIMD DSP micro-codes routines,including de-quantization, inverse DCT, and motioncompensation. The resulting reconstructed blocks aretransferred under RISC control back to the DRAM framebuffer for subsequent post-processing and display.

NTSC/PAL Video Encoder

The NTSC/PAL video encoder accepts digital linearCCIR656/601 YCbCr at the standard (13.5 MHz) pixeldata rate. Various color space conversion modes areprovided to match the input data to the required outputformat. The data is then filtered to limit the bandwidth ofthe signals to within the supported ranges of the selectedvideo standard.

The output of the encoder is fed directly into the outputFIFO. The ESS RISC is also capable of writing variablelength data into the FIFO in order to insert anynon-TCOEFF parts into the bitstream. The RISC writesvariable length data to the output FIFO up to 10 bits at atime. Smaller tokens can be written by right justifying fewerbits in the least significant bits of the data field. Since theoutput FIFO is shared between the ESS RISC and theencoder, the ESS RISC should only write to it when theencoder is idle.

The encoder generates all the necessary synchronizationsignals for NTSC and PAL standards, which are insertedinto the composite and luma outputs. Digital syncs arealso provided for the rest of the system. The encoder alsogenerates the corresponding sub-carrier frequency forcolor encoding. The encoder generates pixels at bothsquare and nonsquare pixel data rates.

These measurements assume internal 2x and 4x pixeldata rate clock sources. Most of the processing isperformed at a 2x pixel rate. The output rate is at a 4x pixelrate, which allows the output filtering to consist of a fewpassive components.

The encoder is a mixed digital/analog design whichincorporates four 10-bit video DACs in the devicearchitecture. This level of video DAC incorporation allowsthe ES6425 to generate composite, luma, and chromaoutputs both in Y/C and YUV modes. The S-video lumaand chroma outputs are summed internally to generate thecomposite video output in Y/C mode.

All filtering of the luminance and chrominance signals isperformed using DSP techniques. The fi l ters areprogrammable so that the encoder can provide enhancedbandwidth video for S-video output, but can also providecorrectly band-limited signals for composite NTSC/PAL.The sync:white ratio is 40:100 IRE for NTSC, and 43:100IRE or 34:100 IRE for PAL.


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Progressive ScanThe ES6425 supports the progressive scan reconstructionprocess as well as interlaced video for the NTSC and PALformats during video playback. The ES6425 supports bothbaseline and progressive JPEG decoding.

In order to show a progressive image, the CRT controllerof the ES6425 is driven to generate and refresh the scanlines used to create the active display at a rate double thatof the refresh speed used by the NTSC system in order todraw an entire frame in the same amount of time it takesto draw a single field.

The progressive scan features of the ES6425 make thefaster screen refresh possible, allowing for a flicker-freepicture of superior quality to be displayed during videoplayback, while also reducing the number of scan linesvisible to the unaided eye.

Unlike interlaced video, every scan line of a complex videoframe is refreshed when using progressive scan. Sincethe reconstruction process of de-interlaced video is adigital process, the reconstruction process is a losslessone during A/D and D/A conversion of the bitstream.

On-Screen Display ControllerThe 8-bit On-Screen Display (OSD) controller providesdisplay support for 256 palletized colors in eight degreesof transparency and can occupy the entire viewable areaof a display or a portion of the display, depending on thesystem design. The OSD bitmap, which is stored in thereference memory, is multiplexed into the output videostream before color space conversion is performed.

The ES6425 performs its 3-bit blending of the on-screendisplay information when the LDMD bit (bit 2) of theVID_SCN_OSD_MISC register is set, enabling bits 2:0 ofthe VID_SCN_OSD_PALETTE registers to establish thedesired blending value for the different types of pixelmodes required.

The setting of MODE bits 1:0 in the VID_SCN_OSD_MISCregister determine the level of blending. Bit 3 of all theVID_SCN_OSD_PALETTE registers enable the actualblending when set at 0. Modes 1 (2 bit/pixel), 2 (4bits/pixel) and 3 (8-bit/pixel) are supported.

For mode 3 (8-bit/pixel), the upper four bits of the pixel arethe blend information, while the lower four bits of the pixelare the palette index and the blend information in thepalette is ignored.

Device Interfaces

Audio InterfaceThe audio interface is a bidirectional serial port thatconnects to an external audio ADC/DAC for the transfer ofPCM (pulse coded modulation) audio data in I2S format. Itsupports 16-, 24-, and 32-bit audio frames. No externalmaster clock is required.

The ES6425 offers three audio interface modes:

1. Stereo mode using TSD0 on pin 33.

2. 5.1 channel mode using TSD[2:0] on pins 37, 36, and 33.

3. 5.1 channel mode using S/PDIF on pin 41.

The ES6425 audio mode configuration is selectable,allowing it to interface directly with low-cost audio DACsand ADCs. The audio port provides a standard I2Sinterface input and output and S/PDIF (IEC958) audiooutput.

Stereo mode is in I2S format while 5.1 channel audiooutput can be channeled through both the I2S interfaceand the S/PDIF. The S/PDIF interface consists of abi-phase mark encoder, which has low skew.

The transmit I2S interface supports the 128, 192, 256, 384,and 512 sampling frequency formats, where samplingfrequency Fs is usually 32 kHz, 44.1 kHz, 48 kHz, 96 kHz,or 192 kHz. The audio samples for the I2S transmitinterface can be 16, 18, 20, 24, and 32-bit samples.

For Linear PCM audio stream format, the ES6425supports 48 kHz and 96 kHz. The ES6425 incorporates abui l t- in programmable analog PLL in the devicearchitecture in order to generate a master audio clock.

The MCLK pin is for the audio DAC clock and can eitherbe an output from or an input to the ES6425. Audio dataout (TSD) and audio frame sync (TWS) are clocked out ofthe ES6425 based on the audio transmit bit clock (TBCK).Audio receive bit clock (RBCK) is used to clock in audiodata in (RSD) and audio receive frame sync (RWS).

Host Interface The host interface of the ES6425 allows communicationbetween the RISC and an external host, and is comprisedof three ports. Two of these ports are the 8-bit wide debugand command ports, with the third being the 16-bit wideDMA port. The command port transfers control and statusinformation between the host and the ES6425. Theexternal host controls the ES6425 through the commandport.


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The debug port provides a path to the RISC core fordebugging purposes. This allows programmers access tothe state of the hardware and the software withoutdisturbing the command or DMA ports.

The DMA port transfers data to be multiplexed with theaudio and video data in an encoded bitstream. Thismechanism allows applications such as file transfers tooccur. Additionally, the DMA port can carry both the audioand the encoded bitstream.

The host interface has two registers that control theoperation of the flags and interrupts, R_HOSTRQSTATand R_HOSTMASK fo r the R ISC s ide andH_HOSTRQSTAT and H_HOSTMASK for the host side.Flags indicate the readiness of the ES6425 to accept orsupply data over the host interface DMA channel.Interrupts may be used for exception indication fromRISC-to-host or from host-to-RISC. The interrupts aremaskable.

The pulse width high times of the HRRQ# and HWRQ#signals are defined as minimum values only. Themaximum values of these parameters are softwaredependent. The internal DMA channel bandwidth dependsupon the presence of other DMA operations in theES6425.

Memory InterfaceThe ES6425 provides a glueless 16-bit interface to DRAMmemory devices used as video memory for videoplayback. The maximum amount of memory supported is16 MB of Synchronous DRAM (SDRAM). The memoryinterface is configurable in depth to support 128-Mbaddressing.

The memory bus interface generates all the controlsignals to interface with external memory. The ES6425supports different configurations using the memoryconfiguration bits SDCFG[1:0] (bits 12:11), the SD8BIT bit(b i t 14 ) , and SD64M b i t (b i t 15) i n theBUSCON_DRAM_CONTROL register. Configurationscan be implemented in many ways. Table 4 lists the typicalSDRAM configurations used by the ES6425.

The memory interface controls access to both externalSDRAM or EDO memories, which can be the sole unifiedexternal read/write memory acting as program and datamemory as well as various decoding and display buffers.At high clock speeds, the ES6425 memory bus interfacehas sufficient bandwidth to support the decoding anddisplaying of CCIR656/601 resolution images at full framerate.

SDRAM Considerations

The ES6425 uses SDRAM with a programmed CAS#latency of three clocks (CL=3) and sequential burst of fullpage length. Performance based on SDRAM is doublethat of EDO. SDRAM must be software configured beforeany memory access. The programmable SDRAM refreshperiod can be modified to meet any desired configuration.

SDRAM Address Mapping

The memory address (LA) is mapped to the DMA address,which is formed by ADDR in the BUSCON_DMA_ADDRregisters. The result is then converted into the DRAMcontrol signals using the SDCFG[1:0] configuration bits(b i ts 12 :11) and the SD8BIT b i t (b i t 14) in theBUSCON_DMA_CONTROL register.

SDRAM Configuration Requirements

Table 5 lists the SDRAM memory size configurations, eachwith its corresponding signal pins.

Table 4 Typical SDRAM Configurations

Mem.Size(MB)

Bit Order Memory Configuration

(Mb per pc)SD64M SD8BIT SDCFG1 SDCFG0

2 0 0 0 11 pc: 512K

x16x2 (16 Mb)

4 0 0 0 02 pcs: 512K

x16x2 (16 Mb)

4 0 1 0 12 pcs: 1M

x8x2 (16 Mb)

8 0 1 0 04 pcs: 1M

x8x2 (16 Mb)

8 1 0 X X1 pc: 1M

x16x4 (64 Mb)

16 1 0 X X2 pc: 1M

x16x4 (64 Mb)

16 1 1 X X2 pc: 2M

x8x4 (64 Mb)

16 1 1 X X1 pc: 2M

x16x4 (128 Mb)

Table 5 SDRAM Configurations and Signal Pins

Size(MB)

SDRAM0

SDRAM1

SDRAM2

SDRAM3

SDRAMType

2

DCAS#DRAS0#DCS0#DB[0:15]

— — —512Kx16x2

(16 Mb)

4



— —512Kx16x2

(16 Mb)

Table 4 Typical SDRAM Configurations (Continued)


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Storage Device Interfaces The ES6425 supports the AT Attachment Packet Interface(ATAPI), Compact Flash (CF), Integrated Drive Electronics(IDE), Memory Stick (MS), SD and Smart Mediainterfaces.

ATA/IDE Interface

The host interface directly supports ATAPI devices withPIO modes. The ATA/IDE interface can directly control twodevices through the use of the HCS1FX# and HCS3FX#signals. The ATA/IDE interface of the ES6425 uses acommand execution protocol that allows for the operationof hard disk drives.

Table 6 lists the packet commands and the respectivecommand codes for ATAPI devices, as specified bySFF-8090i.

Compact Flash Interface

The ES6425 provides True IDE Mode I/O support for theCompact Flash storage card interface found on a varietyof removable storage cards used by digital cameras andMP3 players. The ES6425 uses its host interface tocommunicate with Compact Flash devices.

4



— —1M

x8x2(16 Mb)

8





1Mx8x2

(16 Mb)

8


— — —1M

x16x4(64 Mb)

16



— —1M

x16x4(64 Mb)

16



— —2M

x8x4(64 Mb)

16


— — —2M

x16x4(128 Mb)

Table 6 Packet Commands for ATAPI DevicesCode Command Name00h TEST UNIT READY03h REQUEST SENSE04h FORMAT UNIT12h INQUIRY1Bh START/STOP UNIT1Eh PREVENT/ALLOW MEDIUM REMOVAL

Table 5 SDRAM Configurations and Signal Pins (Continued)

Size(MB)

SDRAM0

SDRAM1

SDRAM2

SDRAM3

SDRAMType

23h READ FORMAT CAPACITIES25h READ CAPACITY28h READ (10)2Ah WRITE (10)2Bh SEEK2Eh WRITE AND VERIFY (10)2Fh VERIFY (10)35h SYNCHRONIZE CACHE42h READ SUBCHANNEL43h READ TOC/PMA/ATIP44h READ HEADER45h PLAY AUDIO (10)46h GET CONFIGURATION47h PLAY AUDIO MSF4Ah GET EVENT/STATUS NOTIFICATION4Bh PAUSE/RESUME4Eh STOP PLAY/SCAN51h READ DISC INFORMATION52h READ TRACK/RZONE INFORMATION53h RESERVE TRACK/RZONE54h SEND OPC INFORMATION55h MODE SELECT (10)58h REPAIR RZONE5Ah MODE SENSE (10)5Bh CLOSE TRACK/RZONE/SESSION/BORDER5Dh SEND CUE SHEETA1h BLANKA2h SEND EVENTA3h SEND KEYA4h REPORT KEYA6h LOAD/UNLOAD MEDIUMA7h SET READ AHEADA8h READ (12)AAh WRITE (12)ACh GET PERFORMANCEADh READ VIDEO STRUCTUREB6h SET STREAMINGB9h READ CD MSFBAh SCANBBh SET CD SPEEDBCh PLAY CDBDh MECHANISM STATUSBEh READ CDBFh SEND VIDEO STRUCTURE

Table 6 Packet Commands for ATAPI Devices (Continued)

S Technology, Inc. SAM0530-082704 23

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By implementing Compact Flash support, the ES6425 canreadily detect the insertion and removal of a CompactFlash card, which also constitutes a hot-swapping event.During a hot-swapping event, the CARD_DETECT signalis asserted by the Compact Flash, allowing it to determinethe presence of the removable storage card fully insertedinto its socket.

The ES6425 permits both 8- and 16-bit common memoryI/O accesses with a removable storage card via the hostinterface. Table 7 lists the CF-ATA command set.

Memory Stick Interface

The ES6425 supports recording and playback of digitalmedia in the Memory Stick audio and still image fileformats.

This type of media can be applied to many types ofdevices, including but not limited to, MP3 players anddigital still cameras. Figure 5 depicts a basic Memory Stickdevice module.

Figure 5 Basic Memory Stick Hardware Interfaces

More detailed Memory Stick specifications and informationcan be found at the Memory Stick Technical Supportwebsite at http://www.memorystick.org.

Memory Stick Addressing

The ES6425 supports cluster-style addressing when datais being stored to a Memory Stick device, which makes thedata as accessible from the device as it would be from ahard disk drive.

System SRAM InterfaceThe system SRAM interface controls access to optionalexternal SRAM which can be used for RISC code, stack,and data. The SRAM bus supports four independentaddress spaces, each having programmable bus widthand wait states. The interface can support not only SRAMbut also ROM/EPROM and memory-mapped I/O ports forstandalone applications.

The ES6425 inserts from 1 to 32 wait states into eachcycle, with each wait state being one clock cycle long.When switching from a low speed bank to a high speedbank, the turnoff delay of the low speed bank can overlapthe first access of the high speed bank. To prevent datacorruption, the bank select delay time is programmable foreach SRAM bank from 0 to 3T states.

The signals for the SRAM bus are generated from theinternal RISC clock and are timed in integer multiples ofclock cycles, except for the write strobe, which is delayedby one-half cycle from the address setup and advancedone-half cycle from the start of the next access cycle.

Table 7 CF-ATA Command Set

Class Command Code1 CHECK POWER MODE E5h or 98h1 EXECUTE DRIVE DIAGNOSTIC 90h1 ERASE SECTOR(S) C0h1 IDENTIFY DRIVE ECh1 IDLE E3h or 97h1 IDLE IMMEDIATE E1h or 95h1 INITIALIZE DRIVE PARAMETERS 91h1 READ BUFFER E4h1 READ LONG SECTOR 22h or 23h1 READ MULTIPLE E4h1 READ SECTOR(S) 20h or 21h1 READ VERIFY SECTOR(S) 40h or 41h1 RECALIBRATE 1Xh1 REQUEST SENSE 03h1 SECURITY DISABLE PASSWORD F6h1 SECURITY ERASE PREPARE F3h1 SECURITY ERASE UNIT F4h1 SECURITY FREEZE LOCK F5h1 SECURITY SET PASSWORD F1h1 SECURITY UNLOCK F2h1 SEEK 7Xh1 SET FEATURES EFh1 SET MULTIPLE MODE C6h1 SET SLEEP MODE E6h or 99h1 STAND BY E2h or 96h1 STAND BY IMMEDIATE E0h or 94h1 TRANSLATE SECTOR 87h1 WEAR LEVEL F5h2 FORMAT TRACK 50h2 WRITE BUFFER E8h2 WRITE SECTOR(S) 30h or 31h2 WRITE LONG SECTOR 32h or 33h2 WRITE SECTOR(S) W/O ERASE 38h3 WRITE VERIFY 3Ch3 WRITE MULTIPLE C5h3 WRITE MULTIPLE W/O ERASE CDh

courtesy of memorystick.org


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The on-chip SRAM also allows the ESS RISC core todownload subroutines for the video processor core. TheESS RISC core activates the video processor core bywriting to the command queue, which selects a subroutineeither from the external EPROM, flash memory or by thevideo memory interface.

TDM InterfaceThe ES6425 implements a high-speed, bidirectional serialbus known as a TDM interface that supports a number ofhigh-speed serial protocols. The TDM interface can alsoact as a general-purpose 16-Mbps serial link when notconstrained by TDM protocols.

The TDM interface provides an easy connection betweenthe ES6425 and available communications chips. TheTDM interface is a time-division-multiplexed bus thatmultiplexes byte data on up to 64 channels. Time slot 0starts after N (which can be set in the XMT/RCVDELAYregister) clocks after the frame starts.

Each slot is eight clock periods long, and either transmitsor receives byte data during a write cycle or a read cycle.Immediately after slot 0 completes, slot 1 starts and so on.Each channel is allocated a different time slot on the bus,and the ES6425 can be set to send and receive data in anycombination of different time slots.

Data is assumed to be ordered by time slot; e.g., if timeslots 6, 8, and 17 are used, the first DMA byte sent tomemory would be in time slot 6, followed by time slots 8and 17 in order. All DMA byte reordering is done insoftware. The interface consists of frame sync signalTDMFS, data transmit and receive signals TDMDX andTDMDR, external buffer enable signal TDMTSC# and bitclock signal TDMCLK.

The timing of the data transfer is externally controlled. TheTDM interface can support a number of different timings.The TDM interface can transfer data at a maximum rate of16 Mbps, with a more typical configuration supporting adata rate of up to 4.096 Mbps with a frame sync frequencyof 8 kHz. The TDM interface programmability includesindependent receive, transmit, and frame sync clock edgeselection and independent receive and transmit dataoffsets.

Vacuum Fluorescent Display Controller InterfaceThe ES6425 provides hardware support for the vacuumfluorescent display (VFD) controller interface in DMPplayer designs. The VFD_CTRL register is programmedby the software for supporting the control and formatfunctions in the first access, and enables the interface inthe second access.

The VFD_DATA register, along with the AUX_MODEregister, both act as containers for an external VFD deviceto read data from it and write VFD clock and data to it

during normal operations. The SYS_STATUS register andthe IR_DIFF register provide additional hardware supportfor remote control operations.

Video Interface

Video Display OutputThe video output section controls the transfer of videoframes stored in memory to the internal TV encoder of theES6425. The output section consists of a programmableCRT controller capable of operating either in Master orSlave mode.

Figure 6 shows the display timing on the screen.

Figure 6 Video Output Timing

The video output section features internal line bufferswhich allow the outgoing luminance and chrominancedata to match the internal clock rates with external pixelclock rates, easily facilitating YUV4:2:2 to YUV4:2:0component and sample conversion. Arbitrary horizontaldecimation and interpolation is achieved by a polyphasefilter.

Together with programmable line dropping/duplicationcircuitry and micro-code based post-processing runningon the video processor, the ES6425 is capable ofarbitrating image conversion. Examples include SIF toCCIR656/601, letter-box, NTSC to PAL, and PAL to NTSCconversions.

Video BusThe ES6425 video bus transfers digital video pixels out ofthe chip. In standalone applications the video bus will beconnected to a monitor or an LCD panel. In workstationapplications, the output bus will feed an overlay circuit sothat the output video appears in a window of the GraphicalUser Interface (GUI).

0,0

vblank

HSYNC

vsync

hsyncwidth

start

vstart

vend

vsyncperiod

vblankstop

vsyncwidth

hsyncperiod

MainWindow

hblankstophstart

hend

hblankstart

Location 0,0 is the upper left corner of the screen.

OSD

Active DisplayArea


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The video bus has 8 YUV data pins that transferluminance and chrominance (YUV) pixels in CCIR656/601pixel format (4:2:2). In this format, there are half as manychrominance (U or V) pixels per line as luminance (Y)pixels; there are as many chrominance l ines asluminance.

Video Post-ProcessingThe ES6425 video post-processing circuitry providessupport for the color conversion, scaling, and filteringfunctions through a combination of special hardware andsoftware. Horizontal up-sampling and filtering is done witha programmable, 7-tap polyphase filter bank for accuratenon-integer interpolations. Vertical scaling is achieved byrepeating and dropping lines in accordance with theapplicable scaling ratio.

Figure 7 shows the video post-processing functionalblocks. The first two processing steps are performed bythe video processor core. Video post-processing can beapplied on the decoded images to improve the picturequality.

The next stage in the processing, applicable only to lowresolution MPEG-1 video, is an interlacing filter thatgenerates even and odd fields from decoded frames forapplications that use a TV screen. The filter improves boththe spatial and temporal appearance of the decodedimages on interlaced displays.

Figure 7 Video Post-ProcessingFollowing the interlacing filter is an interpolation sectionthat uses bilinear interpolation to increase the resolution ofthe chrominance components by a factor of two in thevertical dimension. This interpolation section convertsfrom the MPEG chrominance subsampling to that used byCCIR656/601.

The resulting YUV pixels can then be passed through a7-tap horizontal interpolation filter that increases thehorizontal resolution of the image by up to four times. The

horizontal filter automatically chooses between five sets offilter coefficients based on the fractional component of thenew position of the pixel in the video data stream.

The filter coefficients are 8 bits wide. The filter length isselectable as 1, 3, 5, or 7 taps. The relationship betweenthe doubled pixel clock PCLK2XSCN and the internal ESSRISC clock is listed in Table 8.

Video TimingThe video bus can be clocked either by double pixel clockand clock qualifier or by a single pixel clock. The doubleclock typically is used for TV displays, the single forcomputer displays. PCLKQSCN is ignored in 1x clockmode. The timing of the syncs and odd/even fieldindication is shown in Figure 8 and Figure 9.

The output video field indication is done by modifying therelative positions of VSYNC and HSYNC. At the start of aneven field, the horizontal and vertical sync pulses will starton the same clock edge; in odd fields the horizontal syncpulse will be delayed by one clock cycle. The polarity ofboth horizontal and vertical syncs is programmable.

Figure 8 Horizontal Video Timing

Figure 9 Vertical Video Timing

Output

OSD

HorizontalUV VerticalInterlacing

VerticalPost-processing

DRAM

OSD data from DRAM

Vertical scale up

Horizontal scale upYUV 4:2:2Generate

Interpolate

Filter Interpolate Interpolate

Hardware

Improve

by up to 4 timesvertical onlyInterlaced fields

FrameBuffer

by any amountimage quality

Video Processor Core

Table 8 ESS RISC Clock Relationship to Pixel Clocks

Taps Restrictions Frequency

3 Pixel rate < (Internal RISC CLK)/2 27-MHz

5 Pixel rate < (Internal RISC CLK)/3 20-MHz

7 Pixel rate < (Internal RISC CLK)/4 Default 13.5-MHz

PCLKQSCN

HSYNC#Min 128 pixels, max 4095 pixels

Min 4 pixels

HSYNC#

VSYNC#Min 8 lines, max 4095 lines

Min 2 lines


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REGISTERS

Host Interface Host Side Registers

This section describes the host interface host sideregisters of the ES6425.

H_HOSTDMAPORT (0x0, R/W)

The Host Side DMA Port register contains memory and I/Odata transferred to and from the RISC. After reset, thisregister initializes to 0x0000.

H_HOSTVCXPORT (0x1, R/W)

The Host Side Command Port register contains controland status data transferred to and from the RISC. Afterreset, this register initializes to 0x00.

H_HOSTDBGPORT (0x2, R/W)

The Host Side Debug Port register transfers data to andfrom the RISC during debugging. After reset, this registerinitializes to 0x00.

H_HOSTCTL (0x3, R/W)

The Host Side Control register enables and disables thehost-to-RISC and RISC-to-host interrupt capabilities of theES6425. After reset, this register initializes to 0x00.

Bit Definitions:

H_HOSTMASK (0x4, R/W)

The Host Side Interrupt Mask register initializes to 0x00after reset.

Bit Definitions:

HOST INTERFACE (DMA PORT) DATA

15:0

HOST INTERFACE (COMMAND PORT) DATA

7:0

HOST INTERFACE (DEBUG PORT) DATA

7:0

H2R_IRQ OSEL ISEL CLR_RIRQ

7 6:4 3:1 0

Bits Name Description

7 H2R_IRQ Host to RISC IRQ Enable. Writing a 1 to this bit sets the host to RISC IRQ flag.

6:4 OSEL Select which TRE and DW bits are sent to the HRRQ read request pins.HRRQ = (DMA_DW and OSEL_0) or(VCX_DW and OSEL_1) or(DBG_DW and OSEL_2).

3:1 ISEL Select which TRE and DW bits are sent to the HWRQ (write request) pins.HWRQ = (DMA_TRE and ISEL_0) or(VCX_TRE and ISEL_1) or(DBG_TRE and ISEL_2).

0 CLR_RIRQ

RISC-to-Host IRQ Clear. Writing a 1 to this bit clears the RISC To Host IRQ.

ENDN_SEL

DBG_TRE

DBG_DW

DMA_TRE

DMA_DW

VCXI_TRE

VCXI_DW

R2R_IRQ

7 6 5 4 3 2 1 0


7 ENDN_SEL

Host Side Endian Select. When set, this bit switches the upper and lower bytes of data sent as writes to the Host Interface DMA Port register.1 = switch upper/lower bytes.

6 DBG_TRE

Host To RISC Debug Transmit Register Empty Flag.

5 DBG_DW

RISC To Host Debug Data Waiting Flag1 = Host ready to read debug data from ESS

RISC.

4 DMA_TRE

Host To RISC DMA Transmit Register Empty Flag.1 = Host ready to send DMA data to ESS RISC.

3 DMA_DW

DMA data waiting1 = Host waiting to read data from ESS RISC.

2 VCXI_TRE

VCXI transmit register empty 1 =Host ready to send data to ESS RISC.

1 VCXI_DW

VCXI data waiting 1 = Host waiting to read data from ESS RISC.

0 R2R_IRQ

Interrupt flag 1 = Set by ESS RISC as Ready To Receive

signal to the host.



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H_HOSTIRQSTAT (0x5, R)

The read-only Host Side Host Interrupt Status registerreads the status of Interrupts from the ESS RISC to thehost (1 = IRQ present, 0 = No IRQ present).

Bit Definitions:

Video Interface Registers

This section describes the video interface registers of theES6425.

Video Output Registers

VID_SCN_HSTART (0x20001000h, W)

The write-only Video Screen Horizontal Start Addressregister contains the 13-bit horizontal pixel startingaddress of the active video display.

Bit Definitions:

VID_SCN_HEND (0x20001004h, W)

The write-only Video Screen Horizontal End Addressregister contains the 13-bit horizontal pixel ending addressof the active video display.

Bit Definitions:

VID_SCN_VSTART (0x20001008h, W)

The write-only Video Screen Vertical Start Addressregister contains the 13-bit vertical scan line startingaddress of the active video display.

Bit Definitions:

VID_SCN_VEND (0x2000100Ch, W)

The write-only Video Screen Vertical End Address registercontains the 13-bit vertical scan line ending address of theactive video display.

Bit Definitions:

H2R_IRQ

DBG_TRE

DBG_DW

DMA_TRE

DMADW

VCXI_TRE

VCXI_DW

R2H_IRQ

7 6 5 4 3 2 1 0


7 H2R_IRQ

Host To RISC Interrupt Flag. Set by the host as a signal to the RISC to generate an interrupt.

6 DBG_TRE

Host To RISC Debug Transmit Register Empty Flag. When set, host sends data to the RISC.

5 DBG_DW

Host To RISC Debug Data Waiting Flag. When set, host can read data from the RISC.

4 DMA_TRE

Host To RISC DMA Transmit Register Empty Flag. When set, host sends data to the RISC.

3 DMA_DW

Host To RISC DMA Data Waiting Flag. When set, host reads DMA data from the RISC.

2 VCXI_TRE

VCXI transmit register empty (OK for host to send data to the RISC).

1 VCXI_DW

VCXI data waiting (host needs to read data from the RISC).

0 R2H_IRQ

Interrupt flag set by the RISC as a signal to the host.

— HSTART

15:13 12:0


15:13 — Reserved.

12:0 HSTART Horizontal starting address of active window.

— HEND

15:13 12:0


15:13 — Reserved.

12:0 HEND Horizontal ending address of active window.

— VSTART

15:13 12:0


15:13 — Reserved.

12:0 VSTART Vertical scan line starting address of active window.

— VEND

15:13 12:0


15:13 — Reserved.

12:0 VEND Vertical scan line ending address of active window.


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VID_SCN_VERTIRQ (0x20001010h, W)

The write-only Video Screen Vertical Line Interruptregister is selectable by software and contains the line inwhich a vertical interrupt will occur. Line 0 is the top of thescreen, as defined by the leading edge of the VSYNC pin.Typically, an interrupt is set either just before or just afterthe active video display.

Bit Definitions:

VID_SCN_HBLANK_START (0x20001014h, W)

The write-only Video Screen Horizontal Blanking IntervalStart Address register contains the 13-bit starting addressof the horizontal blanking interval for the active videodisplay.

Bit Definitions:

VID_SCN_HBLANK_STOP (0x20001018h, W)

The write-only Video Screen Horizontal Blanking IntervalEnd Address register contains the 13-bit ending addressof the horizontal blanking stop interval for the active videodisplay.

Bit Definitions:

VID_SCN_VBLANK_START (0x2000101Ch, W)

The Video Screen Vertical Blanking Interval Start Addressregister contains the 13-bit starting address of the verticalblanking interval for the active video display.

Bit Definitions:

VID_SCN_VBLANK_STOP (0x20001020h, W)

The write-only Video Screen Vertical Blanking IntervalStop Address register contains the 13-bit ending addressof the vertical blanking stop interval for the active videodisplay.

Bit Definitions:

VID_SCN_HSYNCWIDTH (0x20001024h, W)

The write-only Video Screen Horizontal Sync Width Pulseregister contains the 13-bit value of the horizontal syncpulse width for the active video display. This register isneeded only if sync direction is output

Bit Definitions:

— VERTIRQ

15:13 12:0


15:13 — Reserved.

12:0 VERTIRQ

Line where a vertical interrupt will occur.

— HBLANK_START

15:13 12:0


15:13 — Reserved.

12:0 HBLANK_START

Starting address of the start horizontal blanking interval.

— HBLANK_STOP

15:13 12:0


15:13 — Reserved.

12:0 HBLANKSTOP

Ending address of the horizontal blanking stop interval.

— VBLANK_START

15:13 12:0


15:13 — Reserved.

12:0 VBLANK_START

Starting address of vertical blanking startinterval.

— VBLANKSTOP

15:13 12:0


15:13 — Reserved.

12:0 VBLANKSTOP

Ending address of the vertical blanking stop interval.

— HSYNCWIDTH

15:13 12:0


15:13 — Reserved.

12:0 HSYNCWIDTH

Horizontal sync pulse width value.


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VID_SCN_HSYNCPERIOD (0x20001028h, W)

The write-only Video Screen Horizontal Sync Periodregister contains the 13-bit value for the period of thehorizontal sync pulse used by the active video display. It isneeded only if sync direction is output.

Bit Definitions:

VID_SCN_VSYNCPERIOD (0x2000102Ch, W)

The write-only Video Screen Video Sync Period registercontains the 13-bit value for the period of the vertical syncpulse used by the active video display. This register isneeded only if sync direction is output.

Bit Definitions:

VID_SCN_VSYNCPIXEL (0x20001030h, W)

The write-only Video Screen Vertical Sync Pixel registerdefines which pixel VSYNC will change on for the activevideo display. The number of pixels delayed from HSYNCthat VSYNC will change on either the rising or falling edgeof VSYNC. This register is needed only if sync direction isoutput

Bit Definitions:.

VID_SCN_VSYNCWIDTH (0x20001034h, W)

The write-only Video Screen Vertical Sync Pulse Widthregister defines the width of the 6-bit vertical sync pulse. Itis needed only if sync direction is output

Bit Definitions:.

VID_SCN_VERTCOUNT (0x20001036h, R)

The read-only Video Screen Vertical Counter registercontains the current line of the vertical counter, and startsits counting at VSYNC line 0. This register is typically usedfor testing only.

Bit Definitions:

VID_SCN_HORIZCOUNT (0x20001038h, R)

The read-only Video Screen Horizontal Counter registercontains the current pixel of the horizontal counter, andstarts its counting at HSYNC pixel 0. This register istypically used for testing only.

Bit Definitions:

— HSYNCPERIOD

15:13 12:0


15:13 — Reserved.

12:0 HSYNCPERIOD

Horizontal sync period.

— VSYNCPERIOD

15:13 12:0


15:13 — Reserved.

12:0 VSYNCPERIOD

Vertical sync pulse period.

— VSYNCPIXEL

15:13 12:0


15:13 — Reserved.

12:0 VSYNCPIXEL

Pixel on which VSYNC will change.

— VSYNCWIDTH

15:6 5:0


15:6 — Reserved.

5:0 VSYNCWIDTH

Vertical sync pulse width.

— VERTCOUNT

15:13 12:0


15:13 — Reserved.

12:0 VERTCOUNT

Current pixel of the vertical counter.

— HORIZCOUNT

15:13 12:0


15:13 — Reserved.

12:0 HORIZCOUNT

Current pixel of the horizontal counter.


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VID_SCN_COUNTER_CTL (0x2000103Ch, W)

The write-only Video Screen Counter Control registercontains counter control bits for the inverted blank sync,inverted horizontal sync, and inverted vertical syncfunctions. This register initializes to 0x00 after reset.

Bit Definitions:

VID_SCN_OUTPUTCNTL (0x20001040h, R/W)

The Video Screen Output Control register contains thecontrol logic used to control the clamping and filteringcharacteristics of the signal being output to the videodisplay.

Bit Definitions:

VID_SCN_ITERFACECNTL (0x20001048h, R/W)

The Video Screen Interface Control register contains thecontrol logic used to determine the signal outputcharacteristics to the video display.

Bit Definitions:

— INVBLNK — INVHS INVVS MSTR MODE

7:5 4 3 2 1 0


7:5 — Reserved.

4 INVBLNK

Inverted blank sync.1 = Blank is active low.0 = Otherwise.

3 — Set at zero.

2 INVHS Inverted horizontal sync.1 = Horizontal sync is active-low.

1 INVVS Inverted vertical sync.1 = Vertical sync is active-low.0 = Otherwise.

0 MSTR MODE

Master Mode Select.1= ES6425 drives sync pins.0= Syncs input to ES6425.

— ZEROB BYPASS 3TAP_EN

COEFLDMD

CLAMP_EN

INVMSB

YUV8BIT

TSMODE

15:9 8 7 6 5 4 3:2 1 0


15:9 — Reserved.

8 ZEROB Zero Boundary.1 = Use zeroes for pixels outside of the

border for horizontal filtering.0 = Use the pixel on the edge.

7 BYPASS Horizontal Filter Bypass.1 = Bypass horizontal filter.0 = Use horizontal filter.

6 3TAP_EN 3/7 Tap Filter Select.1 = 3-tap horizontal filter selected.0 = 7-tap horizontal filter selected.

5 COEFLDMD

0 = UV is selected first.1 = Y is selected first.

4 CLAMP_EN

Clamp Enable.1 = Clamp output according to

CCIR656/601 min/max values.0 = No clamping.

3:2 INVMSB Invert MSB YUV Output.INVMSB[1] = Invert MSB of Y output.INVMSB[0] = Invert MSB of UV output.

1 YUV8BIT 8-bit YUV Output Enable.1 = 8-bit YUV output enabled0 = Invalid.

0 TSMODE Toggle Select Mode.1 = Y is first in 8-bit mode.0 = UV is first in 8-bit mode.

— MM MBM INVHS INVVS INVB 1PE EPU MCK CLKDIV IPQ CK1M

15:12 11 10 9 8 7 6 5 4 3:2 1 0


15:12 — Reserved.

11 MM Master Mode.1 = ES6425 drives sync signals.0 = Slave mode.

10 MBM Master Blanking Mode1 = ES6425 determines blanking region.0 = Slave mode.

9 INVHS Invert Horizontal Sync.1 = Horizontal sync inverted.

8 INVVS Invert Vertical Sync.1 = Vertical sync inverted.

7 INVB Invert Blanking.1 = Blanking interval inverted.

6 1PE First Pixel Even.1 = First pixel of active region is even.

5 EPU Even Pixel U Select.1 = Even pixel is U pixel.0 = Even pixel is V pixel.

4 MCK Master Pixel Clock Mode.1 = ES6425 drives master clock.

3:2 CLK_DIV Clock Divider. This field determines which type of video screen clock ES6425 uses for pixel clocks:


CLK_DIV1

CLK_DIV0 Description

0 0 Screen clock depends on CLK1XMOD (default).

0 1 13.5 MHz screen clock is half of input pixel clock.

1 X 6.75 MHz screen clock is one-quarter of input pixel clock.


ES6425 DATA SHEET

REGISTERS

PRELIMINARY

NDA R

EQ

UIR

ED

VID_SCN_RESETS (0x20001050h, R/W)

The Video Screen Reset register contains the control logicfor reset events, including the reset pan and scan,horizontal filtering and DMA enabling functions. Thisregister is set to 1 on reset.

Bit Definitions:

VID_SCN_STATUS (0x20001058h, R)

The Video Screen Status register contains the status bitsfor the video section.

Bit Definitions:

On-Screen Display Controller RegistersThis section deals with the OSD controller registers of theES6425.

VID_SCN_OSD_HSTART (0x20001110h, R/W)

The OSD Video Screen Horizontal Start Address registercontains the horizontal starting address value for the OSD,as referenced from the active display window.

Bit Definitions:

1 IPQ Invert PCLKQSCN.1 = PCLKQSCN pin inverted.

0 CK1M Clock1X Mode.1 = Use PCLK2XSCN or internal 27 MHz PCLK0 = Use 13.5 MHz PCLKQSCN.

— R_PAN — R_Y R_UV R_HF R_CNT DMAGO

15:8 7 6:5 4 3 2 1 0


15:8 — Reserved.

7 R_PAN Reset Pan and Scan.1 = Reset pan and scan function (default).

6:5 — Reserved. Always 1.

4 R_Y Reset Y FIFO.1 = Reset Y FIFO (default).

3 R_UV Reset UV FIFO.1 = Reset UV FIFO (default).

2 R_HF Reset Horizontal Filter.1 = Horizontal filter reset (default).

1 R_CNT Reset Counter.1 = Counter reset (default)

0 DMAGO DMA Enable.1 = DMA enabled (default).

O_E BLNK HS VS VACT ACT ACTD1 ACTD2

15 14 13 12 11 10 9 8

ACTD3 1P NL NF NP EP UP UPD1

7 6 5 4 3 2 1 0


15 O_E VS/HS Odd or Even Field Status.1 = Odd field.0 = Even field.


14 BLNK Blanking Status.

13 HS Horizontal Sync Status.

12 VS Vertical Sync Status.

11 VACT Vertical Active Status.

10 ACT Active Screen for FIFO.

9 ACTD1 Active Horizontal Filter Signal.1 = Horizontal filtering signal active.

8 ACTD2 Active OSD/Mixer Signal.1 = OSD/Mixer signal active.

7 ACTD3 Active Output Port Signal.1 = Output port signal active.

6 1P First Active Pixel for FIFO.1 = First active pixel selected.

5 NL New Line.1 = First pixel of new line selected.

4 NF New Field.1 = First pixel of new field selected.

3 NP New Pixel.1 = One clock cycle of every pixel clock cycle

selected.

2 EP Even Pixel for FIFO.1 = Current pixel selected for FIFO is even.

1 UP U Pixel Horizontal Filter Select.1 = Current pixel uses U for horizontal filtering.0 = Current pixel uses V for horizontal filtering.

0 UPD1 U Pixel Mixer Select.1 = Current pixel uses U for OSD/Mixer.0 = Current pixel uses V for OSD/Mixer.

— OSD_HSTART

15:13 12:0


15:13 — Reserved.

12:0 OSD_HSTART

OSD horizontal starting address value.



ES6425 DATA SHEET

REGISTERS

PRELIMINARY

NDA R

EQ

UIR

ED

VID_SCN_OSD_HEND (0x20001114h, R/W)

The OSD Video Screen Horizontal End Address registercontains the 13-bit horizontal ending address value for theOSD, as referenced from the active video display.

Bit Definitions:

VID_SCN_OSD_VSTART (0x20001118h, R/W)

The OSD Video Screen Vertical Start Address registercontains the 13-bit vertical starting address value for theOSD, as referenced from the active video display.

Bit Definitions:

VID_SCN_OSD_VEND (0x2000111Ch, R/W)

The OSD Video Screen Vertical End Address registercontains the 13-bit vertical ending address value for theOSD, as referenced from the active video display.

Bit Definitions:

VID_SCN_OSD_MISC (0x20001124h, R/W)

The OSD Video Screen Miscellaneous register containsthe control logic and status bits for the OSD controller.

Bit Definitions:

VID_SCN_OSD_PALETTE (0x20001140h–0x2000117Ch, R/W)

These 16 registers contain the OSD palette.

Bit Definitions:

For mode 3 (8-bit/pixel) the upper 4 bits of the pixel are theblend information, the lower 4 bits are the palette indexand the blend information in the palette is ignored.

Digital Video Encoder RegistersThis section addresses the digital video encoder registersof the ES6425.

DVECTL0 (0x20001300h, R/W)

The DVECTL0 register is the control register for the digitalvideo encoder module of the ES6425.

— OSD_HEND

15:13 12:0


15:13 — Reserved.

12:0 OSD_HEND

OSD horizontal ending address value.

— OSD_VSTART

15:13 12:0


15:13 — Reserved.

12:0 OSD_VSTART

OSD vertical starting address value.

— OSD_VEND

15:13 12:0


15:13 — Reserved.

12:0 OSD_VEND

OSD vertical ending address.

LAT_INT RESET_OVERLAY PAL_INDEX INTEN LDMD MODE

7 6 5:4 3 2 1:0


7 LAT_INT Latched interrupt. Read-only.

6 RESET_OVERLAY

Reset overlay section (set to 1 at reset).

5:4 PAL_INDEX

Upper 2 bits of palette address when in 2-bit/pixel mode.

3 INTEN Interrupt enable.

2 LDMD Enable palette load.

1:0 MODE 0 0 = Bypass (initializes to 00 at reset).0 1 = 2 bit/pixel.1 0 = 4 bit/pixel.1 1 = 8 bit/pixel.

Y V U BLND_ON/OFF BLND

15:12 11:8 7:4 3 2:0


15:12 Y Upper 4 bits of luminance data (lower 4 bits are 0).

11:8 V Upper 4 bits of V chrominance data (lower 4 bits are 0).

7:4 U Upper 4 bits of U chrominance data (lower 4 bits are 0).

3 BLND_ON/OFF

Blending/Transparency Enable.1 = Blending off; transparency on.0 = Blending on; transparency off.

2:0 BLND Blending value:

value blend value blend

000001010011

1/82/83/84/8

100101110111

5/86/87/88/8

finalpixel = blnd x palette value + (1 - blnd) x original pixel.

— DVE_EN

7:1 0



ES6425 DATA SHEET

REGISTERS

PRELIMINARY

NDA R

EQ

UIR

ED

Bit Definitions:

DVECTL1 (0x20001304h, R/W)

The DVECTL1 register controls the NTSC/PAL videomode select function, the square/nonsquare pixel selectfunction, and the horizontal and vertical sync clockfunction. After reset, this register returns a default value of0x0000h.

Bit Definitions:

DVECTL2 (0x20001308h, R/W)

The DVECTL2 register is primarily used for testing anddiagnostic purposes for the video DACs. A test pattern canalso be generated in this register to check the blanking,burst and chroma signal outputs of the video encoder.After reset, this register returns a default value of 0x0000h.

DVECTL3 (0x2000130Ch, R/W)

The DVECTL3 register controls the power down featuresof the digital video encoder and its DACs. Video DACdithering can be disabled for diagnostic purposes, whilenoninterlaced NTSC and PAL scan modes can also beenabled in this register. After reset, this register returns adefault value of 0x0000h.


7:1 — Reserved.

0 DVE_EN Digital Video Encoder Enable.1 = Encoder enabled.0 = Disabled.

PORCH SQPIX_SEL

DVE_SETUP

SYN-CLK FIRE FMODE VMODE —

7 6 5 4 3 2 1 0


7 PORCH Standard Front/Back Porch.1 = Pixels follow CCIR-624.0 = Pixels follow nonsquare mode.

6 SQPIX_SEL

Square Pixels Select.1 = Square pixels.0 = Nonsquare pixels (27 MHz CLK2X for

both PAL and NTSC).

5 DVE_SETUP

IRE Setup.1 = 0.0 IRE in NTSC mode.0 = 7.5 IRE in NTSC mode.

4 SYNCLK Sync Slave Mode Enable.1 = External horizontal/vertical sync.0 = Internal horizontal/vertical sync.

3 FIRE Fixed IRE Enable.1 = Use as much of the DAC dynamic range

as possible.0 = All outputs are set to the same number of

codes IRE.

2 FMODE Filter Mode Select.1 = Enhanced BW filters.0 = Normal range for the filters.

1 VMODE Video Mode Select.1 = NTSC interlace.0 = PAL interlace.

0 — Reserved

TPGEN INVERTDAC — COLOR

KILL TRANSI IBLANK DACTEST BYPASS

7 6 5 4 3 2 1 0


7 TPGEN Test Pattern Enable.1 = Test pattern generated.

6 INVERTDAC

Invert DACs. 1 = Data inverted before being applied to

DACs.

5 — Reserved.

4 COLORKILL

Color Kill.1 = Burst and chroma signals are blanked

out at the DACs.

3 TRANSI Transparency Input Control.

2 IBLANK Input Blank Select/1 = Data on DVE_PD is ignored; screen is

blanked.0 = Normal blanking operation.

1 DACTEST DAC Test Mode Select.1 = Test mode.0 = Normal operation.

0 BYPASS Pipeline Bypass Enable. When this bit is set, input data is passed directly to the output scaling stage before being sent to the video DACs.1 = DVE disabled.

— DAC_DITH DTME PWDNV PWDNC PWDNY PWDNALL

7:6 5 4 3 2 1 0


7:6 — Reserved.

5 DAC_DITH DAC Dither Disable.1 = Outputs to the DACs are dithered for

use with 10-bit DAC.0 = Outputs to the DACs are dithered for

use with 9-bit DAC.

4 DTME Noninterlace Mode Select. When this bit is set, this bit produces non-interlace output when in sync-lock to an interlace source.1 = Noninterlace mode continues to

generate 525 lines for NTSC and 625 lines for PAL for two fields, rather than 525 and 626 lines respectively.


ES6425 DATA SHEET

REGISTERS

PRELIMINARY

NDA R

EQ

UIR

ED

DVECTL4 (0x20001310h, R/W)

The DVERCTL4 register controls horizontal and verticalsync for the digital video decoder, RGB output select andYUV input select. The DVECTL4 register also controlsRGB dithering, YUV bit swapping and RGB-to-YUV matrixconversion operation. After reset, this register returns adefault value of 0x0000h.

Bit Definitions:

DVECC1 (0x20001324h, R/W)

The DVECC1 register controls the closed captioningfeatures of the digital video encoder. The default value is00h.

Bit Definitions:

VFD Interface RegistersThis section deals with the VFD interface registers of theES6425.

AUX_MODE (0x20001340h, R/W)

The Aux Pins Mode register contains the control logic forthe Aux2 port and the VFD interface. This registerinitializes to 0x00h after reset.

Bit Definitions:

3 PWDNV V Component Video DAC Power Down.1 = Normal operation.0 = V component video DACs powered

down.

2 PWDNC C Component Video DAC Power Down.1 = Normal operation.0 = C component video DACs. powered

down.

1 PWDNY Y Component Video DAC Power Down.1 = Normal operation.0 = Y component video DACs powered

down.

0 PWDNALL Master Video DAC Power Down.1 = Normal operation.0 = All video DACs powered down.

— NOVERRIDE VSYNC HSYNC MAT

BYPASSRGB_

DITHERPHASE

_SHCB

SWAP

7 6 5 4 3 2 1 0


7 — Reserved.

6 NOVERRIDE

No Override Enable.1 = No Override enabled.

5 VSYNC Vertical Sync Output Enable.1 = Vertical Sync output enabled.0 = Cleared on reset.

4 HSYNC Horizontal Sync Output Enable.1 = Horizontal Sync output enabled.0 = Cleared on reset.

3 MATBYPASS

Matrix Bypass Disable. 1 = Matrix bypass disabled.0 = Bypass cleared on reset.

2 RGB_DITHER

RGB Dither Enable.1 = RGB dithering enabled.0 = Cleared on reset.

1 PHASE_SH YUV Phase Input Sync Clock Shift.1 = Shift sync timing by two 2x clock for

non-square formats (odd pixels start at 123).

0 CBSWAP YUV-YCrCb Input Data Swap.1 = YUV-YCrCb data not swapped.0 = Data swapped.


— CCE_GATE CCE_FLD2 CCE_FLD1

7:3 2 1 0


7:3 — Reserved.

2 CCE_GATE

Closed Caption Gate Enable.1 = Enabled.

1 CCE_FLD2 Closed Caption Field 2 Enable.1 = Field 2 enabled.

0 CCE_FLD1 Closed Caption Field 1 Enable.1 = Field 1 enabled.

— AUX2[7:4]_SEL VFDDATA_OUT

VFDCLK_OUT — IRQ_

OUT

7:5 4 3 2 1 0


7:5 — Reserved.

4 AUX2[7:4]_SEL

Aux2[7:4] Select.1 = Select AUX[7:4].0 = Select AUX2[7:4] (default).

3 VFDDATA_OUT

VFD Data Output Select.1 = VFD data output selected.0 = AUX1[6] selected.

2 VFDCLK_OUT

VFD Clock Output Select.1 = VFD Clock output selected.0 = AUX2[0] selected.

1 — Reserved.

0 IRQ_OUT Interrupt Output Select.1 = Interrupt Output selected.0 = AUX2[3] selected.


ES6425 DATA SHEET

REGISTERS

PRELIMINARY

NDA R

EQ

UIR

ED

CCHIP_CTL (0x20001344h, R/W)

The Companion Chip Control register contains the controllogic for the interrupt counter and the watchdog timer. Thisregister initializes to 0x20h after reset.

Bit Definitions:

VFD_CTL (0x200013CCh, R/W)

The VFD Control register contains the control logic for theVFD interface. This register initializes to 0x00h after reset.

Bit Definitions:

IRQ_CTL (0x200013D4h, R/W)

The System Interrupt Control register contains the controllogic for the ES6425. This register initializes to 0x00h afterreset.

Bit Definitions:

Host Interface RISC Side Registers

This section describes the host interface RISC sideregisters.

R_HOSTDMAPORT (0x20003000h, R/W)

The RISC Side DMA Port register contains datatransferred to and from the host via the DMA port. Afterreset, this register initializes to 0x0000.

R_HOSTVCXPORT (0x20003004h, R/W)

The RISC Side Command Port register contains datatransferred to and from the host via the command port.After reset, this register initializes to 0x00.

R_HOSTDBGPORT (0x20003008h, R/W)

The RISC Side Debug Port register contains datatransferred to and from the host via the debug port. Afterreset, this register initializes to 0x00.

R_HOSTCTL (0x2000300Ch, R/W)

The RISC Side Host Control Port register contains datatransferred to and from the host via the control port. Afterreset, this register initializes to 0x10.

LOAD_WATCH IR_EN —

7 6 5:0


7 LOAD_WATCH

Load Watchdog Timer 1 = Timer loaded.

6 IR_EN Interrupt Counter Enable.1 = Counter enabled.

5:0 — Reserved.

— VFDCLK_FSEL VFD_MODE VFDK_SEL VFD_EN

7:4 3 2 1 0


7:4 — Reserved.

3 VFDCLK_FSEL

VFD Clock Frequency Select.1 = 844 kHz clock selected.0 = 422 kHz clock selected.

2 VFD_MODE

VFD Mode Select.1 = Write.0 = Read.

1 VFDK_ESEL

VFD Sampling Clock Edge Select.1 = Falling edge selected.0 = Rising edge selected.

0 VFD_EN VFD Interface Enable.1 = Enabled.0 = Disabled.

— SPORT_DET — IR_

DET — SPORT_MKS — IR_MSK

7 6 5 4 3 2 1 0


7 — Reserved.

6 SPORT_DET

Interrupt edge detect for Serial Port.1 = Falling edge.0 = Rising edge.

5 — Reserved.

4 IR_DET Interrupt edge detect for IR1 = Falling edge.0 = Rising edge.

3 — Reserved.

2 SPORT_MSK

Interrupt mask for Serial Port.1 = SPORT IRQ for UART masked.

1 — Reserved.

0 IR_MSK Interrupt mask for IR.1 = IR IRQ masked.

HOST INTERFACE RISC SIDE DMA PORT

15:0

HOST INTERFACE RISC SIDE COMMAND PORT

7:0

HOST INTERFACE RISC SIDE DEBUG PORT

7:0

— GW2HST

HST2XPT

R2HIRQ

CLRHIRQ

31:4 3 2 1 0



ES6425 DATA SHEET

REGISTERS

PRELIMINARY

NDA R

EQ

UIR

ED

Bit Definitions:

R_HOSTMASK (0x20003010h, R/W)

The RISC Side Host Mask register contains the maskingbits for interrupts from the host to the RISC. After reset,this register initializes to 0x0.

Bit Definitions:

R_HOSTIRQSTAT (0x20003014h, R)

The RISC Side Host Interrupt Status register reads thestatus of interrupts being sent from the host to the RISC (1= IRQ present, 0 = no IRQ present).

Bit Definitions:

R_IDEDAT (0x20003018h, R/W)

The RISC Side Data register contains IDE bus data beingsent and received to and from an ATAPI slave when theES6425 is operating in master mode. After reset, thisregister initializes to 0x0000h.

R_IDEADDR (0x2000301Ch, R/W)

The RISC Side IDE Address register contains the IDE busaddress value sent to an ATAPI slave when the ES6425 isin master mode. This register initializes to 0x0 after reset.

Bit Definitions:

R_IDECTL (0x20003020h, R/W)

The RISC Side IDE Control register contains the controllogic for interfacing with ATAPI-based loaders and otherperipherals This register initializes to 0x0000h after reset.

Bit Definitions:


31:4 — Reserved.

3 GW2HST

Gateway To Host Select.1 = Allows data transfer from gateway to host. 0 = Allows data transfer from RISC to host.

2 HST2XPT

Host To Transport Parser Select.1 = Allows data transfer to transport parser.0 = Allows data transfer to ESS RISC

1 R2HIRQ

Set RISC to Host IRQ. Writing a 1 to this bit sets the ESS RISC to Host IRQ flag.

0 CLRHIRQ

Clear Host IRQ. Writing a 1 to this bit clears the host to RISC IRQ.

ENDN_SEL

DBG_DW

DBG_TRE

DMA_DW

DMA_TRE

VCX-IDW

VCXI-TRE

H2RIRQ

7 6 5 4 3 2 1 0


7 ENDN_SEL

Big/Little Endian Select1 = switch upper/lower bytes when writing to R_HOSTDMAPORT.

6:0 Mask bits for interrupts from the host to the RISC.

— R2HIRQ

DBGTRE

DBGDW

DMATRE

DMADW

VCXITRE

VCXIDW

H2RIRQ

15:8 7 6 5 4 3 2 1 0


15:8 — Reserved.

7 R2HIRQ Interrupt flag set by the RISC as a signal to the host.

6 DBGTRE

Debug transmit register empty (OK for RISC to send data to the host).

5 DBGDW Debug data waiting (RISC needs to read data from the host).

4 DMATRE

DMA transmit register empty (OK for RISC to send data to the host).

3 DMADW

DMA data waiting (RISC needs to read data from the host).

2 VCXITRE

VCXI transmit register empty (OK for RISC to send data to the host).

1 VCXIDW

VCXI data waiting (RISC needs to read data from the host).

0 H2RIRQ Interrupt flag set by the host as a signal to the RISC.

IDE_DATA

15:0

— IDE_ADDR

7:3 2:0


7:3 — Reserved.

2:0 IDE_ADDR

IDE Address.

— CLRIRQ

IDE2

XPT

IDEST

IDERST

IDEMSK

1

IDEMSK0

IDECS

HSTMODE

IDE_EN

IDE_RW

PIOMODE

15:13 12 11 10 9 8 7 6 5 4 3 2:0


15:13 — Reserved.

12 CLRIRQ Write 1 to clear sector-end interrupt from ATAPI slave.

11 IDE2XPT

In master mode, writing a 1 to this bit enables data transfer from the external ATAPI device to the transport stream parser. The data transfer continues until this bit is reset to 0.

10 IDEST Write 1 to signal the beginning of the sector. The sector start signal will be reset by the first data valid.



ES6425 DATA SHEET

REGISTERS

PRELIMINARY

NDA R

EQ

UIR

ED

R_IDESSTAT (0x20003024h, W)

The write-only RISC Side IDE Status register contains thestatus information for the IDE bus interface.

Bit Definitions:

R_IDECNT (0x20003028h, R/W)

The RISC Side IDE Bus Counter register contains thecounter mechanism for the IDE bus interface of theES6425 when configured to be in Master Mode. Thisregister initializes to 0x07FFh after reset.

Bit Definitions:

Host Interface RISC-SRAM Interface Registers

This section describes the RISC-SRAM interface registersassociated with the host interface of the ES6425.

RIFACE_WIDTH (0x20004000h, R/W)

The RISC-SRAM Interface Width register contains thelogic for establishing the width of the bus to externalmemory, and controls the internal cache.

The value of the TDMDX pin is sampled at the rising edgeof RESET# and the RIFACE_WIDTH register isprogrammed according to the bit settings listed in Table 9.

Bit Definitions:

9 IDERST Write 1 to reset the ATAPI slave, then write 0 to unreset. The ATAPI slave will also be reset at the same time with the ES6425.

8 IDEMSK1

Mask sector-end interrupt from ATAPI to RISC.

7 IDEMSK0

Mask interrupt from ATAPI to RISC.

6 IDECS IDE Chip Select1 = Assert CS3FX#.0 = Assert CS1FX#.

5 HSTMODE

1 = Master mode. Host will send read/write commands (comply to ATAPI).

0 = Slave mode. Host will receive commands or data from DMP-DSP.

4 IDE_EN

Enable the host to write/read to/from the ATAPI slave.

3 IDE_RW

1 = Read from ATAPI slave.0 = Write to ATAPI slave.

2:0 PIOMODE

Programmable IO Mode Select.

— IDEIRQ IDE16 IDEVAL

7:3 2 1 0


7:3 — Reserved.

2 IDEIRQ 1 = Sector-end interrupt from ATAPI slave to RISC.

1 IDE16 Read only bit1 = 16-bit transfer.If reading from ATAPI slave, all 16-bit data of R_IDEDAT are valid.If writing to ATAPI slave, all 16-bit data of R_IDEDAT are received at the ATAPI slave.0 = 8-bit transfer.If reading from ATAPI slave, only the last 8 bits of R_IDEDAT are valid.If writing to ATAPI slave, only the last 8 bits of R_IDEDAT are received at the ATAPI slave.


BIT 2 BIT 1 BIT 0Maximum Transfer

Rate

0 0 0 3.33 MB/0

0 0 1 5.22 MB/0

0 1 0 11.11 MB/0

0 IDEVAL 1 = PIO cycle is completed. In read mode, read from R_IDEDAT to retrieve the data from the ATAPI slave; write 1 to clear this bit.

— IDE_CNT

15:12 11:0


15:12 — Reserved.

11:0 IDE_CNT

Reading from this register returns the IDE bus interface count down value.

— DBG-MODE

CACHE-FLS

CACHEDIS-

ABLEDIV B3W B2W B1W B0W

15:11 10 9 8 7:5 4 3 2 1:0

Table 9 External Memory Width Selection Options

TDMDX/RSEL Selection

0 16-bit ROM.

1 8-bit ROM.


15:11 — Reserved.

10 DBGMODE Debug mode:0 = Save power from outside pins

toggling.1 = riscaddr and riscbus are seen from

the SRAM address/data.Default is a 1 after reset.



ES6425 DATA SHEET

REGISTERS

PRELIMINARY

NDA R

EQ

UIR

ED

RIFACE_WAIT_STATE (0x20004004h, R/W)

The RISC-SRAM Interface Wait State register contains thelogic for the total number of possible external wait statesthat can be inserted per access for SRAM banks 3:0. Upto 32 wait states can be inserted if desired.

Table 10 gives the hexadecimal value for each number ofpossible wait states:

RIFACE_AUX1 (0x2000402Ch, R/W)

This register is a general I/O port for interfacing withexternal devices.

Bit Definitions:

When this register is read, the values read are the valuesat the pin. The two open collector pins allow I2C buscommunication and require an external pull-up resistor.The default value is for P3:P2 to be tri-state, and P1:P0 tobe disabled (i.e., P1, P0 = high (logic 1), and T3, T2 = low(logic 0)).

RIFACE_AUX2 (0x20004030h, R/W)

This register is a second general-purpose I/O port withfour tri-state channels.

Bit Definitions:

When this register is read, the values read are the valuesat the pin. Default values for tri-state controls are 0(tri-state) at reset.

Bus Controller Registers

This section deals with the bus controller register sectionsof the ES6425. The bus controller includes

Bus Controller (SIMD DSP) RegistersThis section describes the SIMD DSP registers of the buscontroller in detail.

9 CACHEFLS Cache Flush. When set to 1, the memory cache is flushed. Default is a 1 after reset.1 = Flush cache.0 = Normal operation.

8 CACHEDISABLE

Cache Disable.0 = Cache enabled.1 = Cache bypassed. Default is a 1 after reset.

7:5 DIV Clock Divisor.

4 B3W Bank 3 Width1 = 16 bits wide.0 = 8 bits wide (default).



1:0 B0W Bank 0 Width [1:0]00 = 8-bit wide (default).01 = 16-bit wide.10 = Map Bank 0 to DRAM.11 = Undefined.

— BANK3 BANK2 BANK1 BANK0

31:20 19:15 14:10 9:5 4:0

Table 10 Hex Values for Wait States

HexValue

Wait State

HexValue

Wait State

HexValue

Wait State

HexValue

WaitState

1F 1 17 9 0F 17 07 25

1E 2 16 10 0E 18 06 26

1D 3 15 11 0D 19 05 27

1C 4 14 12 0C 20 04 28

1B 5 13 13 0B 21 03 29

1A 6 12 14 0A 22 02 30

19 7 11 15 09 23 01 31

18 8 10 16 08 24 00 32 (default)


— 0 T3 T2 P3 P2 P1 P0

15:10 9:6 5 4 3 2 1 0


15:10 — Reserved.

9:6 — Reserved. Always 0.

5:4 T3,T2 Tri-state controls.1 = I/O state selected.0 = Tri-state selected.

3:2 P3, P2 Tri-stateable pins.

1:0 P1, P0 Open collector pins.

— T P

15:8 7:4 3:0


15:8 — Reserved.

7:4 T Tri-stateable controls.

3:0 P Tri-stateable pads.


ES6425 DATA SHEET

REGISTERS

PRELIMINARY

NDA R

EQ

UIR

ED

BUSCON_VP_CONTROL (0x20008000h, R/W)

The Bus Controller Video Processor Control registercontains the control logic for the video processor core.

Bit Definitions:

BUSCON_VP_STATUS (0x20008004h, R)

The read-only Bus Controller Video Processor Statusregister provides status information on the corecomponents of the video processor, including the I/O statemachine, the sequencer, and the command queue.

Bit Definitions:

Bus Controller (Memory Controller) RegistersThis section describes the Memory Controller registers ofthe bus controller in detail.

BUSCON_DRAM_CONTROL (0x20008100h, R/W)

The Bus Controller DRAM Control register contains thecontrol logic for the video memory interface. This registerinitializes to 0x0000 after reset.

Bit Definitions:— DVE_108 LOAD_VP VP_RST#

15:3 2 1 0


15:3 — Reserved.

2 DVE_108 Video PLL Frequency Select.1 = 108 MHz frequency selected.0 = 54 MHz frequency selected (default).

1 LOAD_VP Load video processor microcode.1 = Load microcode.0 = Don’t load.

0 VP_RST# Video Processor Reset.1 = Enabled.0 = Reset.

— SEQ TRD IOSM CMDQ_ST

15:5 4 3 2 1:0


15:5 — Reserved.

4 SEQ Sequencer Status.

3 TRD Transfer Ready Status.

2 IOSM I/O State Machine Status.

1:0 CMDQ_ST

Command Queue Status.

— SELSCLKEN

SD64M

SD8BIT

BIGEDO

SDCF

SREFEN

REFEN — RAS

PRERASDEL

SPDEDO

31:17 16 15 14 13 12:11 10 9 8:6 5:4 3:2 1:0


31:17 — Reserved.

16 SELSCLKEN

SDRAM Clock Enable.1 = Pin 70 is SDSCLKEN0 = Pin 70 is DOE#

15 SD64M SDRAM Type Select.1 = Use 64 Mb SDRAM0 = Use 16 Mb SDRAM

14 SD8BIT

SDRAM 8-Bit Select.1 = SDRAM type is x8.0 = SDRAM type is x16.Note: If the memory used is of 128 Mb type(16 MB total memory), set SD8BIT to 1.

13 BIGEDO

EDO DRAM Select.1 = EDO is 1M x 160 = EDO is 256K x 16

12:11 SDCF SDRAM/EDO Memory Configuration.

10 SREFEN

SDRAM Refresh Enable.1 = Refresh logic for SDRAM enabled.

9 REFEN

EDO Refresh Enable.1 = Refresh logic for EDO DRAM enabled.

8:6 — Reserved.

5:4 RASPRE

RAS Precharge Time Control for EDO.

3:2 RASDEL

RAS to CAS Delay Time.

1:0 SPDEDO

EDO DRAM Speed Select.

MemSize(MB)

SD64M

SD8BIT

SDCFG

1

SDCFG

0

Memory Configuration

(Mb per pc)

2 0 0 0 11 pc 512kx16x2(16 Mb)

4 0 0 0 02 pc 512kx16x2(16 Mb)

4 0 1 0 12 pc: 1Mx8x2(16 Mb)

8 0 1 0 04 pc 1Mx8x2(16 Mb)

8 1 0 — —1 pc: 1Mx16x4(64 Mb)

16 1 0 — —2 pc 1Mx16x4(64 Mb)

16 1 1 — —2 pc 2Mx8x4(64 Mb)

16 1 1 — —1 pc 2Mx16x4(128 Mb)


ES6425 DATA SHEET

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BUSCON_DRAM_SREFTIME (0x20008114h, R/W)

The Bus Controller DRAM Refresh Time register controlsthe SDRAM refresh period for the system, and containsthe refresh interval value. After reset, it is not initialized.

Bit Definitions:

Bus Controller (Command Queue) RegistersThis section describes the Command Queue registers ofthe bus controller in detail.

BUSCON_CMDQUE_VPDMASETUP (0x20008200h, W)

The BUSCON_CMDQUE_VPDMASETUP register takesthe video processor DMA access requests directed to thecommand queue and prioritizes the DMA requests.

Bit Definitions:

Audio Interface Registers

This section describes all the registers controlling theaudio section, and serves as a reference for bothhardware and f i rmware engineers who need tounderstand the internal workings of the ES6425.

AUDIOCTL (0x2000D008h, R/W)

This Audio Control register enables the correspondingfunctions and clocks. After reset, it is initialized to 0x00.

Bit Definitions:

INTVAL

7:0


7:0 INTVAL SDRAM refresh interval value.

— BK DIR HINT — DW2 DB WX DW10 DELY DELX

31:25 24 23 22 21 20 19 18 17:16 15:9 8:0


31:25 — Reserved.

24 BK Break. When set, this bit sends the BREAK# signal to the video processor at the end of a line.

23 DIR Data Transfer Direction.1 = Memory to video processor.0 = Video processor to memory.

22 HINT Video Processor Hint Block. When set, this bit blocks the DMA arbitration to the extent that the next video processor DMA request will be granted over requests at the same level or below the current request level for a back-to-back video processor DMA transaction.

21 — Reserved.

20 DW2 DMA Width Register Select. Used in conjunction with bits 17 and 16.

19 DB Double DMA Width Select.1 = Double DMA width selected.0 = Single DMA width selected.

18 WX Select Delta X as DMA Width Register.1 = Use DMA Width register.0 = Use DELX as DMA Width register.

17:16 DW10 DMA Width Register Select. Use with DW2 bit 20. This 3-bit field permits the selection of one of eight possible DMA width registers, depending on the DMA width selected by DB bit (bit 19) of this register. Four single DMA width registers and four double DMA width registers are available to support the desired DMAs for the memory configuration implemented in the design.

15:9 DELY Transfer Y Longwords

8:0 DELX Transfer X Scan Lines.

AIEN AMS AREN AXEN ABEN DM SRST —

7 6 5 4 3 2 1 0


7 AIEN Audio interrupt enable.The corresponding port must be enabled for proper interrupt status.0 = disabled.1 = enabled.

6 AMS Audio master clock selection:0 = external MCLK.1 = internal MCLK.

5 AREN Audio receive enable.0 = disabled.1 = enabled.

4 AXEN Audio transmit enable. The DMA must be started before enabling the transmit port.1 = Audio transmit enabled.0 = Audio transmit disabled.

3 ABEN Audio bit clock generator enable (used only when internal MCLK is selected).

2 DM Data input (either from pri_bus or risc) debug mode:0 = data from pri_bus.1 = data from risc_bus.

1 SRST Soft reset, this bit will self-reset when a 1 is written.

0 — Reserved.


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AUDIOXMT (0x2000D00Ch, R/W)

This Audio Transmit Format register is used for setting upthe format for the transmit port. After reset, the register isinitialized to 0x0000.

Bit Definitions:

AUDIORCV (0x2000D010h, R/W)

This is the audio receive format register. After reset, it isinitialized to 0x0000.

Bit Definitions:

AUDIOAPLLM (0x2000D014h, R/W)

This register is the Analog PLL Frequency Divider register.After reset, it is initialized to 0x4Ah.

Bit Definitions:

TLSB TDGE TDFS TDM TCF TFM ITFS TBCS AM TBCF

15 14 13 12:10 9:8 7:6 5 4 3:2 1:0


15 TLSB Transmit LSB Select.1 = LSB first.0 = MSB first.

14 TDGE Transmit Bit Clock Edge Select.1 = Output data on falling edge of clock.0 = Output data on rising edge of clock.

13 TDFS Transmit Data Frame Sequence Select.1 = Last bit sent on last cycle.0 = First bit sent on first cycle.

12:10 TDM Transmit Data Frame Mode Select.000 = 16-bit data frame.001 = 18-bit data frame.010 = 20-bit data frame.011 = 24-bit data frame.100 = 32-bit data frame.101 = Reserved.11x = Reserved.

9:8 TCF Transmit Cycle Frame.00 = 16-bit cycle frame.01 = 24-bit cycle frame.10 = 32-bit cycle frame.11 = Reserved.

7:6 TFM Transmit Frame Mode00 = Reserved.01 = Philips I2S format.10 = Normal frame mode.11 = Reserved.

5 ITFS Inverse audio transmit frame sync.1 = Enabled.0 = Disabled.

4 TBCS Audio Bit Clock Select 1 = Use internal bit clock and output bit clock.0 = Use external bit clock.

3:2 AM Audio Mode Select00 = Stereo L-R channel.01 = 5.1 channel.10 = Reserved.11 = Reserved.

1:0 TBCF Audio Transmit Bit Clock Frequency Select00 = MCLK/8.01 = MCLK/2.10 = MCLK/4.11 = MCLK/1.

RLSB RDGE RDFS — RDM RCF RFM IRFS RBCS — RBCF

15 14 13 12 11:10 9:8 7:6 5 4 3:2 1:0


15 RLSB Receive LSB Select.1 = LSB first.0 = MSB first.

14 RDGE Receive Data Bit Clock Edge Select.1 = Input data sampled on falling edge0 = Input data sampled on rising edge.

13 RDFS Receive Data Frame Sequence.1 = Last bit sent on last cycle0 = First bit sent on first cycle.

12 — Reserved.

11:10 RDM Receive Data Frame Select 00 = 16-bit data frame.01 = Reserved.10 = Reserved.11 = Reserved.

9:8 RCF Receive Cycle Frame Select 00 = 16-bit cycle frame.01 = 24-bit cycle frame.10 = Reserved.11 = Reserved.

7:6 RFM Receive Frame Mode Select.00 = Reserved.01 = Philips I2S format.10 = Normal frame mode.11 = Reserved.

5 IRFS Inverse Receive Frame Sync Select.1 = Enabled.0 = Disabled.

4 RBCS Receive Bit Clock Select.1 = Reserved. Driven by external ADC.0 = Use external bit clock.

3:2 — Reserved.

1:0 RBCF Receive Bit Clock Frequency. Reserved. Driven by external ADC.

M

7:0


7:0 M Audio frequency divider M.


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AUDIOAPLLN (0x2000D018h, R/W)

This register is the Analog PLL Frequency Multiplierregister. After reset, it is initialized to 0x1Fh.

Bit Definitions:

S/PDIF Interface RegistersThis section describes the S/PDIF audio interfaceregisters.

SPDIF_CTL (0x2000D01Ch, R/W)

The S/PDIF Control register contains the control logic forthe S/PDIF output function of the ES6425. This registerinitializes to 0x00 after reset.

Bit Definitions:

SPDIF_CSD1:6 (0x2000D020h:0x2000D034h, R/W)

The SPDIF Channel Status Data registers contain the datafor the subframes present in the S/PDIF channel statusblock. After reset, it is initialized to 0x0000 0000h.

Bit Definitions:

AUDIOIMASK (0x2000D038h, R/W)

This register is the Audio Interrupt Mask register. Afterreset, i t is ini t ial ized to 0x00. Write a “1” to thecorresponding bit to mask the interrupt.

Bit Definitions:

FS OD M8 N

7 6 5 4:0


7 FS Sampling Frequency Select.1 = 384 sample frequency selected.0 = 256 sample frequency selected.

6 OD Output Divider.

5 M8 Bit 8 of M Divider Value.

4:0 N Audio frequency multiplier N.

— SPDIF_RST SPDIF_CLK SPDIF_SFRMV SFRMDB — SOE

7 6 5:4 3 2 1 0


7 — Reserved.

6 SPDIFRST

S/PDIF Soft reset.

5:4 SPDIF_CLK

S/PDIF Bit Clock Frequency Select.00 = SPMCLK/8 (n=8)01 = SPMCLK/4 (n=2)10 = SPMCLK/2 (n=4)11 = SPMCLK/16 (n=16)

3 SPDIF_SFRMV

S/PDIF Subframe Validity Select.

2 SFRMDB

User data bit for subframe.

1 — Reserved. Always 0.

0 SOE SPDIF output enable:1 = Enabled.0 = Disabled.

CDS1:6

31:0


31:0 CDS1:6 SPDIF channel status data.

MSSE MSCSE MSTRE MSUE MACS MAUE MATRE MADW

7 6 5 4 3 2 1 0


7 MSSE Mask for SPDIF channel swap error.

6 MSCSE Mask for SPDIF channel status empty.

5 MSTRE Mask for SPDIF transmit register empty.

4 MSUE Mask for SPDIF underflow error.

3 MACS Mask for audio channel swap error.

2 MAUE Mask for audio underflow error.

1 MATRE Mask for audio transmit register empty.

0 MADW Mask for audio data waiting interrupt.



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ES6425 TIMING DIAGRAMS

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Audio Interface Timing

The audio interface timing diagrams for the ES6425 areshown in Figure 10 through Figure 14.

Figure 10 Right Justified Mode / 16-Bit Cycle Frame / 16-Bit Data Frame / MSB First

Figure 11 Right Justified Mode / 24-Bit Cycle Frame / 16-Bit Data Frame / MSB First

Figure 12 Right Justified Mode / 32-Bit Cycle Frame / 24-Bit Data Frame / LSB First

TBCK/RBCK

TWS

TSD[2:0]/RSD

TBCK/RBCK

TWS

TSD[2:0]/RSD

TBCK/RBCK

TWS

TSD[2:0]/RSD


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Figure 13 Left Justified Mode / 32-Bit Cycle Frame / 24-Bit Data Frame / MSB First

Figure 14 I2S Mode

TBCK/RBCK

TWS

TSD[2:0]/RSD

TBCK/RBCK

TWS

TSD[2:0]/RSD


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Clock Interface Timing

The ES6425 clock interface t iming diagram andcharacteristics are shown in Figure 15.

Figure 15 Audio Master, Pixel, Doubled Pixel, and TDM Clock Timing

t1, t6, t11, t16

t2, t7, t12, t17

t3, t8, t13, t18t4, t9, t14, t19 t5, t10, t15, t20

Clock

Symbol Parameter Minimum Typical Maximum Unit Comments

Pixel Clock Timing

t1 tCLK_P Clock period 30 — 100

ns

t2 tCLK_LT Clock low time 15 — —

t3 tCLK_HT Clock high time 15 — —

t4 tCLK_RT Clock rise time — — 6

t5 tCLK_FT Clock fall time — — 6

Doubled Pixel Clock Timing

t6 tPCLK_P Pixel clock period 33 — —

ns

t7 tPCLK_LT Pixel clock low time 15 — —

t8 tPCLK_HT Pixel clock high time 15 — —

t9 tPCLK_RT Pixel clock rise time — — 4

t10 tPCLK_FT Pixel clock fall time — — 4

Audio Master Clock Timing

t11 tACLK_P Audio clock period 40 — —

ns T = 1/192 kHz X 128

t12 tACLK_LT Audio clock low time 9 — —

t13 tACLK_HT Audio clock high time 9 — —

t14 tACLK_RT Audio clock rise time — — 6

t15 tACLK_FT Audio clock fall time — — 6

TDM Clock Timing

t16 tTDMCLK_P TDM clock period 40 — —

ns T = 1/96 kHz X 256

t17 tTDMCLK_LT TDM clock low time 14 — —

t18 tTDMCLK_HT TDM clock high time 14 — —

t19 tTDMCLK_RT TDM clock rise time — — 6

t20 tTDMCLK_FT TDM clock fall time — — 6


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Compact Flash Interface Timing

The Compact Flash interface timing diagrams for theES6425 appear from Figure 16 to Figure 17.

Figure 16 Compact Flash True IDE Mode I/O Read Timing

HA[2:0]

HCS1FX#

HRD#

HIOCS16#

HD[15:0] HDOUT VALID

tH_HRD

tDR_HIOCS16ADR

tD_HRD

tW_HRD

tDF_HIOCS16ADR

tSUCE_HRD

tSUA_HRD tHA_HRD

tHCE_HRD

Symbol Parameter Minimum Typical Maximum Unit

tD_HRD Data delay after HRD#. — — 100

ns

tH_HRD Data hold following HRD#. 0 — —

tW_HRD HRD# width time. 165 — —

tSUA_HRD Address setup before HRD#. 70 — —

tHA_HRD Address hold following HRD#. 20 — —

tSUCE_HRD CE# setup before HRD#. 5 — —

tHCE_HRD CE# hold following HRD#. 20 — —

tDF_HIOCS16ADR HIOCS16# delay falling from address. — — 35

tDR_HIOCS16ADR HIOCS16# delay rising from address. — — 35

NOTE: The maximum load on HIOCS16# is 1 LSTTL with 50pF total load. HDOUT signifies data provided by the Compact Flash storage card or CF+ storage card to the system.


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Figure 17 Compact Flash True IDE Mode I/O Write Timing

HA[2:0]

HCS1FX#

HWR#

HIOCS16#

HD[15:0] HDIN VALID

tH_HWR

tDR_HIOCS16ADR

tW_HWR

tDF_HIOCS16ADR

tSUCE_HWR

tSUA_HWR tHA_HWR

tHCE_HWR

tSU_HWR


tSU_HWR Data setup before HWR#. 60 — —

ns

tH_HWR Data hold following HWR#. 30 — —

tW_HWR HWR# width time. 165 — —

tSUA_HWR Address setup before HWR#. 70 — —

tHA_HWR Address hold following HWR#. 20 — —

tSUCE_HWR CE# setup before HWR#. 5 — —

tHCE_HWR CE# hold following HWR#. 20 — —

tDF_HIOCS16ADR HIOCS16# delay falling from address. — — 35

tDR_HIOCS16ADR HIOCS16# delay rising from address. — — 35

NOTE: The maximum load on HIOCS16# is 1 LSTTL with 50pF total load. HDIN signifies data provided by the system to the Compact Flash storage card or CF+ storage card.


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Host Interface Timing

The host interface timing diagrams for the ES6425 areshown in Figure 18 and Figure 19

.

Figure 18 Host Bus Read Timing

HA[2:0]

HD[15:0]

HWR#

HRD#

HWRQ#

HRRQ#

HIRQ

tHIHR#_OD

tHRDHR#_OD

tHR#_PWL

tHR#_PWH

tHDHR#_ST tHDHR#_HT

tHAHR#_HTtHAHR#_ST

tHRRQ_PH


tHAHR#_ST HA to HRD# setup time 4 — —

ns

tHAHR#_HT HA to HRD# hold time 2 — —

tHDHR#_ST HD to HRD# setup time 0 — 4

tHDHR#_HT HD to HRD# hold time 2 — —

tHR#_PWH HRD# pulse width high 30 — —

tHR#_PWL HRD# pulse width low 30 — —

tHRDHR#_OD HRRQ# to HRD# output delay 0 — 8

tHIHR#_OD HIRQ to HRD# output delay 0 — 8

tHRRQ_PH HRRQ# pulse width high (See note) 75 — —

NOTE: HRRQ# is defined as a minimum value.


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Figure 19 Host Bus Write Timing

tHAHW#_HT

tHDHW#_HTtHDHW#_ST

tHW#_PWL

tHW#_PWH

HA[2:0]

HD[15:0]

HWR#

HRD#

HWRQ#

HRRQ#

HIRQ

tHIHW#_OD

tHWR#_OD

tHAHW#_ST

tHWRQ_PH


tHAHW#_ST HA to HWR# setup time 4 — —

ns

tHAHW#_HT HA to HWR# hold time 2 — —

tHDHW#_ST HD to HWR# setup time 4 — —

tHDHW#_HT HD to HWR# hold time 2 — —

tHW#_PWL HWR# pulse width low 30 — —

tHW#_PWH HWR# pulse width high 30 — —

tHWR#_OD HWRQ# to HWR# output delay 0 — 8

tHIHW#_OD HIRQ to HWR# output delay 0 — 8

tHWRQ_PH HWRQ# pulse width high (See note) 75 — —

NOTE: HWRQ# is defined as a minimum value.


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Memory Stick Interface Timing

The Memory Stick interface timing diagrams for theES6425 appear from Figure 20 to Figure 21.

Figure 20 Memory Stick Read Timing

Figure 21 Memory Stick Write Timing

AUX3[1](Bus State)

AUX3[2](Serial Clock)

AUX4[1](Serial Data I/O)

BS0 BS1 BS2 BS3 BS0

CRCDATABSY/RDYTPC

AUX3[1](Bus State)

AUX3[2](Serial Clock)

AUX4[1](Serial Data I/O)

BS0 BS1 BS2 BS3 BS0

CRCDATA BSY/RDYTPC


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SDRAM Interface Timing

The SDRAM interface timing diagrams for the ES6425 areshown in Figure 22 through Figure 26.

Figure 22 SDRAM Random Column Read Timing

NOTE: Refer to Table 11 for parameter values.

T0

DSCK

DSC[1:0]#

DRAS#

DCAS#

DWE#

DMA[11]

T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

RAw

RAw

RAz

CAw CAx RAy RAz CAz

Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3

Hi-Z

DMA[10]

DMA[9:0]

DQM

DB[15:0]

ActivateCommand

Bank A

ReadCommand

Bank A

ReadCommand

Bank A

ReadCommand

Bank A

ReadCommand

Bank A

ActivateCommand

Bank A

PrechargeCommand

Bank A

Burst Length = 4, DCAS# Latency = 3


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Figure 23 SDRAM Random Column Write Timing


T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22

RBw

RBw

RBz

CBw CBx RBy RBz CBz

DBx0 DBx1 DBy0 DBy1 DBy2 DBy3

Hi-Z

ActivateCommand

Bank B

ReadCommand

Bank B

ReadCommand

Bank B

ReadCommand

Bank B

ReadCommand

Bank B

ActivateCommand

Bank B

PrechargeCommand

Bank B


DBw0 DBw3DBw1 DBw2 DBz1DBz0

DSCK

DSC[1:0]#

DRAS#

DCAS#

DWE#

DMA[11]

DMA[10]

DMA[9:0]

DQM

DB[15:0]


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Figure 24 SDRAM Random Row Read Timing



RBx

RBx

RBy

CBx RAx CAx RBy CByz

Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2

Hi-Z

ActivateCommand

Bank B

ReadCommand

Bank B

ReadCommand

Bank A

PrechargeCommand

Bank A

ReadCommand

Bank B

ActivateCommand

Bank B


RAx

Bx0 Ax3 Ax4 Ax5 Ax6 Axy By0

PrechargeCommand

Bank B

ActivateCommand

Bank A

DSCK

DSC[1:0]#

DRAS#

DCAS#

DWE#

DMA[11]

DMA[10]

DMA[9:0]

DQM

DB[15:0]


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Figure 25 SDRAM Random Row Write Timing



RBx

RBx

RBy

CBx RAx CAx RBy CByz

DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5

Hi-Z

ActivateCommand

Bank A

WriteCommand

Bank A

WriteCommand

Bank B

PrechargeCommand

Bank B

WriteCommand

Bank A

ActivateCommand

Bank A


RAx

DAx3 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3

PrechargeCommand

Bank A

ActivateCommand

Bank B

DAx2DAx1DAx0

DSCK

DSC[1:0]#

DRAS#

DCAS#

DWE#

DMA[11]

DMA[10]

DMA[9:0]

DQM

DB[15:0]


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Figure 26 ES6425 SDRAM Read and Write

Table 11 SDRAM Interface Timing

Symbol Parameter (CAS Latency = 3) Minimum Maximum Units

tRRD Row active to Row Active Delay 2 —

CLK

tRCD DRAS# to DCAS# Delay 3 —

tRP Row precharge time 3 —

tRAS Row active time 6 200

tRC Row cycle time 10 —

tCDL Last data in to new column address delay 1 —

tRDL Last data in to row precharge 1 —

tBDL Last data in to burst stop 1 —

tCCD Column address to column address delay 1 —

tCC

tOD

tCH tCL

tSS tSH

tOH

DB[15:0] (read)

Commands andDMA[11:0], DB[15:0] (write)

DSCK

Table 12 SDRAM Read and Write Timing

Symbol Parameter (CAS Latency = 3) Minimum Maximum Units

tCC CLK cycle time 8 — ns

tOD CLK to valid output delay — 6 ns

tOH Output data hold time 2 — ns

tCH CLK high pulse width 3 — ns

tCL CLK low pulse width 3 — ns

tSS Input setup time 1.5 — ns

tSH Input hold time 0.5 — ns

tSLZ CLK to output in low-Z 1 — ns

tSHZ CLK to output in Hi-Z — 6 ns

NOTE: SDRAM read and write timing is for ES6425 running at 121 MHz.


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SRAM Interface Timing

The SRAM interface timing diagrams for the ES6425 areshown in Figure 27 and Figure 28.

Figure 27 SRAM Read Timing

LA[21:0]

LCS[3:0]#

LWRxx#

LOE#

LD[15:0]

Address Address Address

tSRAM_AT

rd0 rd1 rd0

tSRAM_ATtBS_DT

tRC_DSTDL tRC_DHTDLtRC_DSTDL tRC_DHTDL

n Waitstate Bank Select n Waitstate


tDRAM_IOSS DRAM interface output signal skew 0 — 3

nstRC_DSTDL Read cycle data setup time to data latch 6 — —

tRC_DHTDL Read cycle data hold time to data latch 2 — —

tSRAM_AT SRAM access time 2 — 33Internal CPU clock cycle

tBS_DT Bank Select delay time 0 — 3


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Figure 28 SRAM Write Timing

LA[21:0]

LCS[3:0]#

LWRxx#

LOE#

LD[15:0]

Address Address Address

tSRAM_AT tSRAM_ATtBS_DT

Data Data Data

tA_STWS

tW_STWL

tA_HTWStA_STWS tA_HTWS


tSRAM_IOSS SRAM interface output signal skew 0 — 3 ns

tSRAM_AT SRAM access time 2 — 33

Internal CPU clock cycle

tBS_DT Bank Select delay time 0 — 3

tA_STWS Address setup time to write strobe 0.5 — 0.5

tA_HTWS Address hold time to write strobe 0.5 — 0.5

tW_STWL Write strobe pulse width low 1 — 31.5


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TDM Interface Timing

The TDM interface timing diagram for the ES6425 isshown in Figure 29.

Figure 29 TDM Interface Timing

TDMCLK

TDMFS

TDMDR

TDMTSC#

TDMDX

10 2 3 4 5 6 7

10 2 3 4 5 6 7

Recv Channel 1Recv Channel 0tTDM_RD

tTDMCLK_P

Transmit Channel 0tTDM_TD

tTDM#_COD

tTDMFS_STtTDMFS_HT

tTDMDR_STtTDMDR_HT

tTDMDX_DOD

Symbols Parameters Minimum Typical Maximum Unit

tTDMCLK_P TDM clock period 62.5 — —

ns

tTDM#_COD TDMTSC# control output delay to TDMCLK 0 — 2

tTDMFS_ST TDMFS setup time to TDMCLK 4 — —

tTDMFS_HT TDMFS hold time to TDMCLK 2 — —

tTDMDR_ST TDMDR data setup time to TDMCLK 4 — —

tTDMDR_HT TDMDR data hold time to TDMCLK 2 — —

tTDMDX_DOD TDMDX data output delay to TDMCLK 0 — 2

tTDM_RD TDM receive delay to TDMFS 0 — 8Internal CPU clock cycle

tTDM_TD TDM transmit delay to TDMFS 0 — 8


ES6425 DATA SHEET


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Video Interface Timing

The video interface timing diagrams for the ES6425 areshown in Figure 30 through Figure 38.

Figure 30 NTSC Timing

Figure 31 PAL Timing

522 523 524 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22

DISPLAY DISPLAY VERTICAL BLANK

ODD FIELDEVEN FIELD

H

V

F

260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 283 284 285

ODD FIELD EVEN FIELD


H

V

F

622 623 624 625 1 2 3 4 5 6 7 21 22 23


H

V

F ODD FIELDEVEN FIELD

309 310 311 312 314 315 316 317 318 319 320 334 335 336


H

V

F ODD FIELD EVEN FIELD

313


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Figure 33 PAL Teletext / Vertical Blanking Interval Timing

12.91 s

START

PARITY

PARITY

D0–D6 D0–D6

10.003 s

33.764 s

50 IRE

40 IRE

FREQUENCY = FSC = 3.579545MHzAMPLITUDE = 40 IRE

REFERENCE COLOR BURST(9 CYCLES)

7 CYCLESOF 0.5035 MHz

(CLOCKRUN-IN)TWO 7-BIT + PARITYASCII CHARACTERS

(DATA)

27.382 s

BYTE 0 BYTE 1

10.5±0.25 s

ADDRESS & DATA

RUN-IN CLOCK

TELETEXT VBI LINE

45 BYTES (360 BITS) – PAL


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Figure 34 NTSC Composite (VDAC) Line Output Waveform

Figure 35 PAL Composite (VDAC) Line Output Waveform

92.5 IRE

30.8 IRE

82.7 IRE

89.5 IRE100 IRE

40 IRE

40 IRE

7.5 IRE

IDEALW

HIT

E

YE

LLO

W

CY

AN

GR

EE

N

MA

GE

NT

A

RE

D

BLU

E

BLA

CK

(CCIR-624-4 Scaled to 40 IRE Sync)

DVE NTSC SQSimulation

Code V IRE

954 1.233 172.7

774 1.001 140.1

715 0.924 129.4

476 0.616 86.2

336 0.434 60.8

263 0.340 47.6

221 0.286 40.0

106 0.138 19.3

83 0.108 15.1

0 0.000 0.0

234mv (32.7 IRE)

627mv (87.8 IRE)

620mv (86.8 IRE)700mv (98 IRE)

300mv (42 IRE)

300mv

IDEAL

WH

ITE

YE

LLO

W

CY

AN

GR

EE

N

MA

GE

NT

A

RE

D

BLU

E

BLA

CK

(CCIR-624-4 Scaled to 300mv Sync)

DVE PAL SQSimulation

Code V IRE

960 1.241 173.8

774 1.001 140.1

712 0.921 128.9

464 0.600 84.0

349 0.451 63.1

232 0.300 42.0

115 0.149 20.8

46 0.060 8.4

0 0.000 0.0


ES6425 DATA SHEET


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Figure 36 Luma (YDAC) Line Output Waveform

Figure 37 Chroma (CDAC) Line Output Waveform

White Level

100 IRE

7.5

40 IRE

IDEAL

WH

ITE

YE

LLO

W

CY

AN

GR

EE

N

MA

GE

NT

A

RE

D

BLU

E

BLA

CK

(CCIR-624-4 Scaled to 40 IRE Sync)


Code V IRE

387 1.001 140.1

716 0.926 129.6

476 0.615 86.2

322 0.416 58.3

263 0.340 47.6

221 0.286 40.0

0 0.000 0.0

18.0

Sync Level

Blank Level

Setup Step

100

89.5

72.3

61.8

45.7

35.2

620 0.802 112.2

561 0.725 101.5

417 0.539 75.5

Burst Level

20 IRE 40 IR

E20 IRE

IDEAL (CCIR-624-4 Scaled to 40 IRE Sync)

82.7

IRE

WH

ITE

YE

LLO

W

CY

AN

GR

EE

N

MA

GE

NT

A

RE

D

BLU

E

BLA

CK

117.

7 IR

E

109.

3 IR

E

109.

3 IR

E

82.7

IRE

117.

7 IR

E


Code V IRE

847 1.095 153.3826 1.068 149.6

512 0.662 92.7

398 0.514 72.0

273 0.353 49.4

199 0.257 36.0178 0.230 32.2

626 0.810 113.4

752 0.972 136.1


Code V IRE

847 1.095 153.4827 1.069 149.7

512 0.662 92.7

273 0.353 49.4

199 0.257 36.0178 0.231 32.3

752 0.972 136.1


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Figure 38 Sync and Pixel Clock Timings

NTSC

PAL

:line1:

:line1:

:line2:

:line2:

:line19:

:line23:

122 Period

132 Period

Field 1

NTSC

PCLK2X

PCLK

YUV[7:0]

. . . . .

. . . . .

. .. . . . .

. . . . . . .

PAL

:line 263:

:line 313:

:line 264:

:line 314:

:line 281:

:line 336:

122 Period

132 Period

VSYNC#

HSYNC# . . . . . . . .

Field 2

. . .

. . .

. . . .

YUV[7:0] CB0

PCLK2X

PCLK

. . . . .

. . . . .

. .. . . . .

. . . . . . .

VSYNC#

HSYNC# . . . . . . . . . . . . .

3 Lines/NTSC2.5 Lines/PAL

Y0 CR0 Y1

63.5 Period. . . .

. . . .

. . . . . . . .

CB0 Y0 CR0 Y1

63.5 Period. . . . . . . . . . . .

. . .

. . . .

1 Period = 1 Pixel Clock

CB1

CB1


ES6425 DATA SHEET

ELECTRICAL SPECIFICATIONS

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Absolute Maximum Ratings

Recommended Operating Conditions

Power Dissipation

WARNING: Stress beyond those listed under the AbsoluteMaximum Ratings may cause permanent damage to the device.This is a stress rating only, and functional operation of the deviceat these or any other conditions beyond those indicated in theRecommended Operating Conditions section of this specificationis not implied. Exposure to the Absolute Maximum Ratingsconditions for extended periods may affect device reliability.

WARNING: Electrostatic Discharge (ESD) can damage thisdevice. Proper procedures must be followed to avoid ESD whenhandling this device.

Electrical characteristics for the ES6425 are listed in Table13 through Table 16.

DC Electrical Characteristics

Storage temperature range –65° C to 150° C

Operating temperature range 0° C to 70° C

Voltage range for 5V tolerant input pins

–0.5 V to +5.5 V

Voltage range on all other pins –0.5 V to (VEE +0.5 V)

Operating temperature range 0° C to 70° C

Supply voltage VCC 2.00V±100 mV; 320 mA nominal

Supply voltage VEE 3.30V±100 mV; 55 mA nominal

Supply voltage AVEE 3.30V±100 mV; 5 mA nominal

Supply voltage ADVEE 3.30V±100 mV; 200 mA nominal

Power dissipation 1.5 W

Table 13 DC Electrical Characteristics

Symbol Parameter Minimum Maximum Unit Comments

VIH High-level input voltage2.0 VEE V

All inputs TTL levels except CLK and 5V tolerant input pins

2.0 5.5 V All 5V tolerant inputs (*)

VIL Low-level input voltage –0.3 0.8 V All inputs TTL levels except CLK

VCLKH CLK high-level input 2.0 VEE +0.25V TTL level input

VCLKL CLK low-level input –0.3 0.8

VOH High-level output voltage 3.0 — V IOH = 1 mA

VOL Low-level output voltage — 0.45 V IOL = 4 mA

ILI Input leakage current — ±15µA

ILO Output leakage current — ±15

CIN Input capacitance — 10pF fc = 1 MHz

CO Input/output capacitance — 12

CCLK CLK capacitance — 20 pF fc = 1 MHz

(*) RESET#, TDMDR, TDMCLK, TDMFS, SPDIF_IN, RSD, RWS, RBCK, DCLK, AUX3[2], VSYNC#/AUX3[1], HSYNC#/AUX3[0], HD[7:0]/DCI[7:0]/AUX1[7:0], HD8/DCI_FDS#/AUX2[0], HD9/AUX2[1], HD10/AUX2[2], HD11/AUX2[3], HD12/AUX2[4]/C2PO, HD13/AUX2[5], HD14/AUX2[6], HD15/IR/AUX2[7], AUX4[1:0], DCI_ERR#/AUX4[7], AUX3[5], AUX3[3], DCI_CLK/AUX4[5], DCI_ACK#/AUX4[6], AUX3[4], AUX3[7], AUX3[6], AUX4[4:2], I2CDATA/AUX0, I2C_CLK/AUX1, AUX[7:2], and LD[15:0].


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AC Electrical Characteristics

Table 14 Video DAC DC Electrical Characteristics

Parameters Minimum Typical Maximum Unit

DAC resolution — 10 — bits

Integral linearity (INL) — ±2 ±2LSB

Differential linearity error (DNL) — ±0.5 ±1

Gain error — — ±5 %

DAC output impedance — 20K — Ω

Output current-DAC 33.5 35.2 36.5 mA

Internal reference voltage (VREF) 1.17 1.235 1.29 V

Output load 34 37.5 42 Ω

Output capacitance — — 40 pF

Table 15 Video DAC AC Electrical Characteristics


D/A Input Clock Rate — — 15

ns

Clock to Valid Output — — 15

Analog Output Skew — — 30

Output Rise and Fall Time — 8 10

Output Settling Time — — 12

Glitch Energy — 150 300 pYs

Power Dissipation 610 — 670 mW

SLX On to Output Sleep — — 165

nsSLX Off to Output Awake — — 1550

SL On to Output Sleep — — 1665

SL Off to Output Awake — — 62.2 ms

Table 16 VFD Interface Characteristics


VFD Clock Frequency — — TBD MHz

VFD Clock Pulse Width 500 — —

nsVFD Data Setup 50 — —

VFD Data Hold 50 — —

VFD Data Output Delay — — 5


ES6425 DATA SHEET

MECHANICAL DIMENSIONS

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MECHANICAL DIMENSIONSThe mechanical dimensions for the ES6425 are shown inFigure 39.

Figure 39 208-pin Plastic Quad Flat Package (PQFP)

Symbol DescriptionMillimeters

Minimum Nominal Maximum

D Lead to lead, X-axis 30.25 30.60 30.85

D1 Package’s outside, X-axis 27.90 28.0 28.10

E Lead to lead, Y-axis 30.25 30.60 30.85

E1 Package’s outside, Y-axis 27.90 28.00 28.10

A1 Board standoff 0.25 0.33 0.42

A2 Package thickness 3.17 3.37 3.67

b Lead width 0.17 0.20 0.27

e Lead pitch — 0.50 —

e1 Lead gap 0.23 0.30 0.33

L Foot length 0.35 — 0.75

L1 Lead length — 1.30 —

— Foot angle 0° — 7°

— Coplanarity — — 0.102

— Number of leads in X-axis — 52 —

— Number of leads in Y-axis — 52 —

— Total number of leads — 208 —

— Package type — PQFP —

For lead-free devices, the solder paste and PCB finish/plating must be 100% lead free in order to

ensure proper solderability. (Cu = Copper, Sn = Tin, Bi = Bismuth).

E1

A2 A1

L

E

D1

b

D

ES6425e

1

e1

L1208-Pin PQFP


ES6425 DATA SHEET

ORDERING INFORMATION

PRELIMINARY

No part of this publication may be reproduced, stored in a retrieval MPEG is the Moving Picture Experts Group of the ISO/IEC. References

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ORDERING INFORMATION

Other DMP Processors

Part Number Description Package

ES6425F Digital Media Processor 2 208-pin PQFP

The letter F at the end of the part number identifies the package type PQFP.

Part Number Description Package

ES6425FF Digital Media Processor 2 with lead-free leads. 208-pin PQFP

The second letter F at the end of the part number indicates lead-free leads with the device.

68 http://www.esstech.com © 2004 ESS Technology, Inc. SAM0530-082704

system, transmitted, or translated in any form or by any means,electronic, mechanical, manual, optical, or otherwise, without the priorwritten permission of ESS Technology, Inc.

ESS Technology, Inc. makes no representations or warrantiesregarding the content of this document.

All specifications are subject to change without prior notice.

ESS Technology, Inc. assumes no responsibility for any errorscontained herein.

U.S. patents pending.

to MPEG in this document refer to the ISO/IEC JTC1 SC29 committeedraft ISO 11172 dated January 9, 1992.

Vibratto, SmartBright, SmartLogo, SmartColor, and Music Slideshoware trademarks of ESS Technology, Inc.

Dolby is a trademark of Dolby Laboratories, Inc.

Trusurround, Trusurround XT, SRS, and (o) symbol are trademarks ofSRS Labs., Inc.

All other trademarks are trademarks of their respective companies andare used for identification purposes only.

ESS Technology, Inc.48401 Fremont Blvd.Fremont, CA 94538Tel: (510) 492-1088Fax: (510) 492-1898

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