Ers Prac 3 Report

8/2/2019 Ers Prac 3 Report

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DEPARTMENT OF ELECTRICAL, ELECTRONIC AND COMPUTER ENGINEERING

DIGITAL SYSTEMS ERS 220

PRACTICAL 3: Sequential logic circuit design

A game of Ping-Pong.

DATE: 24/10/2011

Name: Frederick Schalk Montgomery Student no. 10030868

Name: Joshua Leigh Sendall Student no. 10029924

Name: Sebastian Sylvo Volker Student no. 10000543

Name: Danil Andr van der Walt Student no. 10042088


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DECLARATION OF ORIGINALITY

UNIVERSITY OF PRETORIA

The Department of places great emphasis upon

integrity and ethical conduct in the preparation of all written work submitted for academic evaluation.

While academic staff teach you about referencing techniques and how to avoid plagiarism, you too have

a responsibility in this regard. If you are at any stage uncertain as to what is required, you should speak

to your lecturer before any written work is submitted.

You are guilty of plagiarism if you copy something from another authors work (eg a book, an article or a

website) without acknowledging the source and pass it off as your own. In effect you are stealing

something that belongs to someone else. This is not only the case when you copy work word-for-word

(verbatim), but also when you submit someone elses work in a slightly altered form (paraphrase) or use

a line of argument without acknowledging it. You are not allowed to use work previously produced by

another student. You are also not allowed to let anybody copy your work with the intention of passing if

off as his/her work.

Students who commit plagiarism will not be given any credit for plagiarized work. The matter may also be

referred to the Disciplinary Committee (Students) for a ruling. Plagiarism is regarded as a serious

contravention of the Universitys rules and can lead to expulsion from the University.

The declaration which follows must accompany all written work submitted while you are a student of the

Department of .......................................................................... No written work will be accepted

unless the declaration has been completed and attached.

Full names of student: ............................................................................

Student number: ............................................................................

Topic of work: ................................................................ ............

Declaration

1. I understand what plagiarism is and am aware of the Universitys policy in this regard.

2. I declare that this (eg essay, report, project, assignment,

dissertation, thesis, etc) is my own original work. Where other peoples work has been used (either from

a printed source, Internet or any other source), this has been properly acknowledged and referenced in

accordance with departmental requirements.

3. I have not used work previously produced by another student or any other person to hand in asmy own.

4. I have not allowed, and will not allow, anyone to copy my work with the intention of passing it

off as his or her own work.

SIGNATURE

...................................................................................................................................


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Contents

List of Figures ............................................................................................................................................... iii

AIM OF THE PRACTICAL ................................................................................................................................ 1

METHOD ........................................................................................................................................................ 1

RESULTS ........................................................................................................................................................ 2

CONCLUSION ............................................................................................................................................... 14

BIBLIOGRAPHY ............................................................................................................................................ 14

List of Figures

Figure 1, State diagram. ................................................................................................................................ 2

Figure 2, Logical OR gate truth table. ........................................................................................................... 3

Figure 3, Logical AND gate truth table. ......................................................................................................... 3

Figure 4, Logical XOR gate truth table. ......................................................................................................... 3Figure 5, Logical INVERTER truth table. ........................................................................................................ 3

Figure 6, Excitation table. ............................................................................................................................. 5

Figure 7, S0* Excitation map. ........................................................................................................................ 6

Figure 8, S1* Excitation map. ........................................................................................................................ 7

Figure 9, Circuit 1. ......................................................................................................................................... 8

Figure 10, Circuit 2. ....................................................................................................................................... 9

Figure 11, Circuit 3. ..................................................................................................................................... 10

Figure 12, Circuit 4. ..................................................................................................................................... 11

Figure 13, Circuit 5. ..................................................................................................................................... 11

Figure 14, Circuit 6. ..................................................................................................................................... 12Figure 15, Circuit 7. ..................................................................................................................................... 13

Figure 16, Circuit 8. ..................................................................................................................................... 13
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AIM OF THE PRACTICAL

The aim of this practical project was to successfully implement the aspect of memory in sequential logic

circuits to create a game of Ping-Pong. The game would be played by two players, each controlling apaddle consisting of two parts, an upper half as well as a lower half. Therefore it can be seen as a

game of doubles.

The constraints for this project were detailed by the rules that had to be designed into the game. A

working implementation of a scoring system between the two players was attempted seeing as extra

marks would be awarded for extra effort.

An appropriate hypothesis for this project is that it will have to be a Mealy machine design, seeing as

inputs and current states will have to influence future states.

METHOD

Firstly, following the design principles stated in (Wakerley, 2007), the project was divided into three

parts, i.e. Next-State Logic, State Memory and Output Logic. A state diagram was then constructed

according to the word description of the problem given, to account for every possible situation in the

game. Secondly, the Excitation table and Excitation maps were constructed to relate inputs and current

states to next/future states.

It was chosen not to implement state registers, but rather only bit counters in conjunction with

decoders and a clock signal. The design of the court was expanded into a two-dimensional LED array

where the ball exhibited dynamic behaviour. The players would play the game by using the remote,

which allows for a comfortable and exciting gaming experience.

After the theoretical design of the project had been completed, the actual layout of the circuit had to be

designed and built. The circuit design was created using PSPICE and ORCAD software. After this step had

been completed, the actual circuit was realised using several logic gates, flip-flops, bit-counters, LEDs

and so forth.

Finally, the project also had to be coded in VHDL format. This was done only after the circuit had been

completely constructed.


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RESULTSState diagram

LPB = Left Push Button

RPB = Right Push Button

LL = Left Lamp

RL = Right Lamp

In figure 1 it can be seen that scoring has not yet been implemented. After scoring has been taken into

account, it adds two more states to the above diagram i.e. one state being Player1 wins and the other

being Player2 wins.

Figure 1, State diagram.


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Truth and Excitation tables

Displayed below are the truth tables for the logic gates implemented in the design as well as the

Excitation table which relates Next-State logic and Current-State logic.

Figure 2, Logical OR gate truth table.

Figure 3, Logical AND gate truth table.

Figure 4, Logical XOR gate truth table.

Figure 5, Logical INVERTER truth table.


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S0 S1 LPB RPB L-LAMP R-LAMP S0* S1*

0 0 0 0 0 0 0 0

0 0 0 0 0 1 0 0

0 0 0 0 1 0 0 1

0 0 0 0 1 1 d d0 0 0 1 0 0 0 0

0 0 0 1 0 1 d d

0 0 0 1 1 0 1 1

0 0 0 1 1 1 d d

0 0 1 0 0 0 0 1

0 0 1 0 0 1 0 1

0 0 1 0 1 0 1 1

0 0 1 0 1 1 d d

0 0 1 1 0 0 0 00 0 1 1 0 1 0 1

0 0 1 1 1 0 1 1

0 0 1 1 1 1 d d

0 1 0 0 0 0 d d

0 1 0 0 0 1 0 0

0 1 0 0 1 0 d d

0 1 0 0 1 1 d d

0 1 0 1 0 0 d d

0 1 0 1 0 1 0 10 1 0 1 1 0 d d

0 1 0 1 1 1 d d

0 1 1 0 0 0 d d

0 1 1 0 0 1 0 1

0 1 1 0 1 0 d d

0 1 1 0 1 1 d d

0 1 1 1 0 0 d d

0 1 1 1 0 1 0 1

0 1 1 1 1 0 d d0 1 1 1 1 1 d d

1 1 0 0 0 0 d d

1 1 0 0 0 1 d d

1 1 0 0 1 0 1 0

1 1 0 0 1 1 d d


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1 1 0 1 0 0 d d

1 1 0 1 0 1 d d

1 1 0 1 1 0 1 1

1 1 0 1 1 1 d d

1 1 1 0 0 0 d d1 1 1 0 0 1 d d

1 1 1 0 1 0 1 1

1 1 1 0 1 1 d d

1 1 1 1 0 0 d d

1 1 1 1 0 1 d d

1 1 1 1 1 0 1 1

1 1 1 1 1 1 d d

1 0 0 0 0 0 1 0

1 0 0 0 0 1 1 11 0 0 0 1 0 1 0

1 0 0 0 1 1 d d

1 0 0 1 0 0 1 1

1 0 0 1 0 1 0 0

1 0 0 1 1 0 1 1

1 0 0 1 1 1 d d

1 0 1 0 0 0 0 1

1 0 1 0 0 1 0 1

1 0 1 0 1 0 d d1 0 1 0 1 1 d d

1 0 1 1 0 0 1 0

1 0 1 1 0 1 0 1

1 0 1 1 1 0 d d

1 0 1 1 1 1 d d

Figure 6, Excitation table.

Figure 6 above shows the relationship between the Next-State logic and Current-State logic. In each of

these states, the outputs of the circuit were clearly defined, the outputs being the LED array as well as

the scoring implementation. This is the Excitation table that was used to generate the Excitation maps in

order to obtain the simplified excitation equations.


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Excitation maps

Map for S0*

Using Product-of-Sums for the above Excitation map yields:

S0*= (S0 + S1 + LPB + RPB).(RPB + RL).(S0 + LPB + RPB).(S0 + LL)

This equation represents the next value of S0 as a function of the inputs and previous states. This

confirms the Mealy machine design hypothesis.

Figure 7, S0* Excitation map.


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Map for S1*

Using Sum-of-Products for the Excitation Map above yields:

S1* = LPB(RPB + RL) + RPB(LL + S0.RL + S0.LPB.RL) + (S0.LPB.RL) + (S0.LL + RL)

This equation represents the next value of S1 as a function of the inputs and previous states. This

confirms the Mealy machine design hypothesis.

The two excitation equations, given by S0* and S1*, were implemented by using normal combinational

logic design, i.e. logical AND, OR and NOT gates. Seeing as SO* and S1* are both functions of the inputs

and current states, the scoring implementation would also have to be dependent on these inputs andstates. The scoring implementation was formally described by the following equations:

Score_Player_1= S1.S0.(RPB XOR RL)

Score_Player_2= S1.S0.(LPB XOR LL)

Figure 8, S1* Excitation map.


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Bit

Counter

S1CLKS0

CLK

CLR

Circuit Diagram 1: LED implementation Part1

Wires leading from the

3-8 decoder to the

LED's

3-8 Decoder

1

2

3

1

2

3

1

2

3

Circuit diagrams

Please refer to the diagrams below for the full representation of the logic circuit. Please also note that in

the logic diagrams, each logic gate is actually situated within its own specific IC (Integrated Circuit).

These ICs are all supplied with 5 Volts DC to enable proper functionality of the logic gates housed

within.

Figure 9, Circuit 1.


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560

560

560

560

Wires leading to

the 3-8 decoder

Wires leading

to the 4-2

decoder

Circuit Diagram 2: LED implementation Part 2



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Bit

Counter

CLK

4-2

Decoder

Wires leading

to the LEDs

1

2

3

1

2

3

1

2 3

CLK Q

1

23

CLK (LL + RL)'

Circuit Diagram 3: LED implementation Part 3



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UU L L

12

4 5

6

34

1 2

3

5.6k5.6k

VCCVCC

1 2

45

6

3 4

12

3

To main circuit board

Circuit Diagram 6: Remote Control logic layout

Right Push ButtonLeft Push Button



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Circuit Diagram 7: Scoring implementation Part 1

1

2

3

1

2

3

1

2

3

1

2

3

1

2

3

1

2

3

12

12

12

RPB

S0

S1

LL

LPB

S0

S1

RL

Score_Player_2

Score_Player_1

Score_Player_1

Clock

Score_Player_2

Player_1 Seven Segment

Player_2 Seven Segment

Circuit Diagram 8: Scoring implementation Part 2

7474

D2

CLK3

Q5

Q6

PRE4

CLR1

7474

D12

CLK11

Q9

Q8

PRE10

CLR13

74196

A4

B10

C3

D11

CLK18

CLK26

LOAD1

CLR13

QA5

QB9

QC2

QD12




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CONCLUSION

It can be seen that a fully functional sequential logic circuit can be implemented to create a game of

Ping-Pong. Throughout this project, it was seen that memory forms an integral part of the design of

sequential logic circuits and also that memory can be used to perform a large variety of tasks.

BIBLIOGRAPHY

Digital Systems ERS 220. Studyguide. Digital Systems ERS 220. [Online].Available:

. [Accessed 19 October

2011].

Wakerley, J. (2007). Digital Design: Principles and Practices 4th Edition. Pearson Prentice Hall.
http://www.ee.up.ac.za/main/en/undergrad/subjects/ers220/indexhttp://www.ee.up.ac.za/main/en/undergrad/subjects/ers220/index

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