EPC2012 – Enhancement Mode Power...
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eGaN® FET DATASHEET EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2012 | | PAGE 1 EPC2012 EPC2012 – Enhancement Mode Power Transistor V DSS , 200 V R DS(ON) , 100 mW I D , 3 A Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment leverag- ing the infrastructure that has been developed over the last 55 years. GaN’s exceptionally high elec- tron mobility and low temperature coefficient allows very low R DS(ON) , while its lateral device structure and majority carrier diode provide exceptionally low Q G and zero Q RR . The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate. EPC2012 eGaN® FETs are supplied only in passivated die form with solder bars Applications • High Speed DC-DC conversion • Class D Audio • Hard Switched and High Frequency Circuits Benefits • Ultra High Efficiency • Ultra Low R DS(on) • Ultra low Q G • Ultra small footprint EFFICIENT POWER CONVERSION Maximum Ratings V DS Drain-to-Source Voltage 200 V I D Continuous (T A =25˚C, θ JA = 70) 3 A Pulsed (25˚C, Tpulse = 300 μs) 15 V GS Gate-to-Source Voltage 6 V Gate-to-Source Voltage -5 T J Operating Temperature -40 to 125 ˚C T STG Storage Temperature -40 to 150 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Static Characteristics (T J = 25˚C unless otherwise stated) BV DSS Drain-to-Source Voltage V GS = 0 V, I D = 60 μA 200 V I DSS Drain Source Leakage V DS = 160 V, V GS = 0 V 10 50 μA I GSS Gate-Source Forward Leakage V GS = 5 V 0.2 1 mA Gate-Source Reverse Leakage V GS = -5 V 0.1 0.5 V GS(TH) Gate Threshold Voltage V DS = V GS , I D = 1 mA 0.7 1.4 2.5 V R DS(ON) Drain-Source On Resistance V GS = 5 V, I D = 3 A 70 100 mΩ Source-Drain Characteristics (T J = 25˚C unless otherwise stated) V SD Source-Drain Forward Voltage I S = 0.5 A, V GS = 0 V, T = 25˚C 1.9 V I S = 0.5 A, V GS = 0 V, T = 125˚C 2 All measurements were done with substrate shorted to source. NEW PRODUCT HAL Thermal Characteristics R θJC Thermal Resistance, Junction to Case 7.6 ˚C/W R θJB Thermal Resistance, Junction to Board 36 ˚C/W R θJA Thermal Resistance, Junction to Ambient (Note 1) 85 ˚C/W TYP Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board. See http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
Transcript of EPC2012 – Enhancement Mode Power...
eGaN® FET DATASHEET
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2012 | | PAGE 1
EPC2012
EPC2012 – Enhancement Mode Power Transistor
VDSS , 200 VRDS(ON) , 100 mWID , 3 A
Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment leverag-ing the infrastructure that has been developed over the last 55 years. GaN’s exceptionally high elec-tron mobility and low temperature coefficient allows very low RDS(ON), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate. EPC2012 eGaN® FETs are supplied only in
passivated die form with solder bars
Applications• HighSpeedDC-DCconversion• ClassDAudio• HardSwitchedandHighFrequencyCircuits
Benefits• UltraHighEfficiency• UltraLowRDS(on)
• UltralowQG
• Ultrasmallfootprint
EFFICIENT POWER CONVERSION
Maximum Ratings
VDS Drain-to-Source Voltage 200 V
ID
Continuous (TA =25˚C, θJA = 70) 3A
Pulsed (25˚C, Tpulse = 300 µs) 15
VGS
Gate-to-Source Voltage 6V
Gate-to-Source Voltage -5
TJ Operating Temperature -40 to 125˚C
TSTG Storage Temperature -40 to 150
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Static Characteristics (TJ= 25˚C unless otherwise stated)
BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 60 µA 200 V
IDSS Drain Source Leakage VDS = 160 V, VGS = 0 V 10 50 µA
IGSS
Gate-Source Forward Leakage VGS = 5 V 0.2 1mA
Gate-Source Reverse Leakage VGS = -5 V 0.1 0.5
VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 1 mA 0.7 1.4 2.5 V
RDS(ON) Drain-Source On Resistance VGS = 5 V, ID = 3 A 70 100 mΩ
Source-Drain Characteristics (TJ= 25˚C unless otherwise stated)
VSD Source-Drain Forward VoltageIS = 0.5 A, VGS = 0 V, T = 25˚C 1.9
VIS = 0.5 A, VGS = 0 V, T = 125˚C 2
Dynamic Characteristics (TJ= 25˚C unless otherwise stated)
CISS Input Capacitance
VDS = 100 V, VGS = 0 V
VDS = 100 V, VGS = 0 V
128 145
pFCOSS Output Capacitance 73 95
CRSS Reverse Transfer Capacitance 3.3 4.4
QG Total Gate Charge (VGS = 5 V)
VDS = 100 V, ID = 3 A
1.5
nC
QGD Gate to Drain Charge 0.57
QGS Gate to Source Charge 0.33
QOSS Output Charge 11
1.8
0.75
0.41
14
QRR Source-Drain Recovery Charge 0
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
All measurements were done with substrate shorted to source.
All measurements were done with substrate shorted to source.
NEW PRODUCT
HAL
Thermal Characteristics
RθJC Thermal Resistance, Junction to Case 7.6 ˚C/W
RθJB Thermal Resistance, Junction to Board 36 ˚C/W
RθJA Thermal Resistance, Junction to Ambient (Note 1) 85 ˚C/W
TYP
Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board. See http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
eGaN® FET DATASHEET
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2012 | | PAGE 2
EPC2012I D
– Dr
ain
Curre
nt (A
)
VDS – Drain to Source Voltage (V)
15
10
5
00 0.5 1 1.5 2
VGS = 5VGS = 4VGS = 3VGS = 2
I D –
Drai
n Cu
rrent
(A)
VGS – Gate to Source Voltage (V)
15
10
5
00 0.5 1.5 1 2 2.5 3 3.5 4 4.5
25˚C125˚C
VD = 3 V
R DS(
ON) –
Dra
in to
Sour
ce R
esist
ance
(mΩ
)
VGS – Gate to Source Voltage (V)
200
150
100
50
02.5 2 3 3.5 4 4.5 5 5.5
ID = 3 AID = 6 AID = 10 AID = 15 A R D
S(ON
) – D
rain
to So
urce
Res
istan
ce (mΩ
)
VGS – Gate to Source Voltage (V)
250
200
100
50
150
02 2.5 3 3.5 4 4.5 5 5.5
ID = 3 A
25˚C125˚C
Figure 1: Typical Output Characteristics Figure 2: Transfer Characteristics
Figure 3: RDS(ON) vs. VGS for Various Drain Currents Figure 4: RDS(ON) vs. VGS for Various Temperatures
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Static Characteristics (TJ= 25˚C unless otherwise stated)
BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 60 µA 200 V
IDSS Drain Source Leakage VDS = 160 V, VGS = 0 V 10 50 µA
IGSS
Gate-Source Forward Leakage VGS = 5 V 0.2 1mA
Gate-Source Reverse Leakage VGS = -5 V 0.1 0.5
VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 1 mA 0.7 1.4 2.5 V
RDS(ON) Drain-Source On Resistance VGS = 5 V, ID = 3 A 70 100 mΩ
Source-Drain Characteristics (TJ= 25˚C unless otherwise stated)
VSD Source-Drain Forward VoltageIS = 0.5 A, VGS = 0 V, T = 25˚C 1.9
VIS = 0.5 A, VGS = 0 V, T = 125˚C 2
Dynamic Characteristics (TJ= 25˚C unless otherwise stated)
CISS Input Capacitance
VDS = 100 V, VGS = 0 V
VDS = 100 V, VGS = 0 V
128 145
pFCOSS Output Capacitance 73 95
CRSS Reverse Transfer Capacitance 3.3 4.4
QG Total Gate Charge (VGS = 5 V)
VDS = 100 V, ID = 3 A
1.5
nC
QGD Gate to Drain Charge 0.57
QGS Gate to Source Charge 0.33
QOSS Output Charge 11
1.8
0.75
0.41
14
QRR Source-Drain Recovery Charge 0
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
All measurements were done with substrate shorted to source.
All measurements were done with substrate shorted to source.
eGaN® FET DATASHEET
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2012 | | PAGE 3
EPC2012I SD
– So
urce
to D
rain
Curre
nt (A
)
VSD – Source to Drain Voltage (V)
15
10
5
00 0.5 1 1.5 2 2.5 3 4 4.53.5
25˚C125˚C
Norm
alize
d On-
Stat
e Res
istan
ce –
RDS
(ON)
TJ – Junction Temperature ( ˚C )
1.6
1.8
1.4
1.2
1
0.8-20 0 20 40 60 80 100 120 140
ID = 3 AVGS = 5 V
I G –
Gate
Curre
nt (A
)
VGS – Gate-to-Source Voltage (V)
.025
.02
.015
.01
.005
00 1 2 3 4 5 6
25˚C125˚C
Norm
alize
d Thr
esho
ld Vo
ltage
(V)
1
1.2
1.4
1.6
0.8
0.6
0.4
0.2-20 0 20 40 60 80 100 120 140
ID = 1 mA
Figure 7: Reverse Drain-Source Characteristics Figure 8: Normalized On Resistance vs. Temperature
Figure 10: Gate CurrentFigure 9: Normalized Threshold Voltage vs. Temperature
TJ – Junction Temperature ( ˚C )
V G –
Gat
e Vol
tage
(V)
C – Ca
pacit
ance
(nF)
VDS – Drain to Source Voltage (V)
0.05
0.1
0.15
0.2
0.25
00 50 100 150 200
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
QG – Gate Charge (nC)
5
4
3
2
1
00 0.5 1 1.5 2
ID = 3 AVD = 100 V
Figure 5: Capacitance Figure 6: Gate Charge
All measurements were done with substrate shortened to source.
eGaN® FET DATASHEET
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2012 | | PAGE 4
EPC2012
Figure 11: Transient Thermal Response Curves
Figure 12: Safe Operating Area
Duty Factors:
Notes:Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJB x RθJB + TB
PDM
t1
t2
0.50.20.10.050.020.01
Single Pulse
1
0.1
0.01
0.001
0.000110-5 10-4 10-3 10-2 10-1 1 10 100
Normalized Maximum Transient Thermal Impedance
tp, Rectangular Pulse Duration, seconds
Z θJB
, Nor
mal
ized T
herm
al Im
peda
nce
Normalized Maximum Transient Thermal Impedance
tp, Rectangular Pulse Duration, seconds
Duty Factors:
Notes:Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJC x RθJC + TC
PDM
t1
t2
0.5
0.2
0.1
0.05
0.02
0.01
Single Pulse
1
0.1
0.01
0.001Z θJC
, Nor
mal
ized T
herm
al Im
peda
nce
10-510-6 10-4 10-3 10-2 10-1 1
0.01
0.1
1
10
100
0.1 1 10 100 1000
I D- D
rain
Curre
nt (A
)
VDS - Drain-Source Voltage (V)
limited by RDS(ON)
TJ = Max Rated, TC = +25°C, Single Pulse
10 µs
100 µs
1 ms
10 ms100 ms/DC
eGaN® FET DATASHEET
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2012 | | PAGE 5
EPC2012
DIE OUTLINESolder Bar View
Side View
Bcd X2
1
3 42
d
e g g
fx2
A
815 M
ax
100 +
/- 20
SEATING PLANE
(685
)
DIM MIN Nominal MAX
A 1.681 1.711 1.741B 0.889 0.919 0.949c 0.660 0.663 0.666d 0.251 0.254 0.257e 0.230 0.245 0.260f 0.251 0.254 0.257g 0.600 0.600 0.600
MILLIMETERS
a
d e f g
c
b
EPC2012 (note 1) Dimension (mm) target min max
a 8.00 7.90 8.30 b 1.75 1.65 1.85
c (note 2) 3.50 3.45 3.55 d 4.00 3.90 4.10 e 4.00 3.90 4.10
f (note 2) 2.00 1.95 2.05 g 1.5 1.5 1.6
TAPE AND REEL CONFIGURATION4mm pitch, 8mm wide tape on 7” reel
Note 1: MSL1 (moisture sensitivity level 1) classi�ed according to IPC/JEDEC industry standard.Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole.
Dieorientation
dot
Gatesolder bar is
under thiscorner
Die is placed into pocketsolder bar side down
(face side down)
7” reel
Loaded Tape Feed Direction
2012
YYYY
ZZZZ
Die orientation dot
Gate Pad solder bar is under this corner
Part Number
Laser Markings
Part #Marking Line 1
Lot_Date CodeMarking line 2
Lot_Date CodeMarking Line 3
EPC2012 2012 YYYY ZZZZ
DIE MARKINGS
eGaN® FET DATASHEET
EPC – EFFICIENT POWER CONVERSION CORPORATION | WWW.EPC-CO.COM | COPYRIGHT 2012 | | PAGE 6
EPC2012
RECOMMENDEDLAND PATTERN (units in µm)
Pad no. 1 is Gate
Pad no. 2 is Substrate
Pad no. 3 is Drain
Padno.4isSource
The land pattern is solder mask defined
Information subject to change without notice.
Revised October, 2012
600
409
600
919
1711
234 X2
234
643
234 1 1
3 4 3 4
2 2
600
409
600
919
1711
234 X2
234
643
234 1 1
3 4 3 4
2 2
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any productor circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Efficient Power Conversion Corporation.
