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• Entity declaration

– describes the input/output ports of a module

entity reg4 isport ( d0, d1, d2, d3, en, clk : in std_logic;

q0, q1, q2, q3 : out std_logic );end entity reg4;

entity nameport mode (direction)

port typereserved words

punctuation

Port Name

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Modeling Behavior

• Architecture body– describes an implementation of an entity– may be several per entity

• Behavioral architecture– describes the algorithm performed by the module– contains

• process statements, • Function• Statement1• Port interface

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Modeling Structure

• Structural architecture– implements the module as a composition of

subsystems– contains

• signal declarations, for internal interconnections– the entity ports are also treated as signals

• component declarations– instances of previously declared entity/architecture pairs

• port maps in component instances– connect signals to component ports

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Component Declaration

Component Component-name [is]

[port (list-of-interface-port);]

End component [component-name];

Component-name: may or may not refer to the name of an entity already existing in a library.

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Component cont..

• List-of-interface-port specifies the name,mode, and type for each port of the component in a manner similar to that specified in an entity declaration.

• The names of the ports may also be different from the names of the ports in the entity to which it may be bound.

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Component declaration

• Component declaration appear in the declaration part of an architecture body.

• They may also appear in a package declaration

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Signal declaration

• Are required to connect different types of ports.(mode of ports)

• Class of the object identifier

• Signal object should be same data type as it is in component and entity.

• Signal object can be also be declared as an array

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Component Instantiation

• A Component instantiation statement defines a subcomponent of the entity in which it appears.

• It associates the signals in the entity with the ports of that subcomponent.

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Format of a component Instantiation statement

Component-label : component-name [port map (association-list)];

* Component-label: It can be any legal identifier and can be considered as the name of the instance.

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Component instantiation

• The component-name must be the name of a component declared earlier using a component declaration.

• The association-list associates signals in the entity, called actuals, with the ports of a component, called formals.

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Association technique

• There are two ways to perform the association of formals with actuals:

1. Positional association

2. Named association

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Positional association

• An association-list is of the form:Actual1,actual2,actual3…………………………actualn

The first port in the component declaration corresponds to the first actual in the component declaration corresponds to the first actual in the component instantiation, the second with second, and so on.

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Named association

• An association-list is of the form:

Formal1=>actual1,formal2=>actual2……..formaln=>actualn

In named association, the ordering of the association is not important since the mapping between the actuals and formals is explicitly specified.

The scope of the formals is restricted to be within the port map part of the instantiation for that component.

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Rules of the port map

1. The types of the formal and actual being associated must be the same.

2. The modes of the ports must conform to the rule that if the formal s readable, so must the actual be; and if the formal is considered to be both readable and writeable, such a signal may be associated with a formal of any mode.

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1. If an actual is a port of mode in, it may not be associated with a formal of mode out or inout;

2. if the actuals is a port of mode out, it may not be associated with a formal of mode in or inout;

3. if the actual is a port of mode inout, it may be associated with a formal of mode in,out, or inout.

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Circuit of Half adder

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Circuit of Full adder

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Design a 4-bit adder using FA

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Example (Full adder using macro of Half adder)

library ieee;use ieee.std_logic_1164.all;

entity ha isport ( x, y : in std_logic;

s, c : out std_logic);

end ha;

architecture ha_behave of ha isbegin

s <= x xor y;c <= x and y;

end ha_behave;

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library ieee;use ieee.std_logic_1164.all;entity fa is

port ( xin, yin, zin : in std_logic; cout, sum : out std_logic

);end fa;architecture fa_struct of fa iscomponent ha is

port ( x, y : in std_logic; s, c : out std_logic

);end component ha;signal temp0,temp1,temp2 : std_logic;beginha1 : ha port map (x=>xin,y=>yin,s=>temp0,c=>temp1);ha2 : ha port map (x=>temp0,y=>zin,s=>sum,c=>temp2);

cout <= temp1 or temp2;end fa_struct;

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library ieee;use ieee.std_logic_1164.all;entity fa_4bit isport ( a,b : in std_logic_vector (3 downto 0);

sum : out std_logic_vector (3 downto 0);carry : out std_logic);

end fa_4bit;architecture fa_4bit_behave of fa_4bit is

component fa isport ( xin, yin, zin : in std_logic;cout, sum : out std_logic);

end component fa;signal c : std_logic_vector (3 downto 0);

beginc(0) <= '1';

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u1 : fa port map (xin=>a(0),yin=>b(0),zin=>c(0),sum=>sum(0),cout=>c(1));

u2 : fa port map (xin=>a(1),yin=>b(1),zin=>c(1),sum=>sum(1),cout=>c(2));

u3 : fa port map (xin=>a(2),yin=>b(2),zin=>c(2),sum=>sum(2),cout=>c(3));

u4 : fa port map (xin=>a(3),yin=>b(3),zin=>c(3),sum=>sum(3),cout=>carry);

end fa_4bit_behave;

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Adder-Subtractor using Mode control