International Journal of Nanotechnology and Applications ISSN 0973-631X Volume 2, Number 1 (2008), pp. 89–106 © Research India Publications http://www.ripublication.com/ijna.htm

Implementation of Quantum cellular automata combinational and sequential circuits using Majority

logic reduction method

E.N.Ganesh1, Lal Kishore2 and M.J.S. Rangachar3

1.Reserach scholar JNTU, Hyderabad, India 2.Registrar JNTU, Hyderabad, India

3.HOD, ECE Dept., BSA Crescent Engg. College, India

Abstract

Quantum cellular automata is a promising nanotechnology that has been recognized as one of the top six emerging technology in future computers. In this paper the method of majority voting scheme is used to develop basic QCA combinational and sequential circuits. We developed QCA subtractive algorithm, combinational circuit algorithms for circuit simulation. We also developed simple D and T flip flops using QCA technology. We verified the proposed algorithm using simulation from QCADESINGER tool. These algorithms and simulations are useful for building complex QCA circuits. Keywords: Quantum cellular automata (QCA), Majority Logic voting, Combinational circuits, Sequential circuits. Quantum computation.

Introduction Quantum dots are nanostructures created from standard semi conductive materials. These structures are modeled as quantum wells. They exhibit energy effects even at distances several hundred times larger than the material system lattice constant. A dot can be visualized as well. Once electrons are trapped inside the dot, it requires higher energy for electron to escape. Quantum dot cellular automata is an Novel technology that attempts to create general computational functionality at the nanoscale by controlling the position of single electrons [1][2][8]. The fundamental unit of QCA is QCA cell created with four quantum Dots positioned at the vertices of a square.[1] [8]. The electrons are quantum mechanical particles, they are able to tunnel between the dots in a cell. The electrons in the cell that are placed adjacent to each other will interact; as a result the polarization of one cell will be directly affected by the

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polarization of its neighboring cells. Fig 1 below shows quantum cells with electrons occupying opposite vertices.

1(a) 1(b) Figure 1 : Shows QCA cells with four quantum dots.1(a) P = +1 (Binary 1) 1(b) P = -1 (Binary0) [1][2][4][8] This interaction forces between the neighboring cells able to synchronize their polarization. Therefore an array of QCA cells acts as wire and is able to transmit information from one end to another [5][6]. Thus the information is coded in terms of polarization of cell. Polarization of each cell depends on polarization of its neighboring cells. Quantum Computation To perform logic computing, we require universally a complete logic set. We need a set of Boolean logic gates that can perform AND, OR, NOT and FANIN and FAN OUT Operations. The combination of these is considered as universal because any general Boolean function can be implemented with the combination of these logic primitives. The fundamental method for computing is majority gate or majority voter method [1] [4]. Suppose three inputs are given to QCA circuit, then the output of the QCA structure is tabulated in table 1.

Table 1 : Majority voting scheme [3][4] [5]

INPUT OUTPUT MAJORITY VOTING 000 0 001 0 010 0 011 1 100 0 101 1 110 1 111 1

The majority gate produces an output that reflects the majority of the inputs. The majority function is a part of a larger group of functions called threshold functions.

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Threshold functions works according to inputs that reaches certain threshold before output is asserted. The majority function is most fundamental logic gate in QCA circuits. In order to create an AND gate we simply fix one of the majority gate input to 0 (P = -1). To create OR gate we fix one of inputs to 1 P = +1. The inverter or NOT gate is also simple to implement using QCA. If we place two cells at 45 degrees with respect to each other such that they interact inversely.

Figure 2 : Majority AND gate [6] [11] Control input is -1. Majority e [The output of majority AND gate reflects the majority of the inputs. Suppose input A =1, B = 1, Control input 0(-1), the output is equal to 1.

Figure 3 : Majority OR gate [6][11][12] Figure 2 and 3 shows the majority AND and OR gate structure. Control input to AND gate is -1 and for OR gate is +1. Hence QCA technology can be used to construct universal quantum logic gates. This paper discuss about the basic combinational and sequential circuits using QCA technology. We propose some basic algorithms based on majority voting logic for combinational and sequential circuits like QCA Full substractor, Decoder, Multiplexer, Priority encoder, T and D Flip flops. we followed the same majority voting scheme of construction of QCA circuits as in [ ]. We validate our expressions by comparing the simulated waveforms from QCADESIGNER tool.

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QCA Clocking Clocking is the requirement for synchronization of information flow in QCA circuits. It requires a clock not only to synchronize and control information flow but clock actually provides power to run the circuit [13] [14] [19]. The cells are not powered from any other external source apart from the clock. These clocks have been proposed to control the potential barriers between the dots. When the clock signal is high the potential barriers between the dots are low and electrons effectively spread out in the cell and no net polarization exists.[19] (P = 0). As the clock signal is switched low, the potential barriers between the dots are raised high and the electrons are localized such that a polarization is developed based on the interaction of their neighbors [7][17].In short when clock is high cell is unlatched and when clock is low cell is latched. In order to pump information down a circuit in a controllable manner four clocking zones are available as shown in Figure 4. Each of clocking signal lagging in phase by 90 degrees with respect to one before. In this way, the cells are latched in series and propagate information in the same direction. So clocking is essential for QCA circuits.

Figure 4 : Shows clocking scheme of QCA circuits [4][5][14][15] QCA Combinational circuits Study I - Full adder / Full subtractor QCA Full adder circuit Here we apply Majority logic method for constructing QCA Full subtractor. We review initially Full adder and QCA addition algorithm as given in [1] [2]. Walus etal proposed QCA addition algorithm is very efficient and fast in simplified majority expressions for QCA design circuits. We have taken 1 bit full adder as an example. QCA addition algorithm can be written as Inputs : a,b and c Outputs : Sum , Carry CA

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Equation 1 and 2 gives Sum and carry expressions. _ _ _ _ _ _

Sum = abc + a bc + a b c + a b c (1)

CA = a.b + b.c + c.a (2)

Figure 5 : (a), (b) and (c) Majority AND logic of Equation (2).

Proof 1: Majority logic of Carry in Full adder CA = A.B + B.C + C.A = m(A,B,-1) + m(B,C,-1) +m(C,A,-1)

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= [m(m(A,B,-1), m(B,C,-1), +1)] + m(C,A,-1) = [m(m(A,B,-1), m(B,C,-1),+1), m(A,C,-1),+1] (3) = m[a,b,c] (4) _ _ _ _ _ _ SUM = A.B.Cin + A.B.Cin + A.B.Cin + A.B.Cin _ _ _ _ _ = (A.B + A.B) Cin + (A.B + A.B) Cin (5) _ _ _ _ _ _ _ _ _ _ _ = [ A.B + A.B + A.Cin + A.Cin + B.Cin + B Cin] Cin + (A.B + A.B) Cin _ _ _ _ _ _ _ _ _ _ _ = [( A.B + A.Cin + B.Cin) + (A.B + A Cin + B Cin)] Cin + (A.B + A.B)Cin _ _ _ _ _ _ _ _ = [( A.B + A.Cin + B.Cin) + (A.B + A Cin + B Cin)] Cin + _ _ _ _ _ _ (A.Cin + B.Cin) +(A.Cin + B.Cin) _ _ _ _ _ _ _ _ = [( A.B + A.Cin + B.Cin) Cin + (A.B + A Cin + B Cin) Cin] + _ _ _ _ _ _ _ _ (AB + A.Cin + B.Cin) (A.Cin + B.Cin + AB) (6) _ _ _ _ _ _ _ _ =m(A,B,C) .Cin + m(A,B,Cin). Cin + m(A,B,Cin) m(A,B,Cin) (7) _ _ _ _ =m[m(A,B,Cin), Cin, m(A,B,Cin)] (8) _ _ =m[Cout, Cin, m(A,B,Cin)] (9) Equation 3 and 4 shows the majority logic proof of carry in full adder. Equation 7,8 and 9 shows majority logic representation of sum in full adder. Equation 3 gives AND logic representation of three product terms in carry expression. For sum expression, the equation (1) is expressed in convenient way in terms of majority logic method, these expressions are simplified using Boolean laws. Equation for computing SUM has inputs like carry in, a, b and carry out as shown in equation (9) and the majority is written according to table 1. Figure 6 shows QCA Full adder and figure 9 shows the simulated waveforms of QCA full adder. QCA full adder has four clocking zones at clock 0 outputs sum and carry are evaluated. Initially clock 0 is used to get the inputs a,b,cin, clock 1 is used to route inputs for majority gate logic, clock 2 is used for finding majority logic and clock 3 is used to compute sum and carry output. The output sum and carry is available at clock 0 again. Clock 1 to 3 considered here as sequence of setup, hold, relax and release phase to control the flow of information in QCA circuits. Figure 8 shows three majority gates with an inverter which is used to compute sum output. If we note down the equation (9), three majority gates (one for Cout, one for A,B and Cin’ and overall one) are required to compute sum. We compared the simulated waveform with the equations 4 and 9, QCA full adder works as binary full adder circuit.

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Figure 8 : QCA full adder

Figure 9 : Simulated waveform of QCA Full adder

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Full subtractor QCA Subtractor algorithm: We propose QCA subtractor algorithm as same as of QCA addition algorithm with minor changes in equation (5). Equation 13 and 14 shows Majority logic simplified equation for computing difference output. Equation 15 and 16 used to calculate output borrow. Equation 14 has a’,b,Cin forms a majority expression, a,b’ and cin forms the second majority expression, overall with Cin’ third majority expression can be formed to find difference. _ _ _ _ _ _ Diff = (A.B + A.B ) Cin + (A.B + A.B) Cin _ _ _ _ _ = [ A.B + A.Cin + A.Cin + A.B + B.Cin + BCin ] Cin _ _ + (A.B + A.B) Cin (10) _ _ _ _ _ = [ A.B + A.Cin + A.Cin + A.B + B.Cin + BCin ] Cin _ _ + [ A.Cin + B.Cin] [ A.Cin + B.Cin] (11) _ _ _ _ _ _ =[ A.B + B.Cin + A.Cin] Cin + [A.Cin + A.B + B.Cin] Cin _ _ _ _ + [ A.Cin + B.Cin + A.B ] [ A.Cin + B.Cin +A.B] (12) _ _ _ _ _ _ = m(A,B,Cin) Cin + m(A,B,Cin) Cin + m(A,B,Cin) m(A,B,Cin) (13) _ _ _ = m[ m(A,B,Cin), Cin , m(A,B,Cin)] (14) Borow = a.b + b.c +a.c (15) Borrow = m(m(a,b,-1), m(b,c,-1),m(a,c,-1)) (16) Figure 10 and 11 shows the QCA Full subtractor and simulated waveform of full subtractor. QCA full subtractor has three majority gates only with no inverter as in full adder circuit. The proposed design has less area than full adder circuit. The main advantage of QCA technology is the available of input and inversion in a single QCA wire which we have used in figure 10. Hence the speed of computation is much faster than full adder circuit. Figure 11 shows the simulated waveform of full subtractor circuit. We validate the waveforms with the equation 14 for difference and equation 16 for borrow which gives similar results. We used chain of clocking zones to compute difference and borrow as shown in figure 10. Initially inputs are available at clock0, clock 1,2,3 is to route the inputs for computing majority logic, again clock0 is used to compute majority logic to find borrow and one of the majority gate for difference. Again at third cycle difference is computed at clock 0. The only disadvantage of this approach is no of clock cycles required to route. Simulated waveforms in figure 11 shows 1 bit QCA full subtractor circuit.

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Figure 10 : QCA Full subtractor

Figure 11 : Simulated waveform of QCA Full substractor

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Study II - QCA 4:1 Multiplexer 4:1 Mux

Figure 12 : QCA Multiplexer Logic diagram

Figure 13 : 4:1 QCA Multiplexer

We proposed QCA Multiplexer and De-multiplexer algorithms using Majority voting scheme. Let A and B are the input to Multiplexer, Sx be the control signal and Y be the output. Equation 18 and 21 multiplexer representation in terms of majority voting scheme. Equation 17 has two product terms added together, so minimum two AND majority expressions (19 and 20) are required to form output y as in equation 18. 4:1 Multiplexer can be constructed using two 2:1 Multiplexer.

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Y = A.Sx + B.Sx (17) Y = m(X1,X2,1) (18) _ X1 =m(A,Sx,-1) (19) X2 = m(B,Sx,-1) (20) _ Y = m[ m(A,Sx,-1) , m(B,Sx,-1),1] (21)

Figure 13 : Simulated waveform of 1:4 QCAMultiplexer (Output y = input b) Let A,B,C,D input, Sx, Sy be control singals and y be output of 4:1 Multiplexer Y1 = m[ m((A,S’x ,-1),m(B,Sx,-1),+1)] (22) Y2 = m[m((C,S’y,-1),m(D,Sy,-1),+1)] (23) X1 = m(Y1,S1’S2’,-1) (24) X2 = m(Y2,S1S2,-1) (25) Y = m(X1, X2, +1) (26) Equation 22 and 23 represents 2:1 Mux, X1 and X2 shows selection signal s1 and s2 to select any of the 2:1 Mux, Y be the output of 4:1 Multiplexer. Figure 13 shows the simulated waveform of 4:1 Multiplexer. Simulation is performed to select the input signal b so output y is same as that of b. for selecting input b, Sx signal to be

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active 1 and y1 is always high that leads to X1 high and Y is same as that of b. Clock 0 is used to get output, clock 2 and 3 is used to evaluate majority logic as shown in figure 13. We validate the expression with the simulated waveforms which shows the same results as that of given equations. 1:4 QCA Demultiplexer Let A,B be the select signal and D be the input signal and Y1,Y2,Y3 and Y4 be the output of QCA De-multiplexer circuit. Equation 27 to 30 shows the output of De-multiplexer circuit by majority voting scheme. _ _ _ _ Y1 = D.A B = m[ m(A,B,-1), D,-1] (27) _ _ Y2 = D.A.B = m[ m(A,B,-1), D,-1] (28) _ _ Y3 = D.A.B = m[ m(A,B,-1), D,-1] (29) Y4 = D.A.B = m[ m(A,B,-1), D,-1] (30)

Figure 14 : QCA demultiplexer circuit

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Figure 15 : Shows the simulated waveform of de-multiplexer. Figure 14 shows the QCA demultiplexer circuit and 15 shows the simulated waveforms. We verify that the equation defined obeys according to the simulation as in figure15. Here the output available at clock0, clock1,2 and 3 is used to route the input to compute majority gate, Clock 0 to compute Majority gate, again clock 1 ,2 and 3 to guide the output to Y, thus the output is available at clock 0 in the third cycle.

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Study III QCA Decoder / Enocder

Figure 16 : QCA decoder

Figure 17 : Simulated waveform of QCA decoder Y1 = m(a’,b’,-1) (31) Y2 = m(a’,b,-1) (32) Y3 = m(a’,b’,-1) (33) Y4 = m(a,b,-1) (34) QCA decoder algorithm shows equation 31 to 34. These equations are simple AND gate majority logic. Let a and b be the input, Y1,Y2,Y3 and Y4 be the output of

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decoder, output are expressed in terms of simple majority logic scheme. Figure 16 and 17 shows the QCA decoder and simulated waveform of QCA decoder. Simulated waveform shows directly and gate logic and can be verified using equations 31 to 34. Study IV D / T Flip Flops

Figure 18 : QCA D flip flop

Figure 19 : Simulated waveform of QCA D Flip flop

Figure 21 : QCA T-Flip flop

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Figure 22 : Simulated waveform T- Flip flop Figure 18 and 21 shows the QCA D/ T Flip flops, we propose sequential QCA circuits using majority voting scheme. QCA algorithms for D and T Flip flops are given in equation 35 to 40. Y1 = m(D’,Clock,-1) (35) Y2 = m(D,Clock,+1) (36) qD= m(Y1,Y2,q’) (37) X1 = m(T’,Clock,+1) (38) X2 = m(T,Clock,-1) (39) qT = m(X1, X2,q’) (40) QCA algorithms are verified using simulated waveforms in figure 20 and 22. Both Q and T flip flop behaves according to equations described above. For both the D and T QCA flip flop, inputs are available at clock 0, clock 1 is used to route the inputs to majority gate, clock 2 is used to compute the majority gate, clock 3 is used to find output q. Conclusion We conclude QCA technology one of the promising nanotechnology in future can be used to build quantum computers. QCA combinational and sequential algorithm can be used to construct arithmetic logic units and microproessors etc. We have developed

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in this paper some of the basic QCA algorithms which has not discussed before. We have simulated full adder, subtractor, multiplexer, decoder and flip flops with the equation by majority voting scheme. This simulation and algorithm used to build complex QCA circuits. Reference [1] K.Walus, Wei Wang and Julliaen et al, December 2004. “Majority logic

reduction for Quantum Cellular Automata” in Proc IEEE Nanotechnology conf, vol 3.

[2] K.Walus, Wei Wang and Julliaen et al, December 2004 “Quantum Cellular Automata adders” in Proc IEEE Nanotechnology conf, vol 3 page 461-463.

[3] K.Walus, Schulaf and Julliaen et al, 2004 “High level Exploration of Quantum Dot Automata” in Proc IEEE Nanotechnology conf, vol 2, page 30- 3.

[4] K.Walus, Schulaf and Julliaen et al, 2004 “Circuit design based on majority gates for application with Quantum dot cellular automata” in Proc IEEE Nanotechnology conf, vol 4, page 1350- 135..

[5] K.Walus, Dimitrov and Julliaen et al, 2003 “Computer Architecture structure for Quantum Cellular Automata”in Proc IEEE Nanotechnology conf, vol 3, page 1435 – 1439.

[6] K.Walus, Dysart and Julliaen et al, June 2004 “QCQ Designer A Rapid design and simulation tool for quantuim dot cellular automata” in IEEE transactions on Nanotechnology conf, vol 3, No – 2.

[7] K.Walus, Dysart and Julliaen et al, March 2004 “Split current Quantum dot cellular automata modeling and simulation” in IEEE transactions on Nanotechnology conf, vol 3 .

[8] A. Vetteth et al., 2002 “Quantum dot cellular automata carry-look-ahead adder and barrel shifter,” in Proc. IEEE Emerging Telecommunications Tech-nologies Conf.

[9] A. Vetteth, K. Walus, G. A. Jullien, and V. S. Dimitrov. February 2003 “ Ram design using quantum-dot cellular automata”. NanoTechnology Conference and Trade Show. vol. 2, pp. 160–163.

[10] C. S. Lent and P. D. Tougaw, 1997 “A device architecture for computing with quantum dots,” Proc. IEEE, vol. 85, no. 4, pp. 541–557.

[11] W. Porod etal, 1997 “Quantum-dot devices and quantum-dot cellular automata,” Int. J. Bifurcation Chaos, vol. 7, no. 10, pp. 2199–2218.

[12] I. Amlani et al.,2000 “Experimental demonstration of a leadless quantum-dot cellular automata cell,” Appl. Phys. Lett., vol. 77, no. 5, pp. 738–740.

[13] A. Orlov et al.,2000 “Experimental demonstration of clocked single-electron switching in quantum-dot cellular automata,” Appl. Phys. Lett., vol. 77, no. 2, pp. 295–297.

[14] I. Amlani et al.,1999 “Digital logic using quantum-dot cellular automata,” Science, vol. 284, pp. 289–291.

[15] A. Orlov et al.,1999 “Experimental demonstration of a binary wire for

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quantum-dot cellular automata,” Appl. Phys. Lett., vol. 74, no. 19, pp. 2875–2877.

[16] K. Walus. (2002) ATIPS Laboratory QCADesigner Homepage. ATIPS Laboratory, Univ. Calgary, Calgary, Canada. [Online]. Available: http://www.atips.ca/projects/qcadesigner

[17] G. Toth, 2000 “Correlation and Coherence in Quantum-Dot Cellular Au-tomata,” Ph.D. dissertation, Univ. Notre Dame, Notre Dame..

[18] G. Toth and C. S. Lent, 1999 “Quasiadiabatic switching for metal-island quantum-dot cellular automata,” J. Appl. Phys., vol. 85, no. 5, pp. 2977–2984.

[19] K. Hennessy and C. S. Lent, 2000 “Clocking of molecular quantum-dot cellular automata,” J. Vac. Sci. Technol. B., vol. 19, no. 5, pp. 1752–1755.