ENG3640 Microcomputer Interfacing

Week #10 Busses & Transmission

Lines

ENG3640 Fall 2012 2

Topics Types of Busses

Synchronous Busses Asynchronous Busses Semi-Synchronous Busses Bus Arbitration

Signals along Busses Transmission Lines Reflections & Distortions How to solve the problem? Bus Terminations

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Resources Huang, Chapter 14, Sections

14.7 Waveforms of Bus Signals Microcomputer Interfacing, By Harold

Stone, 1982 (Chapter II) “High Speed Digital System Design”: A

Handbook of Interconnect Theory and Design Practices, By S. Hall, G. Hall and J. McCall, John Wiley & Sons, INC. 2000 (Chapters I, II)

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68HC812A4 Block

Diagram

CPU12

1-KB SRAM

4-KB EEPROM

I/O Ports

I/O Ports

Port TTimer Module

Port ADAnalog to Digital

Port SSerial

Communication

Busses act as the computer skeleton holding all its other organs (functional modules) together

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Definition from “Microcomputer Busses”, by R.M. Cram, (Academic Press, 1991).

A bus is a tool designed to interconnect the functional blocks of a microcomputer in a systematic manner. It provides for standardization in mechanical form, electrical specifications, and communication protocols between board-level devices. Can extend definition to include the P as well

Processor-specific bus : a bus that is intended for use with only one processor or with members of one family of compatible processors.

Ex: MC68HC12 Bus

Standardized processor-independent bus : a bus that is intended to promote interchangeability among a class of board-level products based on possibly different processors.

Ex: PCI Bus

Definitions

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CPU Bus I/O CPU needs to talk with I/O

devices such as keyboard, mouse, video, network, disk drive, LEDs

Memory mapped I/O Devices are mapped to

specific memory locations just like RAM

Uses load/store instructions just like accesses to memory

Ported I/O (Isolated I/O) Special bus line and

instructions

Address

CPU

Memory I/O Device

Data

Read

Write

CPU

MemoryI/O Device

Data

Read

Write

Address

I/O Port

Memory I/O

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ALU & Control

CPU & Memory

Slow Speed High Speed

Several types of Busses ….

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A Functional Classification of Busses1) Processor-Memory Busses

--- short, synchronous, high-speed --- processor-specific; often proprietary

e.g. RAMBUS, VESA local bus

2) Input/Output (I/O) Busses and Instrument Busses--- asynchronous or semi-synchronous--- must accommodate a variety of data rates--- open standards are used to maximize market

e.g. SCSI, GPIB(IEEE- 488), USB, Firewire

3) Backplane Busses--- often midway in performance between processor-memory busses and I/O/Instrument busses--- standard busses are used to reduce design cost and to reduce the time-to-market

e.g. VME, NuBus, PCI

Note: The distinctions between these three bus types are oftenblurred.

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System Interfaces and Modularity

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Bus Properties

Serialization: Only one component

can send a message at any given time.

There is a total order of messages.

Broadcast: A Module can send a

message to several other components without an extra cost

Some Bus TerminologyBus protocol : a set of allowed bus signal transition sequences and required

timing constraints.

Bus operation / transaction : a data transfer or control transfer operation that takes place using bus signals according to a bus protocol.

Bus master : a subsystem connected to the bus that can determine the bus operations. More than one bus master can be present on the same bus, but only one bus master can have control (i.e. be active) at a time.

e.g. multiple CPU’s, DMAC, Math Co-processor, DMA

e.g. RAM, Peripheral Chips

May not be a separate chip, but included in the CPU

Bus slave : a subsystem connected to the bus that responds to bus operations initiated by the currently active bus master

Bus arbitration : the process of determining which one of two or more contending bus masters will be awarded control of the bus (and thereby become the active bus master).

Arbiter : a circuit that performs arbitration

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Components of a Bus

Mechanical

Electrical

Protocol

Mechanical Layer determines its cost but

has very little direct influence on its

electrical performance

Electrical characteristics determines bus

drivers/receivers, signal strength

Protocol determines how the bus is driven and how receiver and transmitter

send/receive their data

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- To drive the bus, a bus driver is needed. To receive data a bus receiver is needed.

- A bus driver and receiver have an enable signal to control its connection to the bus.

- The bus driver and bus receiver are often combined to form a bus transceiver.

DeviceX1

DeviceX2

DeviceX3

X1 drive enable

X1 receive enable

X2 drive enable

X3 drive enable

X2 receive enable

X3 receive enable

X4 drive enable

X4 receive enable

X5 drive enable

X5 receive enable

DeviceX4

DeviceX5

Figure 13.23 Multiple devices attached to the bus line

Bus line

Bus Drivers & Receivers

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Signal Groups within a Typical Bus

1. Data signals

-- encode the data that is passed between the bus master and bus slaves

-- number of data signals determines the “bit width” of the system

-- parity bits or other error detection and correction bits maybe included with each data word

2. Address signals

-- used to identify locations in memory, and registers in peripheral chips

68HC812A4 ? 21 wires, A0 - A20

-- number of address signals determines the maximum size of the memory

Note: Some or all of the data and address signals may be time-multiplexed on the same bus lines

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Signal Groups (con’t)3. Control signals

--- used to co-ordinate bus transactions

R/W, strobes, enables

--- used to arbitrate among:

-- multiple possible bus masters

Bus conflict may lead to errors and damage of peripherals if two

or more modules attempt to use the bus simultaneously.

--- power failure handling

--- entry into and exit from test modes

4. Power signals

--- typically +5 VDC, +12 VDC, -12 VDC, +3.3 VDC

--- optionally -5 VDC

Caution: terminology may vary slightly between vendors.

Double check by checking data sheets

Set-up time , tsu: the minimum length of time that a signal must be valid at a circuit input before a second triggering signal arrives at a second input.

Timing Terminology

Delay time , tco: the length of time that a circuit requires for its output(s) to begin to change in response to a triggering signal arriving at a second input.

Hold time , tho: the minimum length of time that a signal must be kept valid at a circuit input after a triggering signal has been received at a second input.

Timing skew , tskew: the maximum range of times over which a particular signal transition can occur.

-- Due to variations in driver output resistance

-- Combinational logic takes a while to stabilize

Usually a clock

Timing Diagram Notation

L

H

L

H

L

H

L

H

L

H

Changing values Stable Value, high or low Changing values

Clean transitions

Stable, driven High impedance

Tristated

tsu tho

tskew

t

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Bus Protocols

Protocol refers to the set of rules agreed upon by both the bus master and bus slave Synchronous bus transfers occur in relation to successive edges

of a clock Asynchronous bus transfers bear no particular timing relationship Semi synchronous bus Operations/control initiate asynchronously,

but data transfer occurs synchronously

CPU Device 1 Device 2 Device 3

Bus

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Synchronous Bus Protocol

Are among the easiest to implementeasiest to implement. Why? Because the only control signal is a clock oscillator

The rising and falling edges of the clock signify, respectively the beginning and end of the bus cycle.

Not only are synchronous protocols the least complex but also lead to fastest transactionslead to fastest transactions. Provided What?

Provided that the responding devices are fast enough to operate at the bus clock speed.

Examples: ISA Bus (Industry Standard Architecture)

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Synchronous Bus Protocol Transfer occurs in relation to successive edges of the system clock Example:

Memory address is placed on the address bus within a certain time, relative to the rising edge of the clock

By the trailing edge of this same clock pulse, the address information has had time to stabilize, so the READ line is asserted

Once the chip has been selected, then the memory can place the contents of the specified location on the data bus

Clock

Address

Master (CPU) RD

Master (CPU) CS

Data

stable stable

stable stableunstable unstable

Instruction Addr Data Addr

I-fetch data

access time

decoding delay

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Asynchronous Bus Protocol

Handshaking signals are used to transfer information from source to destination (fully interlocked).

The protocol is inherently slower than synchronous protocol because of extra propagation delay.

The wide acceptance of the fully interlocked asynchronous protocol is largely due to:

1. Reliability

2. General efficiency in dealing with devices that have a broad range of response time.

When is it useful? Useful for systems where CPU and I/O devices run at different

speeds

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Asynchronous Bus Protocol

No system clock used Example:

1. Master puts address and data on the bus and then raises the Master signal

2. Slave sees master signal, reads the data and then raises the Slave signal

3. Master sees Slave signal and lowers Master signal

4. Slave sees Master signal lowered and lowers Slave signal

write read

Address

Master

Slave

Data

there's somedata

I’vegot it

I see yougot it

I see yousee I got it

We call this exchange “handshaking”

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Semi Synchronous Bus Protocol Combines the advantage of synchronous and

asynchronous busses: It has the speed of the synchronous bus It has the versatility of an asynchronous bus

It basically uses two control signals1. Clock from the Master

2. Wait signal from the Slave

For fast devices the bus is essentially a synchronous bus controlled by the clock alone

If a device cannot respond in one clock cycle it raises a wait signal and accordingly the master halts

Example: SCSI Bus

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Semi Synchronous Bus Protocol If device cannot respond in one clock cycle it raises the

WAIT signal & master halts When the slave can respond it drops WAIT & master

accepts the slave response using the timing of the standard synchronous protocol.

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Synchronous vs. Asynchronous Buses

Compare max. bandwidth for a synchronous bus and an asynchronous bus

Synchronous bus

1. has clock cycle time of 50 ns

2. each transmission takes 1 clock cycle Asynchronous bus (see timing diagram)

1. requires 40 ns per handshake Find bandwidth for each bus when performing 4-byte

reads from a 200ns memory

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Comparison: Synchronous Bus

1. Send address to memory: 50 ns

2. Read memory: 200 ns

3. Send data to device: 50ns

4. Total: 300 ns Max. bandwidth:

4 bytes/300ns = 13.3 MB/second

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Asynchronous Handshake Protocol

ReadReq: Indicates a read request by CPU from memory DataRdy: Indicates that data word is now ready on data lines Ack: Used to acknowledge the ReadReq or DataRdy signal

of the other party

DataRdy

Ack

Data

ReadReq 13

4

57

642 2

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Asynchronous Handshake Protocol

1. Memory sees ReadReq, reads address from data bus, raises Ack

2. I/O device sees Ack high, releases ReadReq and data lines

3. Memory sees ReadReq low, drops Ack to acknowledge ReadReq

4. When memory has data ready, it places data on the data lines and raises DataRdy

5. I/O devices sees DataRdy, reads data from the bus, signals that it has the data by raising Ack

6. Memory sees the Ack signal, drops DataRdy, releases datalines

7. If DataRdy goes low, the I/O device drops Ack to indicate that transmission is over

DataRdy

Ack

Data

ReadReq 13

4

57

642 2

ENG3640 Fall 2012 29

Comparison: Asynchronous Bus

Apparently much slower because each step of the protocol takes 40 ns and memory access 200 ns

Notice that several steps are overlapped with memory access time

Memory receives address at step 1 steps 2,3,4 can overlap with memory access

Step 1: 40 ns Step 2,3,4: 3 x 40ns =120ns Steps 5,6,7: max(3 x 40ns = 120ns, 200ns) Total time: 40ns+120ns+200ns 360ns max. bandwidth 4bytes/360ns=11.1MB/second

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Bus Arbitration

Refers to how the busses are controlled. Single CPU, Memory, I/O Multiple CPUs, or One CPU

and DMA Bus Arbitration when more

than one master wants to control the bus simultaneously

Simple technique: Every device connects to the bus request line and the first one there gets it

CPU Device 1 Device 2 Device 3

Bus

Bus request line

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Bus Arbitration

What happens if multiple devices want access to the bus?

Scheme A: Device Bus Request Signal, CPU Bus Grant, Device Bus Grant Ack Problem Simultaneous

Request? Scheme B:

daisy chain the devices devices further down the daisy chain pass the request to the CPU device's priority decreases further down the daisy chain

CPU Device 1 Device 2 Device 3

Bus

Bus request line

CPU

Device 3

Bus

Device 1 Device 2RequestGrant

Bus Grant

Bus grant ack

Sharing a Bus Among Multiple Masters

1. Exclusive Control

each bus master retains exclusive control of the bus for several bus transactions.

2. Cycle Stealing

bus transactions from different bus masters are interleaved on an ad hoc or strictly round-robin basis.

e.g. CPU, DMAC1, DMAC2,CPU

3. Split Transaction (Pipelined Bus)

read transactions are split into two transactions:

1) master sends read command & target address

2) slave sends a return packet containing data

the bus is available to be used by other masters during the memory access time e.g. RAMBUS, Synchronous DRAMs

Coarsest granularity

Finest granularity

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Split Cycle Protocol A read is split into two separate transactions:

1. During the first transaction bus master transmits an address to the slave and then disconnects from the bus

2. Other masters use the bus …

3. Slave initiates the 2nd part of the split cycle by accessing the bus as a master and transmitting data to other party which now responds as a slave.

Address

MASTER

SLAVE

Data

Mater transmits

Address to slave

Bus Idle Slave transmits Data to Master

PROS CONS

ExclusiveControl

-- simplicity-- software method-- no special

hardware

-- coarse granularity

CycleStealing

-- fairer sharing of the bus

-- requires hard- ware support

SplitTransactions

-- high-speed buses do not have to wait for slowly responding devices

-- requires hard- ware support on bus and in affected devices

-- bus time may not be shared fairly or efficiently

-- however this support is available in most CPU’s

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Option High Performance Low Cost

1) Bus Sharing

2) Data Width

3) Transfer Size

4) Bus Masters

5) Split Transactions?

6) Clocking

Separate Data & MultiplexedAddress Busses Data & Address

Wider is Faster Narrower is < $ e.g. 32, 64 e.g. 16, 8

Block Transfers Single word using using DMA CPU

Multiple masters One master,(requires arbitration) the CPU, no arbit.

Yes, to get more pipelining No, too complex

Synch. With Asynchronous,matched elements semi-synch.

Summary: Bus Trade-Offs

Busses as Transmission Lines

37

Introduction:

Designers of electronic circuits, normally make the simplifying assumption that signal propagation over conductors is instantaneous is instantaneous and that the received received signal is a faithful replica signal is a faithful replica of the transmitted signal

Is this a valid assumption?Is this a valid assumption?

We need to understand how signals propagate on We need to understand how signals propagate on wires and learn the type of wires and learn the type of distortions that might distortions that might occur occur as: as:

Frequency of operation increasesFrequency of operation increases Wire length increasesWire length increases

37ENG3640 Fall 2012

Transmission Line Concept

PowerPlant

ConsumerHome

Power Frequency (f) is @ 60 Hz

Wavelength () is 5 106 m

( Over 3,100 Miles)

38ENG3640 Fall 2012

General transmission line: a closed system in which power is transmitted

from a source to a destination

Propagation velocity is the speed with which signals are transmitted through the transmission line in its

surrounding medium.

PC Transmission Lines

Integrated Circuit

Microstrip

Stripline

Via

Cross section view taken herePCB substrate

T

W

Cross Section of Above PCB

T

Signal (microstrip)

Ground/PowerSignal (stripline)Signal (stripline) Ground/Power

Signal (microstrip)

Copper Trace

Copper Plane

FR4 Dielectric

W

Signal Frequency (f) is approaching 10 GHz

Wavelength () is 1.5 cm ( 0.6 inches)

Micro-

Strip

Stripline

39ENG3640 Fall 2012

Transmission Line “Definition”A two conductor wire system with the wires in close

proximity, providing relative impedance, velocity and closed current return path to the source.

Characteristic impedance is the ratio of the voltage and current waves at any one position on the transmission line

Propagation velocity is the speed with which signals are transmitted through the transmission line in its surrounding medium.

I

VZ 0

r

cv

40ENG3640 Fall 2012

Speed of Light

Permitivity

41

Wire Delay Signal Transmission:

Signal wave-front moves close to the speed of light (~1ft/ns)

Time from source to destination is called the “transit time”.

In ICs most wires are short, and the transit times are relatively short compared to the clock period.

But, long wires on PCB Busses Global Control signals Clock

t

x

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Reflections and Distortion on Busses

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Reflections: Example

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44

Considering Transmission Line Effects

Question: When are transmission line effects important? Answer: When the wavelength is comparable to the size

of the circuit.

44ENG3640 Fall 2012

45

Introduction: (Facts)

In high-speed circuits, transmission line effects tend to distort signals on paths that are long compared to the wavelength of the signals propagating on the paths.

1. At 100 MHz, wires only a few centimeters long show nonnegligible transmission line effects.

2. For 50 to 60 Hz, the effects are unnoticeable in ordinary wiring, but become visible on power transmission lines that run a few hundred kilometers.

45ENG3640 Fall 2012

Examples of Transmission Line Structures- I Cables and wires

(a) Coax cable(b) Wire over ground(c) Tri-lead wire (d) Twisted pair (two-wire line)

Long distance interconnects

(a) (b)

(c) (d)

+

-

+

+ +-

- -

-

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Speed of Signals along Busses

Transfer time for a high speed signal in a wire is controlled by the movement of electrons

Movement of Electrons? Slows due to impedance of the wire.

Wires have: Resistance Capacitance Inductance

To reason about wires we create models Ideal Lumped R, C Lumped L, R, or C …..

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48

Resistance of wires

Most real wires have resistance Depends on

Material Length Cross Section

What does it cause? Delay Loss (power consumption)

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Capacitance of wires

Real wires have Resistance Capacitance

Causes? Delay. Loss. Attenuation.

i = C dv/dt

Electric Field

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Inductance of Wires

Real wires have Resistance Capacitance Inductance

V = L di/dt

Impact of inductance on supply voltages: Change in current induces a change in voltage Longer supply lines have larger L

Magnetic Field

ENG3640 Fall 2012

Presence of Electric and Magnetic Fields

Both Electric and Magnetic fields are present in the transmission lines These fields are perpendicular to each other and to the direction of wave

propagation. Electric field is established by a potential difference between

two conductors. Implies equivalent circuit model must contain capacitor.

Magnetic field induced by current flowing on the line Implies equivalent circuit model must contain inductor.

V

I

I

E

+

-

+

-

+

-

+

-

V + DV

I + DI

I + DI

V

IH

IH

V + DV

I + DI

I + DI

ENG3640 Fall 2012

ENG3640 Fall 2012 52

Transmission Line Models One way of dealing with transmission lines is to

model it in terms of R and C Impedance of line 1/(1+jwRC)

This is also a low pass filter circuit What is affected?

cutoff frequency fc = 1/(2 pi RC), rise time tr = 2.2 RC

t0 t1

VA

ENG3640 Fall 2012 53

Wire Delay: RC Model More realistic view:

Wires posses distributed network of resistance and capacitance

Time constant associated with distributed RC is proportional to the square of the wire length

For short wires on ICs, resistance is insignificant (relative to effective R of transistors), but C is important.

Typically around half of C of gate load is in the wires.

For long wires on ICs: busses, clock lines, global control signal, etc.

signals are typically “rebuffered” to reduce delay:

v1

v4v3

v2

time

v1 v2 v3 v4

ENG3640 Fall 2012 54

Transmission Line Models However, longer lines cannot be longer lines cannot be simply described

in terms of simple RC models especially when operating at higher frequenciesat higher frequencies

A more complex model can be adopted (RLC) Normally series resistance is small and

conductance is very large so we can simplify the model

Impedance of Capacitor? Inductor? With Low frequency ZC = 1/jwc, ZL = jwL

so, C open, L short, (posing no problem)

55

Transmission Line Models

When can the R and G terms be ignored in the ZWhen can the R and G terms be ignored in the Z00?? As ww increases, the impact of R and G decreases. When the frequency increases above 100 kHz, the terms

multiplied by ww start to dominate.

Impedances of line remains same regardless

of line lengthENG3640 Fall 2012

56

Signals along a conductor

56ENG3640 Fall 2012

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Reflection

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Reflection Coefficient Wires have R, C, L

We therefore have to model wires (busses) as transmission lines that have an impedance Z0

When we send a signal across a wire the signal will usually reflect off the end of the line depending on the termination impedance ZT

Vr Reflected Voltage Vi Incident Voltage Z0 Transmission Line impedance

Reflection CoefficientReflection Coefficient

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Reflection Coefficient @ Src & Dest

The voltage reflection coefficient at the source is

The voltage reflection coefficient at the load is

60

Reflections Coefficient -- Characteristics Three cases

1. ZT = Z0 P = 0 (No Reflection)

2. ZT = 0 (short at the load)P = -1 (Reflection of equal magnitude but opposite polarity)

3. ZT = inf (open load)p = +1 (Reflection of equal magnitude and same polarity)

THE END OF A TRANSMISSION LINE IS SAID TO BE MATCHED IF IT IS TERMINATED WITH ITS CHARACTERISTIC IMPEDANCE (CASE #1)

Ir

Vi

Z0

ZT IT

Ii

T

T

60ENG3640 Fall 2012

Special Cases to Remember

1ZoZo

0ZoZo

ZoZo

100

ZoZo

Vs

ZsZo Zo

A: Terminated in Zo

Vs

ZsZo

B: Short Circuit

Vs

ZsZo

C: Open Circuit

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Solving Transmission Line Problems

We need to establish a procedure that will allow us to solve transmission line problems. Here are the steps:

1. Determination of launch voltage & final “DC” or “t =0” voltage

2. Calculation of load reflection coefficient and voltage delivered to the load

3. Calculation of source reflection coefficient and resultant source voltage

These are the steps for solving all t-line problems.

These are the steps for solving all t-line problems.

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Determining Launch Voltage

Step 1 in calculating transmission line waveforms is to determine the launch voltage in the circuit.

The behavior of transmission lines makes it easy to calculate the launch & final voltages – it is simply a voltage divider!

VsZo

RsVs

0

TD

Rt

A B

t=0, V=Vi

(initial voltage)

RSZ0

Z0VSVi

+=

RSRt

RtVSVf

+=

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Voltage Delivered to the Load

Vs ZoRsVs

0

TD

Rt

A B

t=0, V=Vi

t=TD, V=Vi + B(Vi )t=2TD, V=Vi + B(Vi) + AB)(Vi )

(signal is reflected)

(initial voltage)

Step 2: Determine VB in the circuit at time t = TD

The transient behavior of transmission line delays the arrival of launched voltage until time t = TD. VB at time 0 < t < TD is at quiescent voltage (0 in this case)

Voltage wavefront will be reflected at the end of the t-line VB = Vincident + Vreflected at time t = TD

ZoRtZoRt

Vreflected = (Vincident)

VB = Vincident + Vreflected

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Voltage Reflected Back to the Source

VsZo

RsVs

0

TD

Rt

A B

t=0, V=Vi

t=TD, V=Vi + B (Vi )t=2TD,

V=Vi + B

(Vi) + A

B)(Vi )

(signal is reflected)

(initial voltage)

A B

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Voltage Reflected Back to the Source

Step 3: Determine VA in the circuit at time t = 2TD

The transient behavior of transmission line delays the arrival of voltage reflected from the load until time t = 2TD. VA at time 0 < t < 2TD is at launch voltage

Voltage wavefront will be reflected at the source VA = Vlaunch + Vincident + Vreflected at time t = 2TD

ZoRsZoRs

Vreflected = (Vincident)

VA = Vlaunch + Vincident + Vreflected

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Reflections: Example

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Lattice Diagram Analysis – Key Concepts

Diagram shows the boundaries (x =0 and x=l) and the reflection coefficients

Time (in T) axis shown vertically

Calculate voltage amplitude for each successive reflected wave

Total voltage at any point is the sum of all the waves that have reached that point

Vs

Rs

ZoV(source) V(load)

TD = N ps0

Vs

RtThe lattice diagram is a

tool/technique to simplify the accounting of

reflections and waveformsTime V(source) V(load)

a

source load

bA

cA’

B’

dB

e

0

N ps

2N ps

3N ps

4N ps

5N ps

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Lattice Diagram Analysis – Detail

V(source) V(load)

Vlaunch

source

load

Vlaunch load

Vlaunch

0

Vlaunch(1+load)

Vlaunch(1+load +load source)

Time

0

2N ps

4N ps

Vlaunch loadsource

Vlaunch loadsource

Vlaunch load

source

Vlaunch(1+load+loadsource+

loadsource)

Time

N ps

3N ps

5N psVs

RsZoV(source) V(load)

TD = N ps0Vs

Rt

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Transient Analysis – Over DampedAssume Zs=75 ohms Zo=50ohmsVs=0-2 voltsVs

Zs

ZoV(source) V(load)

Time V(source) V(load)

150

50

2.05075

5075

8.05075

50)2(

ZoZl

ZoZl

ZoZs

ZoZs

ZoZs

ZoVsV

load

source

initial

0.8v

2.0source 1load

0.8v0.8v

0.16v

0v

1.6v

1.92v

0.16v1.76v

0.032v

TD = 250 ps

0

500 ps

1000 ps

1500 ps

2000 ps

2500 ps

0

2 v

Response fr om lattice diagram

0

0.5

1

1.5

2

2.5

0 2 50 500 750 1000 1250

Tim e , ps

Vo

lts

Source

Load

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Transient Analysis – Under Damped

150

50

33333.05025

5025

3333.15025

50)2(

ZoZl

ZoZl

ZoZs

ZoZs

ZoZs

ZoVsV

load

source

initial

Assume Zs=25 ohms Zo =50ohmsVs=0-2 voltsVs

Zs

ZoV(source) V(load)

TD = 250 ps0

2 v

Time V(source) V(load)

1.33v

3333.0source

1load

1.33v1.33v

-0.443v

0v

2.66v

1.77v

-0.443v2.22v

0.148v

0

500 ps

1000 ps

1500 ps

2000 ps

2500 ps 1.920.148v

2.07

Response from lattice diagram

0

0.5

1

1.5

2

2.5

3

0 250 500 750 1000 1250 1500 1750 2000 2250

Time, ps

Vo

lts

Source

Load

71ENG3640 Fall 2012

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What Should Designer do? Practically there are several ways to mitigate the negative

impact of reflections:1. Wait long enough after each signal transition for the reflection on

the line to die out (OK for low speed but not high speed systems)

2. Decrease the frequency of the system so that reflections reach steady state before another signal is driven onto the line (Low Speed Sys!)

3. Shorten the Bus or (PCB trace) so that reflections will reach steady state in a shorter time (not practical or sometimes impossible!)

4. Terminate the transmission line with an impedance equal to the characteristic impedance of the line:

Use a matched termination at far end. Thereby producing no reflections on the line

Use a matched termination at source end absorbing the wave reflected from the far end.

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Matched Termination

Z 0 Z L

Z0

Series Source Termination

Z 0 Z 0

Z S

Parallel Destination Termination

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Terminating the Bus To reduce reflections, the ends of a transmission line

should be terminated by connecting a resistor equal to Z0 across the line

Connecting a resistor between the bus and VCC will pullup the lower logic level and reduce noise immunity

Classic Solution: connect two resistors to the bus one to the ground and one to VCC R1//R2 = Z0

RT

VT

RT = R1//R2 = Z0

Bus

When does a T-line become a T-Line? Whether it is a

bump or a mountain depends on the ratio of its size (tline) to the size of the vehicle (signal wavelength)

When do we need When do we need to use to use

transmission line transmission line analysis analysis

techniques vs. techniques vs. lumped circuit lumped circuit

analysis? analysis?

TlineWavelength/edge rate

Similarly, whether or not a line is to be considered as a transmission line depends on the ratio of length of the line (delay) to the wavelength of the applied frequency or the rise/fall edge of the signal

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Considering Transmission Line Effects Rule of Thumb: Apply TLT

In any system in which rise time of the signal is shorter than twice its propagation time

i.e. if ratio of rise time/prop delay < 0.5

Example #1 Prop delay per meter is 5 ns Rise time is 2ns Signal path length is 4 cm

Answer:2ns /(5ns/m x 4/100) = 10 neglect TLT

Example #2 Prop delay per meter is 20 ns Rise time is 2ns Signal path length is 50 cm

Answer2ns/(20ns/m x 50/100) = 0.25 apply TLT

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Summary Buses are very important components in any digital

system. Three types of busses can be used:

Synchronous Asynchronous Semi-Synchronous

You have to treat interconnections between components as transmission lines if:

High speed > 100 MHz Long connections are used

As engineers you have to make sure that the busses are terminated correctly to match the impedance of the lines, thus no reflection or distortion will be encountered.

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Bus Hardware

Principles to access the bus (using bus transceivers) Bus Transmit: ET Active Bus Receive: ER Active

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- A bus line is simply a conductor.

- The voltage level of a bus line is determined by the device that drives it.

- For this reason, a bus line is often called passive.

- A bus line can be made active by adding a pull-up device.

- A simple pull-up device could be a resistor, a pnp-transistor, or a PMOS transistor.

- In an active bus, the bus voltage will be low only when one or more devices attached to the bus apply a low voltage to the bus.

- When no device drives the bus, the bus voltage will be pulled to high (VDD).

VDD VDD

RP

VDD

(a) (b) (c)

Figure 13.22 Pull-up devices for bus line

PMOS

PNPtransistor

Basics of Bus Signals

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The Dumb Bus: ISA & EISA

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The Dumb Bus: ISA & EISA

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PCI = Peripheral Component Interconnect (McIntosh)

VESA = Video Electronics Standards Association

MCA = MicroChannel Architecture (IBM PS/2)

EISA = Extended Industry Standard Architecture

ISA = Industry Standard Architecture

(ISA is 16 bit (binary digit). The others are 32 and 16 bit)

Bus Types

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So, how does ‘data’ (in all of its various forms and meanings) get around the various devices ?

No problem

It takes a bus

So, what is a bus ?

It is an electronic path in a computer system which transmits bits - the binary digits which represents the atomic values of data

Traveling Around the Computer

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68HC12 Memory Bus for 2x1M ROMS

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There are a number of different varieties of ‘buses’

1. The Internal Bus - its function is to move data around the CPU chip

2. Data Buses - their function is to link the CPU and RAM

3. Local buses - a special bus (or buses) which link peripherals requiring fast response times (display, disk, high speed

local networks) (GUI’s, Multimedia, scanners - all have high bit loads and require fast traffic lanes)

4. Expansion Bus – its function is to extend the data bus and to establish links with peripherals

5. Universal Serial Bus - capability of linking many devices to a single or common port (such as the Zip drive, pluggable hard disk, CD-Rom)

Type of Buses

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Typical PC System Architecture

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Recall ENG241: Flip-Flop Timing

Setup time – time that D must be available before clock edge

Hold time – time that D must be stable after clock edge

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Propagation Delay Propagation delay – time after edge when

output is available

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Clock Skew

Unequal delay in distribution of the clock signal to various parts of a circuit: if not accounted for, can lead to erroneous behavior. Comes about because:

clock wires have delay, circuit is designed with a different number of clock buffers from the

clock source to the various clock loads, or buffers have unequal delay.

All synchronous circuits experience some clock skew: more of an issue for high-performance designs operating with very

little extra time per clock cycle.

clock skew, delay in distribution

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CPU

CacheController

CacheMemory

PCIController

DRAM

EISA/PCI BridgeController

Hard DriveController

VideoAdaptor

PC Card 1 PC Card 2

SCSIAdaptor

PC Card 3

Local CPU / Memory Bus

Peripheral Component Interconnect Bus

EISA PC BusSCSIBus

Co-processor

Hierarchies of Busses To exploit the strengths (and avoid the weaknesses) of different kinds

of busses, high performance systems often use a hierarchy of busses Example: High-Performance Personal Computer

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Arbitration Among Contending Masters

1. Fixed Priority

--- each bus master is assigned a unique priority

--- contending master with highest priority is awarded control of the bus

2. Rotating Priority

--- at any one time, each bus master has a unique priority

--- the priority assignments are periodically rotated so that each bus master takes a turn at having each of the available priorities

A,B,C,D

B,C,D,A

C,D,A,B3. Pseudo-random Selection

--- the winning bus master is selected randomly from among the currently contending masters

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How to settle errorsHow to settle errors

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Summary: Transmission Line Effects

Transmission-line considerations can generally be generally be ignoredignored in the design of logic circuit that have clock

rates from 1 to 10 MHz for paths confined to one PCBconfined to one PCB.

There are however noticeable transmission line noticeable transmission line effectseffects where signals are bused from board to boardboard to board,

and severe effects where signals move from chassis to chassis.

Very high speed equipment that runs with clock rates from 50 MHz to 1GHz and above must normally treat even those signal

lines confined to one circuit board as transmission lines, except possibly for very short lines.

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Reflections Coefficient Consider incident voltage and current: Vi, Ii and reflected voltage,

current ; Vr, Ir

At any point along the line Z0 = Vi/Ii, Ii = Vi/Z0

At termination we have VL =Vi + Vr,

IL = Ii – Ir (negative sign is due to reverse direction of reflected current) Vr = pVi and Ir = pIi

Substituting we have ZL = VL/IL= (Vi+pVi)/(Ii-pIi)

ZL = (Vi + pVi) / ((Vi /Z0) – p(Vi/Z0)) Solve the above for p (ZL – Z0)/(ZL + Z0)

Vi

Z0

ZL IL

Ir

Ii

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View of Busses

Ramp into Source Matched T- line

Ramp function is step function with finite rise time as shown in the graph. The amplitude is 0 before time t0

At time t0 , it rises with straight-line with slope

At time t1 , it reaches final amplitude VA

Thus, the rise time (TR) is equal to t1 - t0 .

The edge rate (or slew rate) is VA /(t1 - t0 )

t0 t1

VA

Z0 ,T0

V1 V2

l

I2I1

VS

RS

T = T0l

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Example of Reflections

T Line Rules of Thumb

Td < .1 Tx

Td < .4 Tx

May treat as lumped Capacitance Use this 10:1 ratio for accurate modeling of transmission lines

May treat as RC on-chip, and treat as LC for PC board interconnect

So, what are the rules of thumb to use?

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Example of Reflections

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E & M Fields – Microstrip Case

The signal is really the wave propagating between the conductors

Electric field

Magnetic field

Ground return path

X

Y

Z (into the page)

Signal path

Electric field

Magnetic field

Ground return path

X

Y

Z (into the page)

Signal path

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Voltage Divider Circuit Consider the simple

circuit that contains source voltage VS, source resistance RS, and resistive load RL.

The output voltage, VL is easily calculated from the source amplitude and the values of the two series resistors.

RS

RLVS VL

RSRL

RLVSVL

+=

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