ENEE 408C LabENEE 408C LabCapstone Project: Digital System Capstone Project: Digital System

DesignDesignSpring 2006Spring 2006

Class Web Site:Class Web Site:http://www.ece.umd.edu/class/enee408chttp://www.ece.umd.edu/class/enee408c

TA’s InformationTA’s Information

Alessandro GeistAlessandro Geist

ageist@umd.eduageist@umd.edu

Office Hours: TBDOffice Hours: TBD

Submission FormatSubmission Format

For Homework, Quiz, or Project For Homework, Quiz, or Project Submission of source code, please name Submission of source code, please name your verilog files:your verilog files:

ageistquiz1df.vageistquiz1df.v // design file// design file

ageistquiz1tb.vageistquiz1tb.v // test bench// test bench

Submission FormatSubmission Format

For Homework, Quiz, or Project Submission of source For Homework, Quiz, or Project Submission of source code, please provide the following header in your verilog code, please provide the following header in your verilog code:code:

/***************************************************************/***************************************************************Author:Author: Alessandro GeistAlessandro GeistDate:Date: 09/02/200509/02/2005Assignment:Assignment: Homework 1Homework 1Module:Module: fourbitadderfourbitadderSubmodules:Submodules: halfAdder, fullAdderhalfAdder, fullAdderDescription:Description: This is a four-bit adder, it takes two four bit numbersThis is a four-bit adder, it takes two four bit numbers

and outputs the sum and carry.and outputs the sum and carry.*****************************************************************/*****************************************************************/

BehavioralBehavioralvs. Structural Descriptionvs. Structural Description

Structural DescriptionStructural Description– a Verilog description of schematica Verilog description of schematic– easy to synthesize easy to synthesize – like gate-level netlistlike gate-level netlist– less readable from human’s point of view.less readable from human’s point of view.

Behavioral DescriptionBehavioral Description– a description of the functionalitya description of the functionality– flexible and more readableflexible and more readable– suitable for large scale designsuitable for large scale design– not always synthesizablenot always synthesizable

Structural DescriptionStructural Description

primitive instantiation (AND, NAND, OR, primitive instantiation (AND, NAND, OR, NOR, XOR, XNOR, BUF, NOT, BUFIF, NOR, XOR, XNOR, BUF, NOT, BUFIF, NOTIF)NOTIF)

parameter value assignment parameter value assignment

Example: Half AdderExample: Half Adder

modulemodule halfAdder (SUM, CARRY, A,B); halfAdder (SUM, CARRY, A,B);

inputinput A, B; A, B;

outputoutput SUM, CARRY; SUM, CARRY;

XOR (SUM, A,B); // exclusive ORXOR (SUM, A,B); // exclusive OR

AND (CARRY, A,B);AND (CARRY, A,B);

endmoduleendmodule

Behavioral DescriptionBehavioral Description

Boolean expression levelBoolean expression level– continuous assignmentcontinuous assignment

Register transfer level (RTL)Register transfer level (RTL)– procedural statementprocedural statement

Algorithm descriptionAlgorithm description– for, whilefor, while loops etc. loops etc. – case, if elsecase, if else statements etc. statements etc.

Example: Half AdderExample: Half Adder

modulemodule halfAdder (SUM, CARRY,A,B); halfAdder (SUM, CARRY,A,B);

inputinput A, B; A, B;

outputoutput SUM, CARRY; SUM, CARRY;

assignassign SUM = A ^ B; // exclusive OR SUM = A ^ B; // exclusive OR

assignassign CARRY = A & B; CARRY = A & B;

endmoduleendmodule

Full AdderFull Adder

Try Full Adder!Try Full Adder!

Full Adder, composed of HA’sFull Adder, composed of HA’s/*************************** FULL ADDER *********************************//*************************** FULL ADDER *********************************/

// fullAdder module definition - contains two instances of module halfAdder needed to // fullAdder module definition - contains two instances of module halfAdder needed to create the fullAddercreate the fullAdder

module fullAdder (SUM, CARRY_OUT, A_in, B_in, CARRY_IN);module fullAdder (SUM, CARRY_OUT, A_in, B_in, CARRY_IN);

input A_in, B_in, CARRY_IN;input A_in, B_in, CARRY_IN;

output SUM, CARRY_OUT;output SUM, CARRY_OUT;

wire w1, w2, w3;wire w1, w2, w3;

halfAdder H1(w1,w2, A_in, B_in); // instance of halfAdder module called H1halfAdder H1(w1,w2, A_in, B_in); // instance of halfAdder module called H1 halfAdder H2(SUM, w3, CARRY_IN, w1); // instance of halfAdder called H2halfAdder H2(SUM, w3, CARRY_IN, w1); // instance of halfAdder called H2

OR OR o1 (CARRY_OUT, w2, w3);o1 (CARRY_OUT, w2, w3);endmoduleendmodule/******************************************************************************//******************************************************************************/

Using a TestbenchUsing a Testbench

Allows you to test the functionality of Allows you to test the functionality of your design by applying test inputs and your design by applying test inputs and observing the outputs.observing the outputs.

When using Modelsim, must be in a When using Modelsim, must be in a separate .v fileseparate .v file

Must match the interface of your designMust match the interface of your design

Need not to be synthesizable.Need not to be synthesizable.

Full Adder Testbench Full Adder Testbench

`timescale 1ns / 1ps`timescale 1ns / 1psmodule tb_fulladder;module tb_fulladder;

wire SUM, CARRY_OUT;wire SUM, CARRY_OUT;reg A_in, B_in, CARRY_IN;reg A_in, B_in, CARRY_IN;fullAdder instance1(SUM, CARRY_OUT, A_in, B_in, CARRY_IN);fullAdder instance1(SUM, CARRY_OUT, A_in, B_in, CARRY_IN);

initialinitialbeginbegin

$monitor ($time,,, $monitor ($time,,, "A = %b B = %b C = %b SUM = %b, Cout = %b", A_in, B_in, CARRY_IN, "A = %b B = %b C = %b SUM = %b, Cout = %b", A_in, B_in, CARRY_IN,

SUM, CARRY_OUT);SUM, CARRY_OUT); //TEST INPUTS //TEST INPUTS

#10 A_in=0; B_in=0; CARRY_IN=0; #10 A_in=0; B_in=0; CARRY_IN=0; #10 A_in = 1; #10 A_in = 1; #10 CARRY_IN = 1; B_in = 1; #10 CARRY_IN = 1; B_in = 1;

end end endmoduleendmodule

VectorsVectors

Vectors can be declared as [highbit:lowbit] Vectors can be declared as [highbit:lowbit] or [lowbit:highbit]or [lowbit:highbit]The The leftmostleftmost number in the square number in the square brackets always corresponds to the brackets always corresponds to the most most significantsignificant bit (as in extensions) bit (as in extensions)When referencing a variable, range When referencing a variable, range indices must be constants, but single indices must be constants, but single indices can be variablesindices can be variables

Vectors in VerilogVectors in Verilog

One dimension: define data with multiple bits.One dimension: define data with multiple bits.E.g.E.g.

reg [15:0]reg [15:0] sum;sum;wire [15:0]wire [15:0] w;w;assign w[3:0] = sum[15:12];assign w[3:0] = sum[15:12];

Two dimension: define a memory storage.Two dimension: define a memory storage.E.g.E.g.

reg [31:0] RegFile[31:0];reg [31:0] RegFile[31:0];always@(posedge clk)always@(posedge clk)

RegFile[0] = 32’b0;RegFile[0] = 32’b0;

Vector ExamplesVector Examples

reg [7:0] bus bus[4:0]

wire [4:2] addends addends[3:2]

wire [2:4] addends addends[2:3]

reg [5:0] value value[var:1]

reg [5:0] value value[n]

The 5 least significant bits of bus

The 2 least significant bits of addends

The 2 most significant bits of addends

Illegal — indices must be constant

The nth bit of value where n is a register or a net

Full Adder, composed of HA’sFull Adder, composed of HA’s/*************************** FULL ADDER *********************************//*************************** FULL ADDER *********************************/

// fullAdder module definition - contains two instances of module halfAdder needed to // fullAdder module definition - contains two instances of module halfAdder needed to create the fullAddercreate the fullAdder

module fullAdder (SUM, CARRY_OUT, A_in, B_in, CARRY_IN);module fullAdder (SUM, CARRY_OUT, A_in, B_in, CARRY_IN);

input A_in, B_in, CARRY_IN;input A_in, B_in, CARRY_IN;

output SUM, CARRY_OUT;output SUM, CARRY_OUT;

wire [2:0] w;wire [2:0] w;

halfAdder H1(w[0],w[1], A_in, B_in); // instance of halfAdder module called H1halfAdder H1(w[0],w[1], A_in, B_in); // instance of halfAdder module called H1 halfAdder H2(SUM, w[2], CARRY_IN, w[0]); // instance of halfAdder called H2halfAdder H2(SUM, w[2], CARRY_IN, w[0]); // instance of halfAdder called H2

OR OR o1 (CARRY_OUT, w[1], w[2]);o1 (CARRY_OUT, w[1], w[2]);endmoduleendmodule/******************************************************************************//******************************************************************************/

Numbers — SizedNumbers — Sized

<size>’<base_format><value><size>’<base_format><value>– <size> is a decimal number and specifies <size> is a decimal number and specifies

the number of bits in the number.the number of bits in the number.– <base_format> is one of <base_format> is one of

[[d/Dd/D] — Decimal] — Decimal[[hh//HH] — Hex] — Hex[[bb//BB] — Binary] — Binary[[oo//OO] — Octal] — Octal

– <value> is a string of characters <value> is a string of characters representing the number.representing the number.

Numbers — Sized : ExamplesNumbers — Sized : Examples

5’5’dd3 = 000113 = 00011

8’8’hh0f = 000011110f = 00001111

7’7’bb0 = 00000000 = 0000000

Numbers — UnsizedNumbers — Unsized

Numbers specified without a Numbers specified without a <base_format> are decimal.<base_format> are decimal.– 4’7 = 01114’7 = 0111

Numbers written without a <size> are Numbers written without a <size> are simulator dependent — typically 32 bits.simulator dependent — typically 32 bits.– ’’hhffff = 32’ffff = 32’hh0000ffff0000ffff

Combinational vs. SequentialCombinational vs. Sequential

CombinationalCombinational– Combinations of logic where the outputs are Combinations of logic where the outputs are onlyonly

dependent on values of the current input signalsdependent on values of the current input signals– Combinational elements can be modeled using assign Combinational elements can be modeled using assign

and always statements. and always statements.

SequentialSequential– Outputs are dependent on values of the past inputs Outputs are dependent on values of the past inputs

as well as current circuit inputs.as well as current circuit inputs.– Sequential elements can be modeled using only Sequential elements can be modeled using only

always statements. always statements.

Boolean Behavior and Continuous Boolean Behavior and Continuous AssignmentAssignment

Define a Boolean equation that describes combinational Define a Boolean equation that describes combinational logic by an expression of operations on variables.logic by an expression of operations on variables.

Left Hand Side must be of type wire, Right Hand Side Left Hand Side must be of type wire, Right Hand Side can be reg or wire.can be reg or wire.

E.g.E.g.wirewire sum; sum;

outputoutput c_out; c_out;

assignassign #1 sum = a ^ b; #1 sum = a ^ b;

assignassign #2 c_out = a & b; #2 c_out = a & b;

Cyclic Behavioral ModelsCyclic Behavioral Models

Model both level-sensitive behavior (combinational) and Model both level-sensitive behavior (combinational) and edge-sensitive behavior (flip-flop) of an element.edge-sensitive behavior (flip-flop) of an element.

always@ (a or b) beginalways@ (a or b) begin

sum = a ^ b;sum = a ^ b;

c_out = a & b;c_out = a & b;

endend

always@ (posedge clk)always@ (posedge clk)

dff_out <= dff_in;dff_out <= dff_in;

Blocking vs. NonblockingBlocking vs. Nonblocking

In always blocksIn always blocksBlockingBlocking– Execute sequentiallyExecute sequentially– Better for combinational logicBetter for combinational logic

NonblockingNonblocking– Execute Concurrently (in parallel)Execute Concurrently (in parallel)– Better for sequential logicBetter for sequential logic– RHS of all statements calculated first from RHS of all statements calculated first from

values before executionvalues before execution

Combinational Examples of Combinational Examples of Blocking vs. NonblockingBlocking vs. Nonblocking

BlockingBlockingReg D, B;Reg D, B;always @ (E or D) beginalways @ (E or D) begin

// D=2, E=5, B=3 initially// D=2, E=5, B=3 initially

D = E;D = E; // D=5// D=5B = D;B = D; // B=5// B=5

endend

NonblockingNonblockingReg D, B;Reg D, B;always @ (E or D) beginalways @ (E or D) begin

// D=2, E=5, B=3 initially// D=2, E=5, B=3 initially

D <= E;D <= E; // D=5// D=5B <= D;B <= D; // B=2// B=2

endend