End of Column Circuits
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End of Column Circuits
Sakari Tiuraniemi - CERN
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EOC Architecture
45
9
Ref CLK40 MHz
DL
L
32-bit
TD
C b
ank
add
ress
RX
5
TD
C b
ank
add
ress
RX
5
TD
C b
ank
add
ress
RX
5
TD
C b
ank
add
ress
RX
59 9 9
PL
L
320 MH
z
40
registers
serial.
registers
serial.
registers
serial.
registers
serial.
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• 9 TDCs, each for a group of 5 non-adjacent pixels
• 32 to 5 bit encoders integrated with hit registers• Instead of reading out all the
32 bits
• Avoid 32x2x9x40 parallel lines in the layout, decrease complexity of the following circuitry
• Encoders not used in the demonstrator
TDC per 5 pixels – EOC
TD
C 1
TD
C 2
TD
C 8
TD
C 9
address
32 to 5 bit
32 to 5 bit
32 to 5 bit
32 to 5 bit
5 5 5 5
123456789
101112...
1920
282936
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Demonstrator Architecture
Pixel 1
Pixel 9
9
9
Pixel 10
Pixel 18
9
Pixel 19
Pixel 27
9
Pixel 28
Pixel 36
9
Receiver 1 Receiver 11
4 ad, receivers
9 receivers
32
-bit
hit
regis
ter
rise
32-b
it h
it re
gis
ter
fall
32-b
it hit
reg
iste
r rise
32-b
it h
it re
gis
ter
fall
2x9 32-bit hit registers
Line output buffer 11Line output buffer 1
4
4 address lines busConnected to each line
buffer
DLL
AD
AD
S-o
ut 1
S_
ou
t 9
Line buffer data word= 32+32+4+6+6=80 bits
Coarse counter
Coarse countConnected to each
line buffer
coars
e
coars
e
320 Mhz
320 Mhz
9 serial outputs
LVDS LVDS
TDR1 TDF1 TDR11 TDF11
Rise fine count Fall fine count R-coarse F-coarse ADD
32 bit 32 bit 6 bit 6 bit 4 bit
Pixel 37
Pixel 45
9
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EOC Demonstrator
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• TDC-bank• Hit Registers: layout
ready
• DLL- and TDC-bank Buffers: layout ready
• DLL• VCDL: layout ready
• CP and PD layout under work
Design Status
• Encoders: not designed
• 32 to 5 encoder
• Address encoder
• Post TDC circuitry: not designed
• PLL: not designed
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Delay Locked Loop
• 32 delay elements• 100ps delay each
• Phase detector• Bang-bang
detector only gives information of the sign of phase error
• Charge Pump• Adjusts the delay
by increasing/ decreasing control voltage by adding/removing charge in C
C
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DLL – Charge Pump
• Capacitance and current of Charge Pump affects
• Accuracy of the delay (jitter)
• Speed of the loop
• Time to achieve lock
• Response time for changes (in the clock phase, etc)
• Need for further simulations to optimize capacitance size against speed
• 1st order system - inherently stable loop
• When higher order poles are at high frequencies
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DLL – Charge Pump
Icp = 1.72 µA
C = 20 pF
Kvcdl = 1.32 ns/V
T = 1/fCLK = 3.2 ns
• Charge pump current is adjustable• Possible to achieve fast
locking time with higher current
• Increase accuracy after lock achieved with lower current
• Tlock = 1.329 µs • Icp = 1.72 µA
• From VRFN = 600 mV (down to ~485.7 mV)
kHzCT
KI vcdlcpn 35
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DLL – Jitter, Transient Analysis
• Jitter at the last delay element output
• Δτ = 13.713 ps
• With
• C = 20 pF
• Icp= 1.72 µA
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DLL – Jitter, Transient Analysis
• Jitter at the last delay element output
• Δτ = 13.713ps
• With • C = 20 pF
• Icp= 1.72 µA
• Delay of the last delay element
• τ = 100.6 ps ± 0.1283 ps
• VRFN = 485.7mV ± 0.18 mV
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DLL – Jitter, Transient Noise Analysis
• Jitter at the last delay element output
• Δτ = 18.11 ps
• With
• C = 20 pF
• Icp= 1.72 µA
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DLL – Jitter, Transient Noise Analysis
• Jitter at the last delay element output
• Δτ = 18.11ps
• With • C = 20 pF
• Icp= 1.72 µA
• Delay of the last delay element
• τ = 100.5 ps ± 0.1554 ps
• VRFN = 493.4mV ± 0.18 mV
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Status of Work - NEXT
1. Finish layout of DLL
2. Post-layout simulations with DLL and TDC
3. Start design work for PLL and post TDC circuits (shift registers and logic)
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One delay cell with buffer
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Delay line
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D flip flop
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18 Hit register bank(TDC’s)