Embedded Package Technologies Austin CTEA May … Package Technologies Austin CTEA May 2017 Mark...
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Embedded Package TechnologiesAustin CTEA May 2017 Mark Gerber
Director, Engineering/Tech Promotion‐Flip Chip/Adv. Interconnect
CT Chiu ‐ aEASIChien‐Fan Chen ‐ SESUB
ASE Global Inc.May 2017
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Contents
1
Interconnect Evolution & ApplicationsEmbedded Packaging Application and OptionsAdvantages of Embedded PackagingSESUB – OverviewaEASI – OverviewSummary
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Package Interconnect Evolution
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Die Embedding Applications & Options
Embedded Packaging
Power/Analog Devices
SiP Module
SolutionsBluetooth/Wifi
Modules
Substrate Based Embedding‐ Driver‐ Size/Performance
Hybrid Substrate/Lead‐frame Embedding ‐ Driver ‐ Power/Thermal/Performance
Fan Out Based Embedding (Chip First/Last)‐ Driver‐ Die Size/Performance
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uPower Module
IPM &SMPS
IGBT HousingModule
Embedded Inductor & Capacitors(<40V, <10A)
(e. g. Step-Down, Buck-Boost, LED Drivers & Battery Chargers)
Multichip as IGBT + Diode + HVIC + LVIC(<600V, <30A)
for AC/DC converter in white goods,Industrial motors Etc.
BGA / LGA Module
High Reliability / High Power Module(600V~1200V / 1200V~3500V, Upto 100Kw)
DC/DC Converter / DC-AC Inverter in automotive, (H)EV, Power Train etc.
IPM : Intelligent Power ModuleSMPS : Switching Mode Power Supply
Housing Module
DIP (Dual In-line PKG) IPM
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Power Packaging Examples
Multichip modules(<220V, <20A)
for AC/DC converter in white goods,Industrial motors Etc.
Mid-Power Modules with Cu-clip & Al wedge bond
ChipChip
Mid-Power Module
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Benefits of Embedded Packaging
Miniaturization & Design Flexibility‐ Embedded chip enables more space for other components or shrinks overall solution‐ Design flexibility now shifts from 2D to 3D
Improved Thermal & Electrical Thermal Performance‐ Shorter interconnections reduce parasitics ‐minimizes distortion and power loss‐ Lower electrical & thermal resistivity in package improves power performance
Improved Reliability and mechanical stability‐ High mechanical system stability due to stable Cu interconnections.
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Electrical Considerations of Embedding
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PIERS Proceedings, Moscow, Russia, August 2009
QFN Package Parasitic ExampleCircuit Parasitic Example
IEEE Power Electronics Magazine, 2015 Dec
Embedded Packaging Reduces Parasitics Through:‐ Shorter Connections (Example ‐ Wire Bond Elimination)‐ Shorter Distance Between Components‐ Passives closer to Chip Pads‐ Fewer Capacitance Areas
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Understanding Ohms Law for Packaging Ohm’s Law ‐ Power Loss = Current Squared x Resistance(Double the Current give you 4x the Power Loss)
Physical Explanation – The voltage difference along a wiredepends on the current – More current flowing withresistance mean more voltage (pressure of electricity ifyou like) is built up.
Practical Explanation – Power measuredin watts is equal to I x R along the path ofcircuit. If you keep resistance small, youminimize power loss as HEAT!!
**Physics Forum 2008
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Overview‐Embedded Package Solutions
SESUB‐ Semiconductor Embedded In Substrate
aEASI –Advanced Embedded Active System Integration
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SESUB – Semiconductor Embedded in Substrate
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What’s SESUB ?SESUB = Semiconductor Embedded in SUBstrate
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Product Portfolio Examples
SESUB (Semiconductor Embedded in SUBstrate)
S‐SESUB (Simplified Semiconductor Embedded in SUBstrate)
4 Metal layers
Total thickness : 300 um typically
Core thickness : 115 um typically
Die thickness : 50um min.
IC ratio (die/substrate) : 15 ~70%
Production: Available
(Max 12x12 mm2 size experienced)
2 Metal layers / Cavity Core
Total thickness : 250um typically
Core thickness : 160 um typically
Die thickness : 100um Typically
IC ratio (die/substrate) : 30% max.
Production: Available
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SESUB Key Features
Die
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Application Space for SESUB – Some Examples
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aEASI – Power Embedding
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What’s a‐EASI ?
Leverages a Mature Organic Substrate Process Flow Modified to Meet High Power Applications Good Current Capability‐ ~60A (Integrated Power Stage Example), ~ 1.9W/mm2 300um thick Copper Heat Spreader/Electrical Pad (Back of Die) Copper Lines ~ 32um Thick for Low Resistivity Deep Full Filled Vias to Die ~ 130um Diam Ultra Low Resistivity Die Attach Interface
aEASI = Advanced Embedded Active System Integration
P1 Example‐Prod Start in 2014Thermal HS/
EMI Shield
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aEASI Product Examples
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aEASI Package Portfolio
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Deep Via (aspect ration ~1.1)Via on Die pad
(50um min in Via bottom)Thin Die (~50um)
Thick Cu (32um)Small via (Diameter = 70um)
A‐EASI Example Cross Section – Integrated Power Stage
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aEASI Package to Die Interconnect Highlights
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aEASI P2
Bottom ViewAg SinteringPassives
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P2 BGA Reliability Summary 4.
0 m
m
4.0 mm
Bottom
Side View
22
Top
Key information : Size : 4.0X 4.0 +/‐ 0.1 mm , TH = 0.35 +/‐ 0.040 mm Ball count : 24 ( pitch: 0.5 mm) Blind Via : 0.085 mm T/S : 60/60 Cavity lead frame
Test Description Abbr Conditon Readout Result
PrecondioningAEC‐Q100 PC*
MSL3MSL Moisture soaking330℃/60%RH
Bake 125°C 24HrsMoisture Soak 168 Hrs3x Reflow (265°C+(0/‐5))
Pass
100hrs Pass 200hrs Pass 500 Cycles Pass 1000 Cycles Pass1500 Cycles Pass1700 cycles Pass2000Cycles Pass500 hrs Pass1000hrs Pass1500hrs Pass2000hrs Pass
HTSTHTSTAEC‐Q100 Grade 0 150℃
"‐65~150℃
HAST AEC‐Q100
HAST 130℃/85%RH 33.3PSIA
TemperatureCyclingAEC‐Q100 Grade 0
TCT
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P2 QFN 5.
0 m
m
5.0 mm
Bottom
Side ViewTop
Key information : Size : 5.0X 5.0 +/‐ 0.1 mm , TH = 0.305 +/‐ 0.040 mm Lead count : 20 Pin (Lead pitch: 0.735/ 0.8mm) Blind Via : 0.06 mm T/S : 40/40 Laser marking on SM Cavity lead frame Passive/Active integrate on top is possible
Test Description Abbr Conditon Readout ResultPrecondioning J‐A113/J‐020 PC*
MSL3 MSL Moisture soaking3 30℃/60%RH
Bake 125°C 24HrsMoisture Soak 168 Hrs3x Reflow (265°C+(0/‐5))
Pass
100hrs Pass 200hrs Pass 500 Cycles Pass 1000 Cycles Pass1500 Cycles Pass1700 cycles Pass2000Cycles Pass500 hrs Pass1000hrs Pass
Temperature Cycling JESD22‐A104
TCT "‐65~150℃
HTST JESD22‐A103‐B
HTST 150℃
HAST J‐ESDD22‐A118
HAST 130℃/85%RH 33.3PSIA
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Electrical Performance Comparison
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Thermal Performance
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Summary Packaging interconnect technology has evolved and for the next level of minaturization
and performance enhancement, embedded packaging will be a key enabler.
Bluetooth/Wifi modules, Power Analog Devices and new SiP Modules are leveraging thistechnology to enable better size, electrical and thermal performance.
Embedding Package solutions such as SESUB and aEASI are available embedding solutionsthat have proven benefits for low and high power analog, digital and RF products.
ASE is the leader in System in Package/System in Module packaging and embedding package technology is a key tool to further enable the next generation of high performance products.
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