Embedded Design Flow Workshop - Xilinx Web viewFPGA Design Flow using Vivado ... file contains lab...

3

Click here to load reader

Transcript of Embedded Design Flow Workshop - Xilinx Web viewFPGA Design Flow using Vivado ... file contains lab...

Page 1: Embedded Design Flow Workshop - Xilinx Web viewFPGA Design Flow using Vivado ... file contains lab documents in Microsoft Word and presentations in PowerPoint format for you to use

README

FPGA Design Flow using Vivado WorkshopZYBO

COURSE DESCRIPTIONThe purpose of this workshop is to introduce digital designers to the FPGA design flow using Vivado design tool. During the course of the workshop, the user will step through the complete Xilinx design flow from design entry to download. The workshop includes slides and labs to help guide the user through the flow.

1. Install Xilinx softwareProfessors may submit the online donation request form at http://www.xilinx.com/member/xup/donation/request.htm to obtain the latest Xilinx software. The workshop was tested on a PC running Microsoft Windows 7 professional edition. Vivado 2016.2 System Edition

2. Setup hardwareConnect ZYBO

a. Set the power supply jumper to USB so the board can be powered up and laboratory assignments can be carried out using single micro-usb cable

b. Connect micro USB cable between PROG UART port of ZYBO and PC

3. Install distribution Extract the 2016_2_zynq_sources.zip file in the c:\xup\fpga_flow directory. This will create a 2016_2_zynq_sources folder. Create the c:\xup\fpga_flow\2016_2_zynq_labs directory. This is where you will do the labs. Download the 2016_2_zynq_labdocs_pdf.zip file which consists of lab documents in the PDF format. Extract this zip file in the c:\xup\fpga_flow directory or any other directory of your choice.

4. For Professors onlyDownload the 2016_2_zybo_labsolution.zip and 2016_2_zynq_docs_source.zip files using your membership account. Do not distribute them to students or post them on a web site. The 2016_2_zynq_docs_source.zip file contains lab documents in Microsoft Word and presentations in PowerPoint format for you to use in your classroom.

5. Get StartedReview the presentation slides (see course agenda) and step through the lab exercises (see lab descriptions) to complete the labs.

http://www.xilinx.com/member/xup/donation/request.htm
Page 2: Embedded Design Flow Workshop - Xilinx Web viewFPGA Design Flow using Vivado ... file contains lab documents in Microsoft Word and presentations in PowerPoint format for you to use

README

COURSE AGENDA

Day 1 Agenda Day 1 MaterialsClass Intro 01_class_intro.pptx7-Series Architecture Overview 11_7_Series_Architecture_Overview.ppt xVivado Design Flow 12_ Vivado Design Flow.pptxLab 1: Vivado Design Flow 12a_lab1_intro.pptx

Lab1.docxSynthesis 13_Synthesis.pptxLab 2: Synthesizing a RTL Design 13a_lab2_intro.pptx

Lab2.docxImplementation and STA 14_ Implementation_and_STA.pptxLab 3: Implementing and Verify the design in hardware

14a_lab3_intro.pptxLab3.docx

Day 2 Agenda Day 2 MaterialsIP Integrator and IP Catalog 15_ IPI_and_IP_Catalog.pptxLab 4: Using IP Catalog 15a_lab4_intro.pptx

Lab4.docxXilinx Design Constraints 16_Xilinx_Design_Constraints.pptxLab 5: Xilinx Design Constraints 16a_lab5_into.pptx

Lab5.docxHardware Debugging 17_Hardware_Debugging.pptxLab 6: Hardware Debugging 17a_lab6_intro.pptx

Lab6.docx

LAB DESCRIPTIONSLab 1 - Vivado Design Flow: Use Vivado IDE to create a simple HDL design targeting the ZYBO. Lab 2 - Synthesizing a RTL Design: Synthesize a design with the default settings as well as some settings changed and observe the effect. Lab 3 - Implementing and Verify the design in hardware: Implement the synthesized design of previous lab, perform timing analysis, generate bitstream, download the bitstream and verify the functionality. Lab 4 - Using IP Catalog: Use the IP Catalog to generate a clock resource and instantiate in a design. Use IP Integrate to generate a core and instantiate in the design.Lab 5 - Xilinx Design Constraints: Create a project with I/O Planning type, enter pin locations, and export it to the rtl. Then create the timing constraints and perform the timing analysis. Lab 6 - Hardware Debugging: Use Mark Debug feature and also available Integrated Logic Analyzer (ILA) core (available in IP Catalog) to debug the hardware.

6. Contact XUPSend an email to [email protected] for questions or comments

mailto:[email protected]

Vivado Design Suite User Guide - Xilinx€¦ · Appendix B: Vivado Simulator Mixed Language Support and Language Exceptions ... • Vivado Design Suite User Guide: Using the Vivado

Vivado Design Suite User Guide - Xilinx€¦ · Appendix B: Vivado Simulator Mixed Language Support and Language Exceptions ... • Vivado Design Suite User Guide: Using the Vivado

Vivado Design Suite Tutorial - Xilinxchina.xilinx.com/.../ug947-vivado-partial-reconfiguration-tutorial.pdf · Vivado Design Suite Tutorial . Partial ... (PR) design flow, example

Vivado Design Suite Tutorial - Xilinxchina.xilinx.com/.../ug947-vivado-partial-reconfiguration-tutorial.pdf · Vivado Design Suite Tutorial . Partial ... (PR) design flow, example

Jose Vivado

Jose Vivado

Vivado HLS Design Flow Lab - Xilinx · 01/03/2012  · This lab comprises 9 primary steps: You will create a new project in Vivado HLS, run simulation, run debugger, synthesize the

Vivado HLS Design Flow Lab - Xilinx · 01/03/2012  · This lab comprises 9 primary steps: You will create a new project in Vivado HLS, run simulation, run debugger, synthesize the

Vivado Tutorial

Vivado Tutorial

Vivado Design Suite User Guide - Xilinx Design ... • Vivado Design Suite Tcl Command Reference Guide ... • Vivado Design Suite User Guide: Using Tcl ...

Vivado Design Suite User Guide - Xilinx Design ... • Vivado Design Suite Tcl Command Reference Guide ... • Vivado Design Suite User Guide: Using Tcl ...

Vivado Design Suite Tutorial - japan.xilinx.com · Vivado Design Suite Tutorial Logic Simulation UG937 ... Using Cursors, ... you must update your Vivado ...

Vivado Design Suite Tutorial - japan.xilinx.com · Vivado Design Suite Tutorial Logic Simulation UG937 ... Using Cursors, ... you must update your Vivado ...

Vivado Design Suite - Xilinx...The Vivado Design Suite provides an IP-centric design flow that helps you quickly turn designs and algorithms into reusable IP. The Vivado IP catalog

Vivado Design Suite - Xilinx...The Vivado Design Suite provides an IP-centric design flow that helps you quickly turn designs and algorithms into reusable IP. The Vivado IP catalog

Vivado tutorial - Xilinx1-1-1. Open Vivado by selecting Start > All Programs > Xilinx Design Tools > Vivado 2013.3 > Vivado 2013.3 1-1-2. Click Create New Project to start the wizard.

Vivado tutorial - Xilinx1-1-1. Open Vivado by selecting Start > All Programs > Xilinx Design Tools > Vivado 2013.3 > Vivado 2013.3 1-1-2. Click Create New Project to start the wizard.

Vivado tutorial - · PDF fileVivado Tutorial Introduction This tutorial guides you through the design flow using Xilinx Vivado software to create a simple digital circuit using Verilog

Vivado tutorial - · PDF fileVivado Tutorial Introduction This tutorial guides you through the design flow using Xilinx Vivado software to create a simple digital circuit using Verilog

Vivado Design Suite Tutorialjapan.xilinx.com/.../ug997-vivado-power-analysis-optimization-tutorial… · Vivado Design Suite Tutorial Power Analysis and Optimization UG997 (v2016.3)

Vivado Design Suite Tutorialjapan.xilinx.com/.../ug997-vivado-power-analysis-optimization-tutorial… · Vivado Design Suite Tutorial Power Analysis and Optimization UG997 (v2016.3)

Vivado Design Suite - Xilinx...3. As an alternative, click the Vivado 2018.x Desktop icon to start the Vivado IDE. The Vivado IDE Getting Started page, shown in the following figure,

Vivado Design Suite - Xilinx...3. As an alternative, click the Vivado 2018.x Desktop icon to start the Vivado IDE. The Vivado IDE Getting Started page, shown in the following figure,

Vivado Design Suite User Guide - Xilinx · as it relates to the entire FPGA design flow, refer to the Vivado Design Suite User Guide: Using the Integrated Design Environment (UG893).

Vivado Design Suite User Guide - Xilinx · as it relates to the entire FPGA design flow, refer to the Vivado Design Suite User Guide: Using the Integrated Design Environment (UG893).

Vivado tutorial - china.origin.xilinx.com · Lab Workbook Vivado Tutorial Nexys4 Vivado Tutorial-1 xup@xilinx.com © copyright 2013 Xilinx Vivado Tutorial Introduction This tutorial

Vivado tutorial - china.origin.xilinx.com · Lab Workbook Vivado Tutorial Nexys4 Vivado Tutorial-1 [email protected] © copyright 2013 Xilinx Vivado Tutorial Introduction This tutorial

Debian Linux on Zynq (Xilinx ARM-SoC FPGA) Setup Flow (Vivado 2015.4)

Debian Linux on Zynq (Xilinx ARM-SoC FPGA) Setup Flow (Vivado 2015.4)

Vivado Design Suite Tutorial - Xilinx...The Vivado Design Suite provides an IP-centric design flow that helps you quickly turn designs and algorithms into reusable IP. As shown in

Vivado Design Suite Tutorial - Xilinx...The Vivado Design Suite provides an IP-centric design flow that helps you quickly turn designs and algorithms into reusable IP. As shown in

UG939 (v2020.2) February 4, 2021 Vivado Design Suite Tutorial · 2021. 7. 31. · 3. As an alternative, click the Vivado 2020.2 Desktop icon to start the Vivado IDE. The Vivado IDE

UG939 (v2020.2) February 4, 2021 Vivado Design Suite Tutorial · 2021. 7. 31. · 3. As an alternative, click the Vivado 2020.2 Desktop icon to start the Vivado IDE. The Vivado IDE

Vivado Design Suite User Guide: Using the Vivado IDE

Vivado Design Suite User Guide: Using the Vivado IDE

Vivado HLS Tutorial

Vivado HLS Tutorial

Vivado Design Suite User Guide - Xilinx · You can use Tcl scripts to run the entire design flow, including design analysis, or to run only parts of the flow. Vivado Design Suite

Vivado Design Suite User Guide - Xilinx · You can use Tcl scripts to run the entire design flow, including design analysis, or to run only parts of the flow. Vivado Design Suite