Microelectronics Journal 47 (2016) 7–18

Contents lists available at ScienceDirect

Microelectronics Journal

http://d0026-26

n CorrE-m

ysahu99rkd769@

journal homepage: www.elsevier.com/locate/mejo

On the reliability of majority logic structure in quantum-dotcellular automata

Bibhash Sen a,n, Yashraj Sahu b, Rijoy Mukherjee a, Rajdeep Kumar Nath a, Biplab K. Sikdar c

a Department of Computer Science and Engineering, National Institute of Technology, Durgapur, Indiab Department of Computer Science and Engineering, SUIIT, Burla, Odisha, Indiac Department of Computer Science and Technology, Indian Institute of Engineering Science and Technology, Shibpur, India

a r t i c l e i n f o

Article history:Received 22 July 2015Received in revised form6 November 2015Accepted 7 November 2015

Keywords:Quantum-dot cellular automata (QCA)ReliabilityFault tolerant logicQCA tilesQCA defectsMajority voter

x.doi.org/10.1016/j.mejo.2015.11.00292/& 2015 Elsevier Ltd. All rights reserved.

esponding author. Tel.: þ91 343 275 4237.ail addresses: bibhash.sen@cse.nitdgp.ac.in (B.@gmail.com (Y. Sahu), rijoy.mukherjee@gmaigmail.com (R.K. Nath), biplab@cs.becs.ac.in (

a b s t r a c t

Quantum-dot cellular automata (QCA) is projected to be a promising nanotechnology due to its extre-mely small feature size and ultra low power consumption. However, acceptance of a QCA design islimited due to its high defect rate. Efficient fault tolerant schemes are, therefore, needed for reliabledesign. This work targets design of a new fault tolerant scheme around QCA logic primitives whichencapsulates two different orientations of QCA cell. A 2�2 array of four rotated (‘þ ’) cells, calledcomplementary tile (CT), is introduced to maximize the throughput. It ensures 100% fault toleranceunder single cell missing defect. Two reliable majority voters (RMV), based on the CT, are designed whichoutperforms the existing majority logic in QCA. The functional characterization and polarization of RMVunder different cell deposition (missing/additional) defects are covered. The significance of the clockingin fault tolerance is also investigated with RMV with multi clock zone. The error probability model for theproposed RMV, under cell deposition (missing/additional) defect, is developed to ensure better under-standing of reliability in QCA.

& 2015 Elsevier Ltd. All rights reserved.

1. Introduction

As CMOS devices reach their fundamental limits, they willincreasingly suffer from lower design tolerances and fabricationvariability, which have negative impacts on reliability and result inincreased device failure rates. These future limitations of CMOShave led many to consider novel nanometer-scale devices that areexpected to have faster switching speed, lower power consump-tion, and better scaling characteristic [1]. Quantum-dot cellularautomata (QCA) have emerged as one of the promising newtechnologies for future generation ICs that overcome the limitationof CMOS [2]. In QCA, information is transferred and transformedby Columbic interactions among basic elements (referred to ascells) rather than electrical currents as in CMOS-based VLSI. So theposition of a cell in the logic gate/circuit is very important as itmay result in erroneous output.

Two arrangements of quantum-dot within a cell referred to asthe 90° (‘� ’) normal cell and the 45° (‘þ ’) rotated cell can beutilized to compute the binary information. The rotated cell isidentical in all ways to the standard cell except it is rotated by ‘45°’

Sen),l.com (R. Mukherjee),B.K. Sikdar).

[2,3]. The fundamental unit of QCA based design is the 3-inputmajority gate. Due to the functional incompleteness of majoritylogic, an additional inverter is mandatory for majority gate toconstitute the universal minority function. Rigorous research isgoing on towards the implementation of complex logic structurein QCA which can be viable for alternative current CMOS [4–16].

According to [17], the predictable huge complexity of nanoarchitectures enforces the requirement of a high fault tolerance.QCA also confronts the challenges of many defects which is firstexplained in [18,19]. Though other fault like stray charge androtational defect may also occur in QCA logic, the cell misplace-ment (cell misalignment, presence/absence of a cell) has beenidentified as the prime source of defect for QCA because the pro-cess of cell deposition is very sensitive. The importance of thereliability of majority voter stems from its use as logic primitives infault-tolerant architectures around QCA [20,21].

Several attempts are made to realize fault tolerant structurearound majority logic [22–28]. To achieve a reliable architecture,QCA tiles with redundant cells are identified as prominent one.This approach ensures at most 67% fault tolerance under single cellmissing defect [21,20]. Realization of coplanar wire-crossing usingboth 45° cell and 90° cell, as in [30], is difficult, but such restrictioncan be averted with the introduction of clock zone based approachas described in [31,4]. The fabrication issue related to cell

A A

B

B

’+’ Cell

’X’ Cell

AOutputInputA’

Binary ’1’P = +1

Binary ’0’P = −1

FMajCBA

F = AB + BC + CA

A

C

B F

2

3

4

1Switch Release

Relax

Hold

Tunnelling Potential

JunctionQuantum Well Tunnel

90−d

egre

e or

ient

atio

n

Localised Electron

45 d

egre

e or

ient

atio

n

A A’

Inverter chain

Fig. 1. QCA basics. (a) Structure of a QCA cell. (b) QCA cell with two polarization.(c) Majority voter. (d) Inverter. (e) Wire-crossing. (f) Clocking.

B. Sen et al. / Microelectronics Journal 47 (2016) 7–188

placement of rotated and non-rotated cell towards the realizationof coplanar wire-crossing is addressed in [4].

On the other hand, Von Neumann proposes probabilistic char-acteristics of a system in which each component can fail inde-pendently with a probability of ε [32]. Neumann states that asystem built with unreliable components can compute reliablywhen ε is sufficiently small. In general, a reliable system is definedas one that performs computation with a probability of outputerror less than 1=2. When the probability of output error reaches 1

2,the results of computation become irrelevant to the inputs andrestoration of the outputs to correct signal values is not possible.

In this context, we attempt to design reliable QCA logic pri-mitives that can ensure highly fault tolerant QCA designs, underdifferent cell deposition (missing/additional) defects. The issue offault tolerance has been so far analysed from an implementationtechnology point of view [17,33] and very few on architecturalpoint of view [27,28]. In this paper we study the issue of faulttolerance from an architectural point of view. At this point,designing QCA is an “in-principle” activity meant to explore whatmight be possible if and when the fabrication issues are overcome[3]. This work focuses on the architectural issues associated withcell deposition (missing/additional) defects which occur duringmanufacturing of circuits. The major contributions of this workaround reliable QCA architecture can be summarized as follows:

� This paper investigates a new design of the tiniest QCA tilestructure (2�2) with hybrid cell (cell with ‘� ’ and ‘þ ’ orien-tation), called complementary tile (CT). The reliability of theQCA structure CT is reported.

� Based on the proposed QCA CT, a new reliable majority voter(RMV) is developed which achieves a high degree of robustnessin terms of misalignment, missing, and dislocation of cells. Theeffectiveness of the design is established as physical proofs aswell as through simulation.

� Detailed characterization of functional properties of the pro-posed logic is described.

� Estimation of error-reliability trade off of a QCA circuit isexplored with error probability model.

� It is established over the other existing implementations thatthe proposed majority gate (RMV) demonstrates significantimprovement in terms of area, complexity, and robustness.

This paper is organized as follows. Section 2 deals with pre-liminaries including a brief overview of QCA technology. Relatedworks on the fault tolerant architecture are explored in Section 3.The proposed design of complementary tile is introduced in Sec-tion 5. In Section 5.3, the performance of proposed CT is reported.In Section 6, a reliable architecture of majority voter based on CT ispresented. The reliability of the proposed RMV is analyzed inSection 7 followed by the introduction of error probability metricaround RMV, to measure its reliability, in Section 8. Simulation andframework is elaborated in Section 4. The conclusion is in Section10.

2. QCA basics

A QCA cell consists of four quantum dots positioned at thecorners of a square (Fig. 1(a)) and contains two free electrons [34].The two free electrons can quantum-mechanically tunnel amongthe dots and settle either in polarization P¼�1 or in P¼þ1 asshown in Fig. 1(b). A QCA cell with polarization P¼�1 denoteslogic 0 state. On the other hand, polarization P¼þ1 defines thelogic 1 state of the cell. Timing in QCA is accomplished by thecascaded clocking of four distinct and periodic phases [34,4] asshown in Fig. 1(f).

The basic structure in QCA is the 3-input majority voter, MV(A,B,C)¼ABþBCþCA (Fig. 1(e)). It can also function as a 2-input ANDor a 2-input OR logic, if one of the three input cells is fixed toP¼�1 or P¼þ1. The QCA inverter realized in two differentorientations is shown in Fig. 1(d). Using simple chain of rotatedcell (45°)/þ-cell an inverter chain can be realised as shown inFig. 1(d). In QCA based logic, two kinds of wire crossover, calledcoplanar crossover and multilayer crossover, are possible. Due tothe fabrication constraints, multilayer wire crossing is notexplained here. Fig. 1(e) describes the co-planar wire crossingconsidering a 90° (� -cell) and a 45° (þ-cell) structure.

The position of the electrons can be found out using Eq. (1). Thestate energy is found out by calculating electrostatic energybetween each cell and its adjacent cell. Electrostatic energybetween two quantum dots in cell i and cell j is calculated asshown in the following equation [35]:

Ei;j ¼qiqj

4πεoεr j ri;j jð1Þ

where, ϵ0 is the permittivity of free space and ϵr is the relativepermittivity of the material of the quantum cell. qi and qj are thecharges of the electron dots at i and j and the distance between thetwo dots is given by ri;j ¼ j ri�rj j . The above equation is used tocalculate the electrostatic energy of the electrons inside faultydevice cell for every different input. The configuration having theminimum energy for a particular input is considered to be themost stable orientation.

Kink energy: The energy of the cell can be calculated by sum-ming over kink energy of all dots in each cell. The Kink energybetween two adjacent cells is defined as the difference in theelectrostatic energy between the two polarization states. The kinkenergy between the two cells ’i’ and ’j’, Ei;j, is calculated by keeping’i’ in its original state (constant) and ’j’ in the two differentpolarization states, and then finding the difference between thesetwo energies:

Ekink ¼ Eopp: polarization�Esame polarization

Ei;j ¼ Ei;j opp: polarization�Ei;j same polarization

2

1

3

4i

3

4 1

22

1

3

4 i j2

j4 1

3

Fig. 2. Kink Energy (Ek) of QCA cell with (a) Opposite polarization. (b) Samepolarization.

Z

F FB

dm

F

F

Extra cell

dmX

FY Y

Z

X

Z

Y

X

Y

X

Z

X

Y

Z Z

Fig. 3. (a) Defect free majority voter. (b) Missing cell. (c) Cell displacement. (d) Cellmisalignment. (e) Additional cell. (f) Rotational cell defects.

A

B

C

FA

B

F

CFig. 4. (a) Cascaded tiles. (b) Orthogonal tiles.

B. Sen et al. / Microelectronics Journal 47 (2016) 7–18 9

Ei;j ¼1

4πεoεr

X4

m ¼ 1

X4

n ¼ 1

qimqjn

j rm;n jð2Þ

The kink energy is thus the difference between these two energies(Fig. 2).

2.1. Defects in QCA

According to [19,18], defects are more likely to occur duringdeposition phase (which result in cell misplacement) (Fig. 3).These defects are mainly categorized in three parts:

� Cell omission/missing: A particular cell is missing or remainsundeposited (Fig. 3(b)).

� Cell displacement and misalignment: The defective cell is dis-placed from its original direction (Fig. 3(c) and (d)).

� Additional cell deposition: An additional cell is deposited on thesubstrate (Fig. 3(e)). This extra cell is erroneously depositedalong the device perimeter (adjacency boundary) of the original(defect-free) configuration (Fig. 3(a))

� Rotational defect: Cell rotation is defined in the case that a cell isin the precise location, but not aligned in the same direction asits neighbouring cell (Fig. 3(f)).

3. Related work

Initially, a fully/non-fully populated tile structures are investi-gated to obtain a fault tolerant design in [36]. A new approach isproposed for the design of QCA-based majority gate by consideringtwo-dimensional arrays of QCA cells (tiles) rather than a single cellin the design of such a fate. In [20], the defect tolerance properties

of PBW (processing-by-wire) are investigated when tiles areemployed using molecular QCA cells. Based on a 3�3 QCA array ofcells (Fig. 4), with different input/output arrangements, differenttiles are realized. The orthogonal tile which functions as majoritylogic can achieve only 66.67% fault tolerance. TMR (Triple ModularRedundancy), is also used for fault tolerant technique where inputlines of TMR are shared by all the copies [22]. A failure in the linesmay simultaneously affect two or all copies of computations andresults in a faulty output. A logic design majority multiplexing(Maj-MUX) has been proposed in [23] which uses NAND gates andrandom permutation multiplexing to restore a bundle of faultycopies of the same signal. It has been shown that given a sufficientnumber of restorative stages and redundant copies of the samesignal, the tolerable fault rate of a computing module is very high.However, fault tolerance of this scheme is limited by the redun-dancy rate that the overall system can afford. Also an imple-mentation of Maj-MUX requires a large number of wire crossingdevices in QCA which leads to crosstalk and erroneous inter-pretation of input bits. All these factors have motivated us to comeup with a novel gate structure which reduces the use of redun-dancy as well as the costly wire crossings.

4. Simulation setup

The design is verified using QCADesigner ver. 2.0.3. All themajority gates has been simulated using coherence vector simu-lation with following parameter: cell size¼18 nm, dot size¼5 nm,radius of effect¼80 nm, layer separation¼11.5 nm, other para-meters is set as default. The adder and flip-flop has been simulatedusing the bistable approximation and the following parametershas been used: number of samples¼128,000, cell size¼18 nm, dotsize¼5 nm, radius of effect¼65 nm, layer separation¼11.5 nm,other parameters are set as default.

5. Design of complementary tile with hybrid cell

This section investigates an alternative tile structure to achievethe desired fault tolerance in QCA circuit realizing multiple func-tions in its outputs simultaneously. It also targets a compactimplementation of such logic structure, minimizing the number oflogic gates. Rotated QCA cells (45°) have inherent inversion logicwhich can make an inverter chain as shown in Fig. 1(d). A new2�2 tile structure based on the rotated cell, called com-plementary tile (CT), is formulated in this work as shown in Fig. 5(a). In Fig. 5(a), driver cell have ‘þ ’ orientation and input-outputQCA cell have ‘� ’ orientation. In CT, outputs ðF1¼ F2Þ are com-plementary to each other (Fig. 5(c)).

An alternative complementary tile with � -cell as the driver, isalso shown in Fig. 5(b). But due to lack of proper polarization(o0:5) this structure is discarded.

A F1

F2

A

F2

F1

Fig. 5. Complementary tiles with (a) ‘þ ’ driver cell. (b) ‘� ’ driver cell. (c) Simula-tion result.

E3

E4

E7 4

1

2

A

F2

3E1 E2E5

E6

E8

Ea

EbF1

Y

X

E3

E4

E7 4

1

2

F1A

F2

3E1 E2

X

Y

E5

E6

E8

Ea

Eb

Fig. 6. Missing cell position of CT for (a) Case A. (b) Case B.

Table 1Estimation of kink energy at F2 under dif-ferent polarization.

Electron x Electron y

Case AUA¼0.713�10�20 UA¼0.475�10�20

UB¼0.713�10�20 UB¼0.475�10�20

U1¼1.55�10�20 U1¼0.571�10�20

U2¼1.69�10�20 U2¼0.751�10�20

U3¼1.04�10�20 U3¼0.525�10�20

U4¼0.575�10�20 U4¼0.379�10�20

U5¼1.27�10�20 U5¼1.15�10�20

U6¼0.856�10�20 U6¼0.606�10�20

U7¼0.707�10�20 U7¼0.464�10�20

U8¼0.515�10�20 U8¼0.460�10�20

UT¼15.485�10�20ðJÞCase BUA¼0.543�10�20 UA¼0.465�10�20

UB¼0.465�10�20 UB¼0.543�10�20

U1¼0.751�10�20 U1¼0.765�10�20

U2¼0.765�10�20 U2¼1.55�10�20

U3¼0.575�10�20 U3¼0.810�10�20

U4¼0.397�10�20 U4¼0.525�10�20

U5¼0.835�10�20 U5¼10.331�10�20

U6¼0.542�10�20 U6¼1.15�10�20

U7¼0.460�10�20 U7¼0.719�10�20

U8¼0.408�10�20 U8¼0.707�10�20

UT¼23.306 �10�20ðJÞ

AE3

E4

E7

E6

4

3

2

X

E8Eb

Ea

Y

E5

F2

F1E3

E4

E7 42

F1A

F2X

Y

E5

E6

E8

Ea

Eb

3

Fig. 7. Polarization of CT under #1 cell missing defect when (a) F2 with P ¼ þ1.(b) F2 with P ¼ �1.

B. Sen et al. / Microelectronics Journal 47 (2016) 7–1810

5.1. Physical verification of complementary tile

To verify the functioning of the proposed complementary tile,the polarization of input cell A as well as the polarization of outputcell F1 is considered as �1 (boolean 0). Firstly, to find the positionof an electron in the output cell, the electrostatic energies at dif-ferent positions of the driver and input cells are considered. Foreach input combination, the position of the electron having theleast energy is considered to be its target position. The quantumdots in the input cell are marked with Ea to Eb and the driver cellsare marked from E1 to E8. The quantum dots of the output cell aremarked as x and y as shown in Fig. 6. Electrostatic energy atposition x due to electron at position EA in cell ’A’ is keq=ra, whererax is the distance between Ea and x. Similarly electrostatic energyat position x due to electron position at Eb and E1–E8 is calculated.The deliberation of the total electrostatic energy at position x(denoted as Ux) is shown below.

For test case A, UA ¼ ðkeq=raxÞþðkeq=rbxÞ ¼ 0:713� 10�20 j;where, keq ¼ q2=4πεoεr ¼ 23:04� 10�20

Likewise, electrostatic energy at position y is calculated asindicated in Table 1. We consider two cases

Case A: Assume that the polarization of output cell F2 to be þ1as shown in Fig. 6(a) and measure the kink energy of the electronsx and y of the output cell F2.

Case B: Consider the polarization of output cell F2 to be �1 asshown in Fig. 6(b).

The kink energy is presented in Table 1. It is clear from theabove observation that case (A) has lower kink energy and is more

stable. Thus the complementary behaviour of the proposed tile isproved.

5.2. Reliability analysis of complementary tile

In order to develop a viable and usable QCA model, it isnecessary to understand the behaviour and robustness of QCAdevices. Specifically, the effects of cell misalignment, dot dis-placement, thermal effects, and other faults must be thoroughlyinvestigated. The proposed fault-tolerant CT has four driver cells.All the faults that may occur in driver cells should be checked toverify the correctness of this tile. Here, one of the faults (missingcell 1) is considered. The fault tolerant capability of the com-plementary tile can be verified from Table 1 for case (A) and case(B). If the cell numbered 1 is missing, then the kink energy of thesystem can be UT- ðUx

1þUx2þUy

1þUy2Þ (where Ux and Uy denote the

energy of electrons with respect to x and y electrons respectively).The missing cell position for cell numbered 1 for the two cases areshown in Fig. 7. Kink energy (UT) for Fig. 7(a) is 10.923�10�20 andKink energy (UT) for Fig. 7(b) is 19.469�10�20. The kink energy inFig. 7(a) is less than that of Fig. 7(b) and hence is more stableconfiguration. This is true for all other cases also. Considering theabove computing, it can be deduced that the proposed structurefor implementing a fault-tolerant design in QCA is correct andresulted in a correct state for t s occur.

B. Sen et al. / Microelectronics Journal 47 (2016) 7–18 11

If cell 3 is missing, a negligible drop in polarization is observedat F2 due to slight changes in polarization of the cell at that zone(red circled in Fig. 8(a)). However, a stable output has been pro-pagated due to the radius of effect of each cell in complementarytile which controls the polarization of the output cells. This changeof polarization can also be nullified placing an additional cell inbetween driver cell in the output cell as shown in Fig. 8(b). Theseadditional cells incur no penalty in terms of area or latency. Whencell 3 is missing: for input¼0, F1¼0, F2¼1, the value of kinkenergy is 11:603� 10�20ðJÞ and for input¼0, F1¼0, F2¼0: kinkenergy is 10:448� 10�20ðJÞ. However, a very little difference ofkink energy is estimated. Simply due to the position of output celland interaction of other cells in CT, it achieves the complementaryoutput of the input signal. Since the CT is used as a basic unit tosynthesize primitive majority logic later, no such drop in polar-ization is found due to the radius of effect of other signal cells inmajority logic (Fig. 8(c)).

5.3. Performance analysis

The fanout is important as it is necessary for complex digitallogic circuits and is essential for compact designs, as multiple cellscan be driven by a single driver cell. Fanout in QCA is also a directdemonstration of power gain in QCA circuits. The smallest tile(2�2) having cells in same orientation (normal tile (NT)) achievesonly fanout without any inversion output (Fig. 9 (a)). Inversion can

F2

F1

A

F2

F1

B

C

A

F2

F1A

Fig. 8. CT under cell #3 missing defect. (For interpretation of the references tocolour in this figure caption, the reader is referred to the web version of this paper.)

A

F2

F1 A

F2

F1

Input

O1

O2

O

Fig. 9. QCA 2�2 tiles. (a) Fanout. (b) Conventional complementary tile. (c) Complementhere. (f) Complementary tile with triple fanout.

be realized with a floating cell placed diagonally on that tile asshown in Fig. 9(b). But it is more prone to defect as well as itsoutputs are less polarized. Recently, two new fanout with com-plementary outputs are explored in [37] for efficient wirecrossingin QCA. These are solely useful wiring in QCA only. No primitivemajority logic can be derived efficiently, which is one of our goalsas well.

A comparative analysis of complementary tile structures isprovided in Tables 2 and 3. The proposed CT can tolerate up to8 nm left/right/up/down direction where as other existing canachieve maximum 3–4 nm only. In order to achieve more stability,electrons of QCA cells are arranged in a manner to achieve mini-mum kink energy [38]. All other existing complementary tilenever possesses 100% fault tolerance against all single celldeposition (missing and additional deposition both) defect asshown in Table 3. The removal of the cell (just before the outputcell) decreases the polarization in all existing complementary tiles.But the removal of such cell from the proposed complementarytiles never decreases polarization. It is apparent from Table 3 thatthe CT is of more stable (less kink energy) and error tolerant(almost 100%) structure in the absence of other deviation from theideal architecture than the fact of the missing and additional celldefect.

The single, double and triple fan-out tiles are also used as partof the interconnect. The triple fanout using CT is possible as shownin Fig. 9(f). In Fig. 9(f), F2 and F3 are inverted fanout whereas F1 isnormal fanout. So without using additional inverter logic, com-plemented and uncomplemented output can be generated simul-taneously. The most effective use of CT can be observed in a designwhere both the F1 and F2 are utilized simultaneously.

6. Design of reliable majority logic

Utilizing the varied functionality offered by complementary tile(CT), a novel fault tolerant design of majority gate is proposed inthis work which has a non-fully populated tile structure (Fig. 10

3Input

O1 O2A

F2

F1

A F1

F2

ary tile 1 in [37]. (d) Complementary tile 2 in [37]. (e) Complementary tile proposed

Table 2Permissible displacement of output cells.

Design Function Right(nm)

Left (nm) Up (nm) Down(nm)

Conventional CT (Fig. 9(b))

F1 4.0 2.8 1.5 –

F2 1.5 – 2.8 4.1CT1 in [37] O1 3.0 3.0 1.0 –

(Fig. 9 (c)) O3 1.0 – 3.0 3.0CT2 in [37] O1 3.0 3.0 – 1.0(Fig. 9 (d)) O2 4.0 4.0 – 1.0CT Proposed F1 4.7 – 8.0 8.0here (Fig. 9 (e)) F2 8.0 8.0 4.9 –

CT ¼ ‘Complementary tile’/tile with two complementary outputs.

Table 3Performance of complementary tiles.

Parameter Conventional tiles (Fig. 9(b)) In [37] (Fig. 9(c)) In [37] (Fig. 9(d)) Complementary tiles proposed here (Fig. 9(e))

No. of cells 4 8 8 4Inversion cells 1 0 0 0Fault tolerance under single cell missing defect 50% 37.5% 100% 100%Fault tolerance under extra single cell deposition 50% 100% 40% 100%Kink energy 9:714� 10�20 J 9:714� 10�20 J – 0:536� 10�20 J

F1

A

C

B F1

A

C

B

Fig. 10. (a) Reliable majority logic gate (RMV). (b) Alternative layout of RMV-II.(c) Simulation result.

3

B

C

1

426

7 8F1

5

PQ R

ST W

A

Fig. 11. Missing/additional cell position in majority gate.

B. Sen et al. / Microelectronics Journal 47 (2016) 7–1812

(a)) as opposed to existing majority gate structure. Here, ‘reliable’and ‘fault tolerant’ terms are used alternatively. A new ReliableMajority Voter structure (RMV) based on CT is synthesized whichrealizes 3-input majority logic is shown in Fig. 10(a). The QCA-implementation of the proposed RMV (Fig. 10(a)) has a cell countof 12 and a delay of 1 clock zone (0.25 clock cycle). The designcovers an area of 0:01 μm2.

On the other hand, clocking has been shown to have a sub-stantial effect on functionality of QCA. Further, to extend the faulttolerance capability of proposed reliable majority logic with theintroduction of clocking, an alternative structure using two clockzones, referred to as RMV-II, is also reported in Fig. 10(b). RMV-IIcan be useful in complex circuit synthesis where inputs are routedto majority voter non-uniformly, i.e inputs are not arriving tomajority logic gate with same delay. The simulation result isshown in Fig. 10(c) which verifies the majority logic function F ¼ABþBCþCA of proposed RMVs.

7. Defect characterization of RMV

In the first part of this work, we discuss how the proposedmajority gate performs with respect to missing and additional celldefects in QCA. In [39], it has been mentioned that with increase incircuit area, number of stray charges could increases. So with theincrease in surface area, the probability of generating the desired

logic decreases. The RMV gate has a surface of 11564 nm2 � 0:01μm2 which is almost comparable to the surface area of existing MVgate in the literature ð9800 nm2 � 0:01 μm2Þ. So, the performanceof both RMV and MV gate towards the effect of stray charge pre-sent in its plane is less comparable. That is why to examine thefault tolerance capability of the proposed logics, missing cell andadditional cell deposition defects are focused to a greater extenthere. To make concrete discussion, the object of the work iscompletely centred in the missing and addition cell deposition asidentified the outstanding source of QCA defects in [40]. Here, theterm ‘DEPOSITION’ is used to refer only cell missing and extra/additional cell defects alternatively.

7.1. Missing cell defect

The cell deposition location of the faulty majority voter isdepicted in Fig. 11. One or more cells may be missing from itsposition in a QCA circuit. Table 4 shows the simulation result whenat most one cell is undeposited from the RMV and RMV-II. Theprobability of generating different boolean functions versus thenumber of undeposited cells is shown in Fig. 12. An exhaustivesimulation has also been pursued for the RMVs, i.e., with i unde-posited cells, i¼1, …, 8 from the layout. For RMV, the number ofpatterns of every output function when i cells are undeposited, areshown in Table 4. Once undeposited cell defects are present, thethree input signals may also interact and different functions can begenerated at the output. In particular, variants of the majorityfunction (with complemented input variables) are expected due topossible input inversion through the cells of the tile. The variantsof the majority function are referred to as MV-like functions.

The following observations can be made from the simulationresults:

(1) In almost all cases, our proposed RMV with undeposited cells(as defects) behaves in the following two ways: wire functionsor MV/MV-like functions.

(2) Undeposited cell defects occurring in corner cells (cells 5 and7) change the logic function of the RMV to the wire. In allother cases of single cell missing defect, have no effect onoutput and thus confirming the 75% defect tolerant design. In

Table 4Overall functional characterization of RMV under multiple undeposited cell defects.

Observation Results

RMVNo. of defective cells 1 2 3 4 5 6 7 8Total defective patterns 8 28 56 70 56 28 8 1Occurrence of wire function 2 14 36 46 31 12 2 0Wire function percentage 25% 5% 64.28% 65.71% 55.35% 42.85% 25% 0Occurrence of MV function 6 12 11 6 2 0 0 0MV function percentage 75% 42.85% 19.64% 8.57% 3.57% 0 0 0Occurrence of MV like function 0 1 2 3 2 1 0 0MV like function percentage 0 3.57% 3.57% 4.28% 3.75% 3.57% 0 0Occurrence of undefined function 0 1 7 15 21 15 6 1Undefined function percentage 0 3.57% 12.5% 21.42% 37.5% 53.57% 75% 100%

RMV-II

No. of undeposited cell 1 2 3 4 5 6 7 8No. of defective patterns 8 28 56 70 56 28 8 1Occurrence of wire function 0 2 14 34 30 12 2 0Wire function percentage 0% 7.14% 25% 48.57% 53.57% 42.85% 25% 0Occurrence of MV function 8 24 33 18 6 0 0 0MV function percentage 100% 85.71% 58.92% 25.71% 10.71% 0 0 0Occurrence of MV like function 0 1 3 3 1 1 0 0MV like function percentage 0 3.57% 5.35% 4.28% 1.78% 3.57% 0 0Occurrence of undefined function 0 1 6 15 19 15 6 1Undefined function percentage 0 3.57% 10.71% 21.42% 33.92% 53.57% 75% 100%

0

10

20

30

40

50

60

70

80

90

100

1 2 3 4 5 6 7 8

MVMV-like

WireUndefined

0

10

20

30

40

50

60

70

80

90

100

1 2 3 4 5 6 7 8

MVMV-like

WireUndefined

Fig. 12. Probability of output function under missing cell defect of (a) RMV.(b) RMV-II.

B. Sen et al. / Microelectronics Journal 47 (2016) 7–18 13

RMV-II, due to introduction of second clock zone it has noinfluence on cell missing defect and thus confirms 100% defecttolerant.

(3) In the simulations using the coherence vector engine, thepolarization level never experiences a significant drop undercell missing defect. In all simulated occurrences, the magni-tude of the maximum polarization is above 0.9 eV. The sta-tistical results in the presence of up to eight undeposited cellsare summarized in Table 4. Note that by definition, the MV-like function set does not include the MV function.

We analyze the behaviour of proposed majority gate (RMV) andthe other majority gates/tiles present in the literature with respectto cell missing defect. Single and double-cell missing defects of themajority gates are given in Table 5. From Table 5, it can beobserved that under one cell missing defect, the probability ofhaving the correct majority function at the outputs is 75% for theRMV and 100% for the RMV-II whereas the existing majority logicgates achieve only 20% success. Again, in double cell missingdefect the proposed RMV logics achieve 42–75% tolerance,whereas existing majority logic gates show 0% tolerance. Evenwith multiple undeposited cells, in most cases the proposed RMVproduces a stable logic function: either the wire function, or themajority-like function (as shown in Fig. 13) which are very usefulfor logic design. The average magnitude of the maximum polar-ization level of the output when a number of cells are undepositedas defects, is shown in Fig. 13.

7.2. Additional cell deposition defect

An extra cell (both� and þ orientation) is placed in theregions around the driver cells of the RMV to investigate theeffects of defect arising out of additional cell deposition. Thepossible additional cell depositions in RMV are P, Q, R, S, T, and W(Fig. 11). Additional cell deposition is applied with different clockzones to cover all possible defects of RMV-II synthesized with twoclocks-zones. All possible extra cell deposition in RMV is reportedin Table 6. The additional cell with ‘þ ’ orientation at position Qand T in RMV results in wire function. The same thing happens incase of RMV-II due to the presence of an extra cell with ‘þ ’

orientation at position Q and T irrespective of a clock-zone. Boththe proposed RMVs show inherent immunity to the remaining all

Table 5Comparative analysis of functional behaviour of majority gates under missing cell defect.

Observation Results

MV [34] OT [20] RMV RMV-II

No. of defective cells 1 2 1 2 1 2 1 2Total defective patterns 5 10 9 36 8 28 8 28Occurrence of wire func. 2 3 0 4 2 14 0 2Wire func. percentage 40% 30% 0% 11.1% 25% 50% 0% 7.14%Occurrence of INV func. 0 2 0 4 0 0 0 0INV func. percentage 0% 20% 0% 11.1% 0% 0% 0% 0%Occurrence of MV func. 1 0 6 13 6 12 8 24MV func. percentage (FT%) 20% 0% 66.7% 36.1% 75% 42.86% 100% 85.71%Occurrence of MV like func. 1 1 3 11 0 1 0 1MV like func. percentage 20% 10% 33.3% 30.5% 0% 3.57% 0% 3.57%Occurrence of undefined state 1 4 0 4 0 1 0 1Undefined state percentage 20% 40% 0% 11.1% 0% 3.57% 0% 3.57%

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

1 2 3 4

MVMV-like

WireUndefined

Total

Fig. 13. Average polarization of RMV under cell deposition.

Table 6Analysis of additional cell deposition defect in RMV.

Position Type Clock Polarization Output

RMV

P � 0 0.968 Maj(A,B,C)þ 0 0.968 Maj(A,B,C)

Q � 0 0.969 Maj(A,B,C)þ 0 0.968 A

R � 0 0.968 Maj(A,B,C)þ 0 0.970 Maj(A,B,C)

S � 0 0.968 Maj(A,B,C)þ 0 0.968 Maj(A,B,C)

T � 0 0.969 Maj(A,B,C)þ 0 0.968 C

W � 0 0.968 Maj(A,B,C)þ 0 0.970 Maj(A,B,C)

RMV-II

P � 0 0.968 Maj(A,B,C)þ 0 0.968 Maj(A,B,C)� 1 0.968 Maj(A,B,C)

B. Sen et al. / Microelectronics Journal 47 (2016) 7–1814

other cases ensuring a reliable system with more than 83% faultagainst the additional cell deposition defect.

þ 1 0.968 Maj(A,B,C)Q � 0 0.969 Maj(A,B,C)

þ 0 0.968 A� 1 0.969 Maj(A,B,C)þ 1 0.968 A

R � 0 0.968 Maj(A,B,C)þ 0 0.970 Maj(A , B,C)� 1 0.968 Maj(A,B,C)þ 1 0.970 Maj(A,B,C)

S � 0 0.968 Maj(A,B,C)þ 0 0.968 Maj(A,B,C)� 1 0.968 Maj(A,B,C)þ 1 0.968 Maj(A,B,C)

T � 0 0.969 Maj(A,B,C)þ 0 0.968 C� 1 0.969 Maj(A,B,C)þ 1 0.968 C

W � 0 0.968 Maj(A,B,C)þ 0 0.970 Maj(A,B, C )� 1 0.968 Maj(A,B,C)þ 1 0.970 Maj(A,B,C)

8. Error characteristics of majority gates

In this section, the error probability of the majority logics isestimated based on the results reported in this paper. In [7], afamily of new appropriate QCA cost functions, based on its basiclogic elements (MV, inverter, wire-crossing, etc.) and delay areproposed to evaluate a QCA design. But these are not appropriatefor evaluating the reliability of the QCA logic circuit. In this work,the effect of different QCA defects is studied. It is found that thenumber of occurrences of missing/extra cell deposition defects isthe important metrics that should be considered when comparingreliable QCA designs. A family of new metrics for evaluating reli-able/fault tolerant QCA circuits is next introduced.

In [41], an analytical method was provided to characterize theinput to the output error probability of majority logic with a gateerror ε. But, the defect in wires, crossovers and inverter are notconsidered in the analysis. Two expressions were derived fromVon Neumann's work [32]. When all the nominal inputs are equal,the output probability p0 is computed with respect to gate error εand input error p as

p0 ¼ εþð1�2εÞð3p2�2p3Þ ð3Þ

When two of the nominal inputs are equal, the same can beexpressed as :

p0 ¼ εþð1�2εÞð2p�3p2þ2p3Þ ð4Þ

In the accompanying discussion, we provide a mechanism tocompute the error probability in QCA under different cell deposi-tion (missing/additional) defects and then we apply the aboveequations of the majority logic developed in this work.

8.1. Error probability model under cell deposition defect (missing/additional)

Error in output of the molecular QCA component can result indue to cell missing defect, extra cell defect. Here, to compute error

B. Sen et al. / Microelectronics Journal 47 (2016) 7–18 15

probability, we consider the error due to cell missing defect andextra cell defect is defined. The error probability due to cellmissing defect εm is defined as

εm ¼ ε1mþε2mþε3mþε4mþ⋯þεnmn

; ð5Þ

for a QCA component with nþ1 cells, where εim is error prob-ability due to i cells missing from the components. For betterunderstanding, we limit the computation up to 2 missing celldefects. From the missing cell defect analysis, the error probabilitycan be computed as

εim ¼Number of wrong output patternsNumber of defective patterns

: ð6Þ

Similarly the error probability due to additional cell depositiondefect εd is computed as

εd ¼Number of wrong output patterns

Number of cells deposited: ð7Þ

Finally, the error probability ε is defined as

ε¼ εmþεd2

: ð8Þ

The above equations are considered to the 3 majority gates. The εmcomputed based on the data provided in Table 5 for missing cell

MVRMV

RMV-IIp=p’

Fig. 14. Output error probability vs. input error probability of majority gates withall inputs identical.

MVRMV

RMV-IIp=p’

Fig. 15. Output error probability vs. input error probability of majority gates with2 inputs identical.

defect are

ε1m ¼ 45¼ 0:80 using ð6Þ

ε2m ¼ 1010¼ 1 using ð6Þ

εm ¼ 0:80þ12 ¼ 0:90 using ð5Þ

8>><>>:

9>>=>>;For existing majority gate

ε1m ¼ 28¼ 0:25 using ð6Þ

ε2m ¼ 1628¼ 0:57 using ð6Þ

εm ¼ 0:25þ0:572 ¼ 0:41 using ð5Þ

8>><>>:

9>>=>>;For proposed RMV

ε1m ¼ 08¼ 0 using ð6Þ

ε2m ¼ 428¼ 0:143 using ð6Þ

εm ¼ 0þ0:1432 ¼ 0:0715 using ð5Þ

8>><>>:

9>>=>>;For proposed RMV� II

The εd, using data in Table 6, for additional cell deposition(applying Eq. (7)) are

εd ¼04¼ 0; for existing majority gate

εd ¼212

¼ 0:167; for RMV

εd ¼624

¼ 0:25; for RMV� II

Next, we calculate the error probability ε for each majority gatefollowing Eq. (8):

ε¼ 0þ0:902

¼ 0:45; for existing majority gate

ε¼ 0:41þ0:1672

¼ 0:2885; for RMV

ε¼ 0:0715þ0:252

¼ 0:161; for RMV� II

Now, substituting the value of ε in Eqs. (3) and (4), we plot a graphbetween input and output probability for 3 identical inputs(Fig. 14) and for 2 identical inputs (Fig. 15). It can be found that theproposed gates can provide output with less error probability foran input error. So from both the figures, it can be concluded thatthe RMV is more reliable than the existing majority gate.

9. Analysis of fault tolerance in circuit synthesized with RMV

It can be observed that in a QCA circuit, uniform clock dis-tribution results in more reliable circuit over the random clockdistribution [42]. An coplanar adder can be designed in many wayswith the orientations of input and output [4,?,?]. Recently, a newcoplanar wire-crossing is proposed which uses aforesaid non-adjacent clock zones for the two crossing wires [4] which incursmost optimum circuit area. In [5], Angizi et al. stated that cells onthe hold phase (clk 1) can cross cells on the relax phase (clk 3) andcells on the switch phase (clk 0) can cross cells on the releasephase (clk2) without polarization effect. In this work, all the wir-ecrossings in full adder are organised with (clk 0, clk2) or (clk 1, clk3) clock phases. Based on the clock based approach, as in [4], thefull adder circuit is synthesized using both conventional andproposed RMV gate as shown in Fig. 16. The simulation results inFig. 17 verifies the correct functionality of the adder. The faulttolerance capability implementing full adder is reported in Table 7.It is evident that proposed RMV logic outperforms over the con-ventional majority logic with enviable 90.58% fault tolerance. Also,a 4-bit ripple carry adder is implemented with the proposed RMVas shown in Fig. 18.

However, it is found that for a complex circuit, the incomingsignals to driver cell of majority logic may traverse an unequal

B1

B2 A2

B3 A3

Cout

S2

S3

Fig. 18. 4-bit ripple carry ad

Fig. 17. Simulation result of adder circuit using RMV gate.

S

Cout

XY

Cin

XY

CinCout

S

Fig. 16. Adder circuit using (a) conventional majority. (b) RMV gate.

B. Sen et al. / Microelectronics Journal 47 (2016) 7–1816

number of cells/wire-length and that results in more delay insignal propagation and switching. So, if the driver cell is placed inthe same clock zone as that of the wire for the incoming signal, thedesired function may not be generated. The input signal with lesspropagation time controls the device cell. Therefore, if the wiresfrom the inputs are in clock zone d, then majority gate is placed inðdþ1Þmod 4 clock zone. If the generated function is to be used asinput to another gate then the wires leading to that gate is placedin ðdþ2Þmod 4 clock zone and so on. So number of clock zonesrequired for such complex circuit increases. In this scenario, theproposed majority gate (RMV-II) with 2 clock zones, is found to bemost efficient. The wire from the inputs of various lengths leadingto the gate can be in the same clock zone (assume d) as that of thedriver cell. Only, CT needs to be in a different clock zone ofðdþ1Þmod 4. Already the performance of proposed RMV is foundimpressive over conventional logic implementing full adder cir-cuit. In the following paragraph, we described the performance ofthe proposed RMV-II implementing D flip-flop which utilizesaforesaid clocking scheme.

The D flip-flop circuit is synthesized using both the proposedRMVs gate as shown in Fig. 19. Missing cell deposition defects ofRMV and RMV-II in implementing adder circuits and D Flip-flopsare reported in Table 8. The Majority with two clock zone (RMV-II)is much more fault tolerant in both the cases. Thus, it can beconcluded that the very large/complex circuit constructed withRMV-II is more cost effective in terms of both signal propagationand fault tolerance.

Table 7Performance of majority logics implementing full adder.

Design Observation No. of missing cell deposition

1 2 3

No. of defective patterns 15 30 30Majoritya No. of correct output 1 0 0

Fault tolerance (%) 6.67 0 0No. of defective patterns 24 84 168

RMV No. of correct output 17 33 30Fault tolerance (%) 70.83 41.67 17.85

Improvement in fault tolerance is 90.58%.

a Conventional majority logic.

A0B0

Cin

A1

S0S1

der's (RCA) using RMV.

Table 8Performance of RMVs under Missing cell defect.

Design observation D Flip-flop

method No. of undeposited cells 1 2 3

No. of defective patterns 24 84 168RMV No. of correct output 21 59 92

FT 87.5 70.24% 54.76%No. of defective patterns 22 84 168

RMV-II No. of correct output 24 74 112FT 100% 88.09% 66.67%

FT, Fault tolerance.

-1.00

1.00

D

Q

-1.00

1.00

D

Q

Fig. 19. D Flip flop using proposed (a) RMV. (b) RMV-II.

B. Sen et al. / Microelectronics Journal 47 (2016) 7–18 17

10. Conclusion

This work has presented a novel design of fault tolerantmajority logic primitives by employing basic block (referred to ascomplementary tile) for assembling QCA circuits prior to celldeposition on a substrate. The complementary tile proposed hereconsists of 2�2 grid of cells with two complementary outputs(F1¼ F2) achieving 100% fault tolerance under single cell missingdefect. A reliable majority voter (RMV) is then developed aroundthe proposed CT. The proposed RMV structure is also found to befault tolerant under cell deposition (missing/additional) defects.Further, the reliability of RMV is estimated based on the analysis ofoutput error probability. It ensures the better robustness of RMVand is at least 50% more than that of the existing majority logic inQCA. The multiple undeposited cell defects in RMV deterministi-cally lead to a new logic functions in some cases. Thus, the simplearrangement in the cells and clocking makes RMV tile a viablefault tolerant design technique for QCA. To surmount the limita-tion signal distribution in circuit level, the proposed RMV-II modelis evolved as an effective module minimizing overall delay andcost of the circuit.

Acknowledgements

The authors would like to convey their sincere thanks to theanonymous reviewers for their valuable suggestions that helped inimproving the paper.

References

[1] ITRS, ITRS: international roadmap for semiconductor,, 2013, ⟨Http://www.itrs.net⟩.

[2] C.S. Lent, P.D. Tougaw, W. Porod, G.H. Bernstein, Quantum cellular automata,Nanotechnology 4 (1993) 49, [online] http://stacks.iop.org/0957-4484/4/i=1/a=004.

[3] C.S. Lent, Personal communication on cell placement with different rotationand its fabrication issues, University of Notre Dame, 20 June 2015.

[4] D. Abedi, G. Jaberipur, M. Sangsefidi, Coplanar full adder in quantum-dotcellular automata via clock-zone-based crossover, IEEE Trans. Nanotechnol. 14(2015) 497–504, http://dx.doi.org/10.1109/TNANO.2015.2409117.

[5] S. Angizi, E. Alkaldy, N. Bagherzadeh, K. Navi, Novel robust single layer wirecrossing approach for exclusive or sum of products logic design withquantum-dot cellular automata, J. Low Power Electron. 10 (2014) 259–271,http://dx.doi.org/10.1166/jolpe.2014.1320.

[6] M. Kianpour, R. Sabbaghi-nadooshan, A novel quantum-dot cellular automatax-bit �32-bit sram, IEEE Trans. Very Large Scale Integr. (VLSI) Syst. (2015), inpress. http://dx.doi.org/10.1109/TVLSI.2015.2418278.

[7] W. Liu, L. Lu, M. O'Neill, E. Swartzlander, A first step toward cost functions forquantum-dot cellular automata designs, IEEE Trans. Nanotechnol. 13 (2014)476–487, http://dx.doi.org/10.1109/TNANO.2014.2306754.

[8] M. Taherifard, M. Fathy, Improving logic function synthesis through wirecrossing reduction in quantum-dot cellular automata layout, IET CircuitsDevices Syst. 9 (2015) 265–274, http://dx.doi.org/10.1049/iet-cds.2014.0327.

[9] M. Graziano, A. Pulimeno, R. Wang, X. Wei, M.R. Roch, G. Piccinini, Processvariability and electrostatic analysis of molecular qca, J. Emerg. Technol.Comput. Syst. 12 (2015) 18:1–18:23, http://dx.doi.org/10.1145/2738041.

[10] S. Angizi, S. Sarmadi, S. Sayedsalehi, K. Navi, Design and evaluation of newmajority gate-based {RAM} cell in quantum-dot cellular automata, Micro-electron. J. 46 (2015) 43–51, http://dx.doi.org/10.1016/j.mejo.2014.10.003.

[11] L.H. Sardinha, D.S. Silva, M.A. Vieira, L.F. Vieira, O.P.V. Neto, Tcam/cam-qca:(ternary) content addressable memory using quantum-dot cellular automata,Microelectron. J. 46 (2015) 563–571, http://dx.doi.org/10.1016/j.mejo.2015.03.020.

[12] D. Silva, L. Sardinha, M. Vieira, L. Vieira, O. Vilela Neto, Robust serial nano-communication with qc, IEEE Trans. Nanotechnol. 14 (2015) 464–472, http://dx.doi.org/10.1109/TNANO.2015.2407696.

[13] G. Causapruno, M. Vacca, M. Graziano, M. Zamboni, Interleaving in systolic-arrays: a throughput breakthrough, IEEE Trans. Comput. 64 (2015) 1940–1953,http://dx.doi.org/10.1109/TC.2014.2346208.

[14] M. Zhang, L. Cai, X. Yang, H. Cui, C. Feng, Design and simulation of turboencoder in quantum-dot cellular automata, IEEE Trans. Nanotechnol. 14 (2015)820–828, http://dx.doi.org/10.1109/TNANO.2015.2449663.

[15] V. Pudi, K. Sridharan, A bit-serial pipelined architecture for high-performance dhtcomputation in quantum-dot cellular automata, IEEE Trans. Very Large ScaleIntegr. (VLSI) Syst. 23 (2015) 2352–2356, http://dx.doi.org/10.1109/TVLSI.2014.2363519.

[16] S. Angizi, M.H. Moaiyeri, S. Farrokhi, K. Navi, N. Bagherzadeh, Designingquantum-dot cellular automata counters with energy consumption analysis,Microprocess. Microsyst. 39 (2015) 512–520, http://dx.doi.org/10.1016/j.micpro.2015.07.011.

[17] R.I. Bahar, D. Hammerstrom, J. Harlow, W.H. Joyner Jr., C. Lau, D. Marculescu,A. Orailoglu, M. Pedram, Architectures for silicon nanoelectronics and beyond,Computer 40 (2007) 25–33, http://dx.doi.org/10.1109/MC.2007.7.

[18] M. Momenzadeh, M. Ottavi, F. Lombardi, Modeling qca defects at molecular-level in combinational circuits, in: 20th IEEE International Symposium on

B. Sen et al. / Microelectronics Journal 47 (2016) 7–1818

Defect and Fault Tolerance in VLSI Systems, DFT 2005, 2005, pp. 208–216,http://dx.doi.org/10.1109/DFTVS.2005.46.

[19] M.B. Tahoori, J. Huang, M. Momenzadeh, F. Lombardi, Testing of quantumcellular automata, IEEE Trans. Nanotechnol. 3 (2004) 432–444, http://dx.doi.org/10.1109/TNANO.2004.834169.

[20] J. Huang, M. Momenzadeh, F. Lombardi, On the tolerance to manufacturingdefects in molecular qca tiles for processing-by-wire, J. Electron. Test. 23(2007) 163–174, http://dx.doi.org/10.1007/s10836-006-0548-6.

[21] J. Huang, M. Momenzadeh, L. Schiano, M. Ottavi, F. Lombardi, Tile-based qcadesign using majority-like logic primitives, J. Emerg. Technol. Comput. Syst. 1(2005) 163–185, http://dx.doi.org/10.1145/1116696.1116697.

[22] T. Wei, K. Wu, R. Karri, A. Orailoglu, Fault tolerant quantum cellular array (qca)design using triple modular redundancy with shifted operands, in: Proceed-ings of the ASP-DAC 2005 Asia and South Pacific Design Automation Con-ference, vol. 2, 2005, pp. 1192–1195. http://dx.doi.org/10.1109/ASPDAC.2005.1466555.

[23] X. Ma, F. Lombardi, Fault tolerant schemes for qca systems, in: IEEE Interna-tional Symposium on Defect and Fault Tolerance of VLSI Systems, DFTVS'08,2008, pp. 236–244, http://dx.doi.org/10.1109/DFT.2008.12.

[24] B. Sen, M. Dutta, M. Goswami, B.K. Sikdar, Modular design of testable rever-sible {ALU} by {QCA} multiplexer with increase in programmability, Micro-electron. J. 45 (2014) 1522–1532, http://dx.doi.org/10.1016/j.mejo.2014.08.012.

[25] M. Dalui, B. Sen, B.K. Sikdar, Fault tolerant qca logic design with coupledmajority–minority gate, Int. J. Comput. Appl. 1 (2010) 81–87, 10.5120/596-645.

[26] R. Farazkish, A new quantum-dot cellular automata fault-tolerant five-inputmajority gate, J. Nanopart. Res. 16 (2014), http://dx.doi.org/10.1007/s11051-014-2259-8.

[27] A. Roohi, R.F. DeMara, N. Khoshavi, Design and evaluation of an ultra-area-efficient fault-tolerant {QCA} full adder, Microelectron. J. 46 (2015) 531–542,http://dx.doi.org/10.1016/j.mejo.2015.03.023.

[28] R. Farazkish, A new quantum-dot cellular automata fault-tolerant full-adder, J.Comput. Electron. 14 (2015) 506–514, http://dx.doi.org/10.1007/s10825-015-0668-2.

[30] A. Chaudhary, D.Z. Chen, X.S. Hu, M.T. Niemier, R. Ravichandran, K. Whitton,Fabricatable interconnect and molecular qca circuits, IEEE Trans. CAD Integr.Circuits Syst. 26 (2007) 1978–1991, http://dx.doi.org/10.1109/TCAD.2007.906467.

[31] S.-H. Shin, J.-C. Jeon, K.-Y. Yoo, Wire-crossing technique on quantum-dot cel-lular automata, in: 2nd International Conference on Next Generation Com-puter Information Technology (NGCIT 2013), pp. 52–57, 2013.

[32] J. Von Neumann, Probabilistic logics and the synthesis of reliable organismsfrom unreliable components, Autom. Stud. (1956) 43–98, [online available:http://www.urut.ch/pdfsPublic/vN_prob_logics.pdf].

[33] J.R. Heath, P.J. Kuekes, G.S. Snider, R.S. Williams, A defect-tolerant computerarchitecture: opportunities for nanotechnology, Science 280 (1998)1716–1721, http://dx.doi.org/10.1126/science.280.5370.1716.

[34] C.S. Lent, P.D. Tougaw, W. Porod, G.H. Bernstein, Quantum cellular automata,Nanotechnology 4 (1993) 49–57, [online available: http://stacks.iop.org/0957-4484/4/i=1/a=004].

[35] G. Toth, Correlation and coherence in quantum-dot cellular automata (Ph.D.thesis), University of Notre Dame, 2000.

[36] A. Fijany, B. Toomarian, New design for quantum dots cellular automata toobtain fault tolerant logic gates, Int. J. Nanopart. Res. 3 (2001) 27–37, http://dx.doi.org/10.1007/s11051-014-2259-8.

[37] S. Angizi, K. Navi, S. Sayedsalehi, A.H. Navin, Efficient quantum dot cellularautomata memory architectures based on the new wiring approach, J. Com-put. Theor. Nanosci. 11 (2014) 2318–2328, http://dx.doi.org/10.1166/jctn.2014.3646.

[38] R. Farazkish, S. Sayedsalehi, K. Navi, Novel design for quantum dots cellularautomata to obtain fault-tolerant majority gate, J. Nanotechnol. 2012 (2010)1–8, http://dx.doi.org/10.1155/2012/943406.

[39] M. Crocker, M. Niemier, X.S. Hu, M. Lieberman, Molecular qca design withchemically reasonable constraints, J. Emerg. Technol. Comput. Syst. 4 (2008)9:1–9:21, http://dx.doi.org/10.1145/1350763.1350769.

[40] M.B. Tahoori, J. Huang, M. Momenzadeh, F. Lombardi, Testing of quantumcellular automata, IEEE Trans. Nanotechnol. 3 (2004) 432–442, http://dx.doi.org/10.1109/TNANO.2004.834169.

[41] J. Han, E. Boykin, H. Chen, J. Liang, J. Fortes, On the reliability of computationalstructures using majority logic, IEEE Trans. Nanotechnol. 10 (2011) 1099–1112,http://dx.doi.org/10.1109/DSN.2005.83.

[42] F. Karim, M. Ottavi, H. Hashempour, V. Vankamamidi, K. Walus, A. Ivanov,F. Lombardi, Modeling and evaluating errors due to random clock shifts inquantum-dot cellular automata circuits, J. Electron. Test. 25 (2009) 55–66,http://dx.doi.org/10.1007/s10836-008-5088-9.

[43] R. Devadoss, K. Paul, M. Balakrishnan, Coplanar qca crossovers, Electron. Lett.45 (2009) 1234–1235, http://dx.doi.org/10.1049/el.2009.2819.