Elsevier Editorial System(tm) for Nuclear

Inst. and Methods in Physics Research, A

Manuscript Draft

Manuscript Number:

Title: A 15 GSa/s, 1.5 GHz Bandwidth Waveform Digitizing ASIC

Article Type: Research Paper

Section/Category: Electronics

Keywords: Waveform sampling; ASIC; Integrated Circuit; Analog-to-Digital;

Switched Capacitor Array

Corresponding Author: Mr. Eric Oberla,

Corresponding Author's Institution:

First Author: Eric Oberla

Order of Authors: Eric Oberla; Henry Frisch; Hervé Grabas; Jean-Francois

Genat; Kurtis Nishimura; Gary Varner

Abstract: The PSEC4 custom integrated circuit was designed for the

recording of fast waveforms for use in large-area time-of-flight detector

systems. The ASIC has been fabricated using the IBM-8RF 0.13 μm CMOS

process. On each of 6 analog channels, PSEC4 employs a switched

capacitor array (SCA) 256 samples deep, a ramp-compare ADC with 10.5~bits

of effective resolution, and a serial data readout with the capability of

region-of-interest windowing to reduce dead time. The sampling rate can

be adjusted between 4 and 15 Gigasamples/second [GSa/s] on all channels

and is servo-controlled on-chip with a low-jitter delay-locked loop

(DLL). The input signals are passively coupled on-chip with a -3 dB

analog bandwidth of 1.5 GHz. The power consumption in quiescent sampling

mode is less than 50 mW/chip; at a sustained trigger and readout rate of

50 kHz the chip

draws 100 mW. After fixed-pattern pedestal subtraction, the uncorrected

differential non-linearity is 0.15%

over an 800 mV dynamic range. With a linearity correction, a full 1 V

dynamic range is available. The sampling timebase has a fixed-pattern

non-linearity with an RMS of 13%, which can be calibrated for precision

waveform feature extraction and picosecond-level timing resolution.

The first experimental application to the front-end readout of large-area

Micro-Channel Plate (MCP) photodetectors is presented.

THE UNIVERSITY OF CHICAGO

THE ENRICO FERMI INSTITUTE

5640 SOUTH ELLIS AVENUE

CHICAGO · ILLINOIS 60637

phone: (773) 795-3342

March 26, 2013

Dr. W. BarlettaCoordinating EditorNuclear Instruments and Methods in Physics Research Section AMassachusetts Institute of TechnologyCambridge, MA, USA

Dear Dr. Barletta:

This is the cover letter with the items requested by Elsevier for themanuscript “A 15 GSa/s, 1.5 GHz Bandwidth Waveform Digitizing ASIC”. Wethank you in advance for your time and effort.

To our knowledge we do not require any special considerations.A brief research background: This paper covers the architecture and per-

formance of PSEC4, a custom-designed 15 Gigasample/second [GSa/s] waveformsampling and digitizing ASIC. This compact ‘oscilloscope-on-a-chip’ was fabri-cated in the 0.13 µm CMOS technology and was designed for the recording oftransient waveforms with baseband signal bandwidths up to 1.5 GHz.

The design of PSEC4 was part of the LAPPD effort to develop very fast,large-area photodetectors [1]. The LAPPD MCP-PMT is a 20×20 cm2 (8×8 in2)hermetically packaged photodetector with a 30 channel RF microstrip anodesignal pick-off [2]. PSEC4 will be used as the front-end readout ASIC for theinitial MCP-PMTs deployed in test-beam experiments.

The Corresponding Author is:Eric OberlaEnrico Fermi InstituteACC 1235640 S. Ellis AveChicago, IL USAejo@uchicago.edu

Sincerely,

Eric Oberla

Cover Letter

References

[1] The Large-Area Picosecond Photo-Detectors Project web page:<http://psec.uchicago.edu>

[2] H. Grabas, R. Obaid, E. Oberla, H. Frisch, et. al., “RF Strip-Line Anodes forPsec Large-Area MCP-based Photodetectors”, to be published Nucl. Instr.Meth. A (2013).

A 15 GSa/s, 1.5 GHz Bandwidth Waveform Digitizing ASIC

Eric Oberlaa, Herve Grabasa,1, Jean-Francois Genata,2, Henry Frischa, Kurtis Nishimurab,3, Gary Varnerb

aEnrico Fermi Institute, University of Chicago; 5640 S. Ellis Ave., Chicago IL, 60637bUniversity of Hawai’i at Manoa; Watanabe Hall, 2505 Correa Rd., Honolulu HA

Abstract

The PSEC4 custom integrated circuit was designed for the recording of fast waveforms for use in large-

area time-of-flight detector systems. The ASIC has been fabricated using the IBM-8RF 0.13 µm CMOS

process. On each of 6 analog channels, PSEC4 employs a switched capacitor array (SCA) 256 samples deep,

a ramp-compare ADC with 10.5 bits of effective resolution, and a serial data readout with the capability

of region-of-interest windowing to reduce dead time. The sampling rate can be adjusted between 4 and

15 Gigasamples/second [GSa/s] on all channels and is servo-controlled on-chip with a low-jitter delay-locked

loop (DLL). The input signals are passively coupled on-chip with a -3 dB analog bandwidth of 1.5 GHz. The

power consumption in quiescent sampling mode is less than 50 mW/chip; at a sustained trigger and readout

rate of 50 kHz the chip draws 100 mW. After fixed-pattern pedestal subtraction, the uncorrected differential

non-linearity is 0.15% over an 800 mV dynamic range. With a linearity correction, a full 1 V dynamic

range is available. The sampling timebase has a fixed-pattern non-linearity with an RMS of 13%, which

can be calibrated for precision waveform feature extraction and picosecond-level timing resolution. The first

experimental application to the front-end readout of large-area Micro-Channel Plate (MCP) photodetectors

is presented.

Keywords:

Waveform sampling, ASIC, Integrated Circuit, Analog-to-Digital, Switched Capacitor Array

1. Introduction1

We describe the design and performance of2

PSEC4, a ≥10 Gigasample/second [GSa/s] wave-3

form sampling and digitizing Application Spe-4

cific Integrated Circuit (ASIC) fabricated in the5

IBM-8RF 0.13 µm complementary metal-oxide-6

semiconductor (CMOS) technology. This compact7

‘oscilloscope-on-a-chip’ is designed for the recording8

1Present address, CEA/IRFU/SEDI; CEN Saclay-Bat141 F-91191 Gif-sur-Yvette CEDEX, France

2Present address, LPNHE, CNRS/IN2P3, UniversitesPierre et Marie Curie and Denis Diderot, T12 RC, 4 PlaceJussieu 75252 Paris CEDEX 05, France

3Present address, SLAC National Accelerator Labora-tory, 2575 Sand Hill Road, Menlo Park, CA 94025

of radio-frequency (RF) transient waveforms with9

signal bandwidths between 100 MHz and 1.5 GHz.10

1.1. Background11

The detection of discrete photons and high-12

energy particles is the basis of a wide range of13

commercial and scientific applications. In many of14

these applications, the relative arrival time of an15

incident photon or particle is best measured by ex-16

tracting features from the full waveform at the de-17

tector output [1, 2]. Additional benefits of front-end18

waveform sampling include the detection of pile-19

up events and the ability to filter noise or poorly20

formed pulses.21

For recording ‘snapshots’ of transient waveforms,22

Preprint submitted to elsevier March 26, 2013

*ManuscriptClick here to view linked References

switched capacitor array (SCA) analog memories23

can be used to sample a limited time-window at a24

relatively high rate, but with a latency-cost of a25

slower readout speed [3, 4]. These devices are well26

suited for triggered-event applications, as in many27

high energy physics experiments, in which some28

dead-time can be afforded on each channel. With29

modern CMOS integrated circuit design, these SCA30

sampling chips may be compact, low power, and31

have a relatively low cost per channel [4].32

Over the last decade, sampling rates in SCA33

waveform sampling ASICs have been pushed to sev-34

eral GSa/s with analog bandwidths of several hun-35

dred MHz [5]. As a scalable front-end readout36

option coupled with the advantages of waveform37

sampling, these ASICs have been used in a wide38

range of experiments; such as high-energy physics39

colliders [6], gamma-ray astronomy [7, 8], high-40

energy neutrino detection [9, 10], and rare decay41

searches [11, 12].42

1.2. Motivation43

A natural extension to the existing waveform44

sampling ASICs is to push design parameters that45

are inherently fabrication technology limited. Pa-46

rameters such as sampling rate and analog band-47

width are of particular interest considering the48

fast risetimes (τ r ∼ 60-500 ps) and pulse widths49

(FWHM ∼ 200 ps - 1 ns) of commercially available50

micro-channel plate (MCP) and silicon photomul-51

tipliers [13, 14]. These and other fast photo-optical52

or RF devices require electronics matched to speed53

of the signals.54

The timing resolution of discrete waveform sam-55

pling is intuitively dependent on three primary fac-56

tors as described by Ritt4 [15]:57

σt ∝τr

(SNR)√Nsamples

(1)58

where SNR is the signal-to-noise ratio of the pulse,59

τ r is the 10-90% rise-time of the pulse, and Nsamples60

is the number of independent samples on the rising61

4Assuming Shannon-Nyquist is fulfilled

edge within time τ r. The motivation for oversam-62

pling above the Nyquist limit is that errors due to63

uncorrelated noise, caused both by random time64

jitter and charge fluctuations, are reduced by in-65

creasing the rising-edge sample size. Accordingly,66

in order to preserve the timing properties of analog67

signals from a fast detector, the waveform record-68

ing electronics should 1) be low-noise, 2) match the69

signal bandwidth, and 3) have a reasonably fast70

sampling rate.71

1.3. Towards 0.13 µm CMOS72

The well-known advantages of reduced transistor73

feature size include higher clock speeds, greater cir-74

cuit density, lower parasitic capacitances, and lower75

power dissipation per circuit [16]. The sampling76

rate and analog bandwidth of waveform sampling77

ASICs, which depend on clock speeds, parasitic ca-78

pacitances, and interconnect lengths, are directly79

enhanced by moving to a smaller CMOS technology.80

Designing in a smaller technology also allows clock-81

ing of an on-chip analog-to-digital converter (ADC)82

at a faster rate, reducing the chip dead-time.83

With the advantages of reduced transistor feature84

sizes also comes increasingly challenging analog de-85

sign issues. One issue is the increase of leakage86

current. Leakage is enhanced by decreased source-87

drain channel lengths, causing subthreshold leakage88

(VGS < VTH), and decreased gate-oxide thickness,89

which promotes gate-oxide tunneling [17]. Effects90

of leakage include increased quiescent power dissi-91

pation and potential non-linear effects when storing92

analog voltages.93

Another design issue of deeper sub-micron tech-94

nologies is the reduced dynamic range [17]. The95

available voltage range is given by (VDD-VTH),96

where VDD is the supply voltage and VTH is97

the threshold, or ‘turn-on’, voltage for a given98

transistor. For technologies above 0.1 µm, the99

(VDD-VTH) range is decreased with downscaled100

feature sizes to reduce high-field effects in the gate-101

oxide [17]. In the 0.13 µm CMOS process, the sup-102

ply voltage VDD is 1.2 V and the values of VTH103

2

Figure 1: Photograph of the fabricated PSEC4 die. The chipdimensions are 4×4.2 mm2.

range from 0.42 V for a minimum-size transistor104

(gate length 120 nm) to roughly 0.2 V for a large105

transistor (5 µm) [18, 19].106

The potential of waveform sampling design in107

0.13 µm CMOS was shown with two previous108

ASICs. A waveform sampling prototype achieved a109

sampling rate of 15 GSa/s and showed the possibil-110

ity of analog bandwidths above 1 GHz [20]. Leak-111

age and dynamic range studies were also performed112

with this chip. In a separate 0.13 µm ASIC, fab-113

ricated as a test-structure chip, a 25 GSa/s sam-114

pling rate rate was achieved using low VTH transis-115

tors [21]. The performance and limitations of these116

chips led to the optimized design of the PSEC4117

waveform digitizing ASIC. The fabricated PSEC4118

die is shown in Figure 1.119

In this paper, we describe the PSEC4 architec-120

ture (§2), experimental performance (§3), and a121

first application to the front-end readout of large-122

area, picosecond resolution photodetectors (§4).123

2. Architecture124

An overview of the PSEC4 architecture and func-125

tionality is shown in Figure 2. For clarity, this block126

diagram shows one of six identical signal channels.127

A PSEC4 channel is a linear array of 256 sample128

points and a threshold-level trigger discriminator.129

Each sample point in the array is made from a130

switched capacitor sampling cell and an integrated131

ADC circuit as shown in Figure 3.132

To operate the chip, a field-programmable gate133

array (FPGA) is used to provide timing control,134

clock generation, readout addressing, data manage-135

ment, and general configurations to the ASIC. Sev-136

eral analog voltage controls are also required for137

operation, and are provided by commercial digital-138

to-analog converter (DAC) chips.139

Further details of the chip architecture, includ-140

ing timing generation (§2.1) sampling and trigger-141

ing (§2.2), analog-to-digital conversion (§2.3) , and142

data readout (§2.4), are outlined in the following143

sections.144

2.1. Timing Generation145

The sampling signals are generated with a 256-146

stage Voltage-Controlled Delay Line (VCDL), in147

which the individual stage time delay is adjustable148

by two complementary voltage controls. Each stage149

in the VCDL is an RC delay element made from a150

CMOS current-starved inverter. The inverse of the151

time delay between stages sets the sampling rate.152

Rates of up to 17 GSa/s are possible with PSEC4153

as shown in Figure 4. The stability of the sam-154

pling rate is negatively correlated with the slope155

magnitude as the VCDL becomes increasingly sen-156

sitive to noise. The slowest stable sampling rate is157

∼4 GSa/s.158

A ‘write strobe’ signal is sent from each stage159

of the VCDL to the corresponding sampling cell in160

each channel. The write strobe passes the VCDL-161

generated sampling rate to the sample-and-hold162

switch of the cell as shown in Figure 3. To allow163

the sample cell enough time to fully charge or dis-164

charge when sampling, the write strobe is extended165

to a fixed duration of 8× the individual VCDL de-166

lay stage. In sampling mode, a block of 8 adjacent167

SCA sampling cells are continuously tracking the168

3

Figure 2: A block diagram of PSEC4 functionality. The RF-input signal is AC coupled and terminated in 50Ω off-chip. Thedigital signals (listed on right) are interfaced with an FPGA for PSEC4 control. A 40 MHz write clock is fed to the chip andup-converted to ∼10 GSa/s with a 256-stage voltage-controlled delay line (VCDL). A ‘write strobe’ signal is sent from eachstage of the VCDL to the corresponding sampling cell in each channel. The write strobe passes the VCDL-generated samplingrate to the sample-and-hold switches of each SCA cell. Each cell is made from a switched capacitor sampling cell and integratedADC register, as shown in Figure 3. The trigger signal ultimately comes from the FPGA, in which sampling on every channelis halted and all analog samples are digitized. The on-chip ramp-compare ADC is run with a global analog ramp generatorand 1 GHz clock that are distributed to each cell. Once digitized, the addressed data are serially sent off-chip on a 12-bit busclocked at up to 80 MHz.

ADC Clock Read_enableV_ramp

12 bit register

C_sample

T1

T2

(~1 GHz)Write Strobe

Trigger

V_in

Data_out<12..1>

V_ped

+

−

Figure 3: Simplified schematic of the ‘vertically integrated’ PSEC4 cell structure. The sampling cell input, Vin, is tied to theon-chip 50Ω input microstrip line. Transistors T1 and T2 form a dual-CMOS write switch that facilitates the sample-and-holdof Vin on Csample, a 20 fF capacitance referenced to V ped. The switch is toggled by the VCDL write strobe while sampling(Figure 2) or a ASIC-global trigger signal when an event is to be digitized. When the ADC is initiated, a global 0.0-1.2 Vanalog voltage ramp is sent to all comparators, which digitizes the voltage on Csample using a fast ADC clock and 12-bitregister. To send the digital data off-chip, the register is addressed using Read enable.

4

input signal.169

To servo-control the VCDL at a specified sam-170

pling rate and to compensate for temperature ef-171

fects and power supply variations, the VCDL can172

be delay-locked on chip. The VCDL forms a delay-173

locked loop (DLL) when this servo-controlled feed-174

back is enabled. The servo-control circuit is made175

of a dual phase comparator and charge pump circuit176

to lock both the rising and falling edges of the write177

clock at a fixed one-cycle latency [22]. A loop-filter178

capacitor is installed externally to tune the DLL179

stability.180

With this DLL architecture, a write clock with181

frequency fin is provided to the chip, and the182

sampling is started automatically after a locking183

time of several seconds. The nominal sampling184

rate in GSa/s is set by 0.256·fin [MHz], and the185

sampling buffer depth in nanoseconds is given by186

103/fin [MHz−1]. A limitation of the PSEC4 de-187

sign is the relatively small recording depth at high188

sampling rates due to the buffer size of 256 samples.189

2.2. Sampling and Triggering190

A single-ended, 256-cell SCA was designed and191

implemented on each channel of PSEC4. Each sam-192

pling cell circuit is made from a dual CMOS write193

switch and a metal-insulator-metal sampling capac-194

itor as shown in Figure 3. With layout parasitics,195

this capacitance is effectively 20 fF. During sam-196

pling, the write switch is toggled by the write strobe197

from the VCDL. To record an event, an external198

trigger, typically from an FPGA, overrides the sam-199

pling and opens all write switches, holding the ana-200

log voltages on the capacitor for the ADC duration201

(≤4 µs).202

The PSEC4 has the capability to output a203

threshold-level trigger bit on each channel. The in-204

ternal trigger is made from a fast comparator, which205

is referenced to an external threshold level, and dig-206

ital logic to latch and reset the trigger circuit. To207

form a PSEC4 trigger, the self-trigger bits are sent208

to the FPGA, which returns a global trigger signal209

back to the chip. Triggering interrupts the sampling210

on every channel, and is held until the selected data211

are digitized and read out.212

2.3. ADC213

Digital conversion of the sampled waveforms is214

done on-chip with a single ramp-compare ADC that215

is parallelized over the entire ASIC5. Each sam-216

ple cell has a dedicated comparator and 12 bit217

register as shown in Figure 3. In this architec-218

ture, the comparison between each sampled voltage219

(Vsample) and a global ramping voltage (Vramp),220

controls the clock enable of a 12-bit register. When221

Vramp > Vsample, the register clocking is disabled,222

and the 12-bit word, which has been encoded by the223

ADC clock frequency and the ramp duration below224

Vsample, is latched and ready for readout.225

Embedded in each channel is a 5-stage ring oscil-226

lator that generates a fast digital ADC clock, ad-227

justable between 200 MHz and 1.4 GHz. The ADC228

conversion time, power consumption, and resolu-229

tion may be configured by adjusting the ramp slope230

or by tuning the ring oscillator frequency.231

2.4. Readout232

The serial data readout of the register bits is per-233

formed using a shift register ‘token’ architecture,234

in which a read enable pulse is passed sequentu-235

ally along the ADC register array. To reduce the236

chip readout latency, a limited selection of PSEC4’s237

1536 registers can be read out. Readout address-238

ing is done by selecting the channel number and a239

block of 64 cells. While not completely random ac-240

cess, this scheme permits a considerable reduction241

in dead time. At a maximum rate of 80 MHz, the242

readout time is 0.8 µs per 64-cell block.243

The readout latency is typically the largest con-244

tributor to the dead-time of the chip. The ADC245

conversion time also adds up to 4 µs of latency246

per triggered event. These two factors limit the247

sustained trigger rate to ∼200 kHz/channel or248

∼50 kHz/chip.249

5An overview of this ADC architecture can be found inreference [23].

5

2

4

6

8

10

12

14

16

18

20

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

Sa

mp

ling

Ra

te [

GS

a/s

]

Voltage Control [V]

MeasuredFit to DataSimulated

Figure 4: Sampling rate as a function of VCDL voltage control. Good agreement is shown between post layout simulation andactual values. Rates up to 17 GSa/s are achieved with the free-running PSEC4 VCDL. When operating the VCDL withoutfeedback, the control voltage is explicitly set and the sampling rate is given by 17.7 (1 − 0.018 exp(5.91 · Vcontrol)) [GSa/s].Typically, the servo-locking will be enabled and the VCDL is run as a delay-locked loop (DLL). In this case, the sampling rateis automatically set by the input write clock frequency.

Figure 5: The PSEC4 evaluation board. The board uses a Cyclone III Altera FPGA (EP3C25Q240) and a USB 2.0 PCinterface. Custom firmware and acquisition software were developed for overall board control. The board uses +5 V power anddraws <500 mA, either from a DC supply or the USB interface.

3. Performance250

Measurements of the PSEC4 performance have251

been made with several chips on custom evalu-252

ation boards shown in Figure 5. The sampling253

rate was fixed at a nominal rate of 10.24 GSa/s.254

Here we report on bench measurements of lin-255

earity (§3.1), analog leakage (§3.2), noise (§3.3),256

power (§3.4), frequency response (§3.5), sampling257

calibrations (§3.6), and waveform timing (§3.7). A258

summary table of the PSEC4 performance is shown259

in §3.8.260

3.1. Linearity and Dynamic Range261

The input dynamic range is limited by the 1.2 V262

core voltage of the 0.13 µm CMOS process [18]. To263

enable the recording of signals with pedestal levels264

that exceed this range, the input is AC coupled and265

a DC offset is added to the 50 Ω termination. This266

is shown in the Figure 2 block diagram, in which267

6

-20

0

20

0 0.2 0.4 0.6 0.8 1 1.2Input Voltage [V]

Fit Residuals 0

500

1000

1500

2000

2500

3000

3500

4000

PS

EC

4 o

utp

ut [A

DC

counts

]

Raw Pedestal ScanLinear fit

Figure 6: DC response of the device running in 12 bit mode.The upper plot shows raw data (red points) and a linear fitover the the same dynamic range (dotted black line, slope of4 counts/mV). The fit residuals are shown in the lower plot.A differential non-linearity (DNL) of better than 0.15% isobserved for input signals between 0.2 V and 1.0 V beforeany calibrations.

the DC offset is designated by V ped. The offset268

level is tuned to match the input signal dynamic269

range to that of PSEC4.270

The PSEC4 response to a linear pedestal scan271

is shown in Figure 6. A dynamic range of 1 V272

is shown, as input signals between 100 mV and273

1.1 V are fully coded with 12 bits. A differential274

non-linearity (DNL) of better than 0.15% is shown275

for most of that range. The linearity and dynamic276

range near the voltage rails are limited due to tran-277

sistor threshold issues in the comparator circuit.278

The DNL of this response, shown by the linear fit279

residuals in Figure 6, can be corrected by creating280

an ADC count-to-voltage look-up-table (LUT) that281

maps the input voltage to the PSEC4 output code.282

The raw PSEC4 data is converted to voltage and283

‘linearized’ using this LUT.284

3.2. Sample Leakage285

When triggered, the write switch on each cell286

is opened and the sampled voltage is held at287

high impedance on the 20 fF capacitor (Fig. 3).288

Two charge leakage pathways are present: 1)289

sub-threshold conduction through the write switch290

[V]ped - VsampleV-0.6 -0.4 -0.2 0 0.2 0.4 0.6

Leak

age

Cur

rent

[fA

]

-400

-300

-200

-100

0

100

200

300

400

500

SPICE simulation:

Write Switch Leakage

NFET tunneling

Figure 7: The PSEC4 leakage as a function of input voltage.The measured leakage is shown by the histogrammed datapoints. Results from a 0.13 µm CMOS spice simulationare also included. The simulation shows the leakage currentcontributions from 1) sub-threshold conduction through thedisengaged write switch; and 2) gate-oxide tunneling fromthe NFET in the input stage of the comparator.

formed by transistors T1 and T2; and 2) gate-oxide291

tunneling through the NFET at the comparator in-292

put. The observable leakage current is the sum of293

these two effects.294

To measure the leakage current, a 300 ns wide,295

variable-level pulse was sent to a single PSEC4296

channel. Since the sampling window is 25 ns, each297

SCA cell sampled the transient level. After trigger-298

ing, the sampled transient voltage was repeatedly299

digitized at 1 ms intervals and the change in voltage300

on the capacitor was recorded over a 10 ms storage-301

time.302

The PSEC4 leakage current as a function of input303

voltage over the full 1 V dynamic range is shown in304

Figure 7. A pedestal level VDD/2 = 0.6 V was set305

at the input. The measured leakage is shown in the306

2-D histogram. A large spread (RMS ∼70 fA) is307

seen at each voltage level. Results from a 0.13 µm308

CMOS spice simulation show that the write-switch309

leakage is the dominant pathway. A small amount310

(≤100 fA) of NFET gate-oxide tunneling is also311

consistent with the data.312

In normal operation, the ADC is started imme-313

diately after a trigger is registered. In this case,314

the analog voltage hold time is limited to the ADC315

7

<Noise>Entries 89244Mean 0.02628RMS 0.7038

Readout [mV]-4 -2 0 2 4 6 8

Cou

nts/

(0.2

5 m

V)

0

2

4

6

8

10

12

310×

<Noise>Entries 89244Mean 0.02628RMS 0.7038

Fit Parameters:mean: 0.03 mVsigma: 0.68 mV

Figure 8: A PSEC4 baseline readout showing the electronicnoise. The data are recorded from single channel after offsetcorrection. The RMS value of ∼700 µV is representative ofthe electronics inherent noise on all channels.

conversion time. Assuming a constant current, the316

leakage-induced voltage change is given by317

∆V =Ileakage ∆t

Csample(2)318

where ∆t is the ADC conversion time. With the319

maximum leakage current of ±500 fA and a con-320

version time of 4 µs, ∆V is ±100 µV. This value is321

at least 5× lower than the electronics noise.322

3.3. Noise323

After fixed-pattern pedestal correction and324

event-by-event baseline subtraction, which removes325

low-frequency noise contributions, the PSEC4 elec-326

tronic noise is measured to be ∼700 µV RMS on327

all channels as shown in Figure 8. The noise figure328

is dominated by broadband thermal noise on the329

20 fF sampling capacitor, which contributes 450 µV330

(RMS 60 electrons) at 300 K. Other noise sources331

include the ADC ramp generator and comparator.332

The noise corresponds to roughly 3 least significant333

bits (LSBs), reducing the effective resolution of the334

device to 10.5 bits over the dynamic range.335

3.4. Power336

The power consumption is dominated by the337

ADC, which simultaneously clocks 1536 ripple338

150

200

250

300

350

200 400 600 800 1000 1200 1400

PS

EC

4 P

ow

er

[mW

]

ADC Clock Freq. [MHz]

0.14 mW/MHz

Figure 9: The total PSEC4 power as a function of the ADCclock rate. Clock rates between 200 MHz and 1.4 GHz can beselected based on the power budget and targeted ADC speedand resolution. When the ADC is not running, the quiescent(continuous sampling) power consumption is ∼40 mW perchip.

counters and several hundred large digital buffers at339

up to 1.4 GHz. The total power draw per chip as a340

function of ADC clock rate is shown in Figure 9. To341

reduce the steady state power consumption and to342

separate the chip’s digital processes from the ana-343

log sampling, the ADC is only run after a trigger is344

sent to the chip. Without a trigger, the quiescent345

power consumption is ∼40 mW per chip, including346

the locked VCDL sampling at 10.24 GSa/s and the347

current biases of all the comparators.348

Initiating the ADC with a clock rate of 1 GHz349

causes the power draw to increase from 40 mW to350

300 mW within a few nanoseconds. To mitigate351

high-frequency power supply fluctuations when352

switching on the ADC, several ‘large’ (2 pF) de-353

coupling capacitors were placed on-chip near the354

ADC. These capacitors, in addition with the close-355

proximity evaluation board decoupling capacitors356

(∼0.1-10 µF), prevent power supply transients from357

impairing chip performance.358

At the maximum PSEC4 sustained trigger rate359

of 50 kHz, in which the ADC is running 20% of360

the time, a maximum average power of 100 mW is361

drawn per chip.362

8

-5

-4

-3

-2

-1

0

1

2

3

4

0.1 1.0 2.0

Am

plit

ude [dB

]

Frequency [GHz]

500mVpp (-2dBm)50mVpp (-22dBm)

Figure 10: The PSEC4 frequency response. The -3 dB ana-log bandwidth is 1.5 GHz. The positive resonance above1 GHz is due to bondwire inductance of the signal wires inthe chip package. Similar responses are shown for large andsmall sinusoidal inputs.

-50

-45

-40

-35

-30

-25

-20

0.1 1.0 2.0

Cro

ssta

lk A

mplit

ude [dB

]

Frequency [GHz]

Ch. 1Ch. 2Ch. 4Ch. 5Ch. 6

Figure 11: The channel-to-channel crosstalk as a function offrequency. Channel 3 was driven with a -2 dBm sinusoudalinput. Adjacent channels see a maximum of -20 dB crosstalkat 1.1 GHz. The electronic noise floor is -50 dB for reference.

3.5. Frequency Response363

The target analog bandwidth for the PSEC4 de-364

sign was ≥1 GHz. The bandwidth is limited by the365

parasitic input capacitance (Cin), which drops the366

input impedance at high frequencies6 as367

|Zin| =Rterm√

1 + ω2 Rterm Cin

(3)368

where Rterm is an external 50 Ω termination re-369

sistor. Accordingly, the expected half-power band-370

width is given by:371

f3dB =1

2π Rterm Cin(4)372

The extracted Cin from post-layout studies was373

∼2 pF, projecting a -3 dB bandwidth of 1.5 GHz374

which corresponds to the measured value shown in375

Figure 10. The chip package-to-die bondwire in-376

ductance gives a resonance in the response above377

1 GHz that distorts signal content at these frequen-378

cies. An external filter may be added to flatten the379

response.380

The measured channel-to-channel crosstalk is381

-25 dB below 1 GHz for all channels as shown in382

Figure 11. For frequencies less then 700 MHz, this383

drops to better than -40 dB. The primary crosstalk384

mechanism is thought to be the mutual induc-385

tance between signal bondwires in the chip pack-386

age. High frequency substrate coupling on the chip387

or crosstalk between input traces on the PSEC4388

evaluation board may also contribute.389

3.6. Sampling Calibration390

For precision waveform feature extraction, both391

the overall time-base of the VCDL and the cell-to-392

cell time step variations must be calibrated. With393

the rate-locking DLL, the overall PSEC4 sampling394

time base is stably servo-controlled at a default rate395

of 10.24 GSa/s. The time-base calibration of the396

individual 256 delay stages, which vary due to cell-397

to-cell transistor size mismatches in the VCDL, is398

the next task. Since this is a fixed-pattern varia-399

tion, the time-base calibration is typically a one-400

time measurement.401

6This ignores negligible contributions to the impedancedue to the sampling cell input coupling. The write switchon-resistance (≤ 4 kΩ over the full dynamic range) and the20 fF sampling capacitance introduce a pole at ≥2 GHz.

9

Time calibrationEntries 256Mean 0.09601RMS 0.01202

Time-base calibration constants [ns]0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2

Ent

ries/

(6.5

ps)

0

10

20

30

40

50

Time calibrationEntries 256Mean 0.09601RMS 0.01202

Fit Parameters:

mean: 95.9 ps

sigma: 12.1 ps

PSEC4 sampling cell no.0 50 100 150 200 250

Tim

e [n

s]

-0.05

0

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4Time-base:

DNLINL

DLL wrap-around offset

Figure 12: LEFT: A histogram of the extracted time-base calibration constants (∆t). These values are calculated using thezero-crossing technique and are used to correct the sampling time-base of the PSEC4 chip. A 13% spread in the ∆t values isobserved. The average sampling rate over these cells is found to be 10.4 GSa/s, slightly higher than the nominal value.RIGHT: The differential (DNL) and integral non-linearity (INL) of the PSEC4 time-base. The extracted ∆t’s are comparedto an ideally linear time-base with equal time-steps per sample point. The large time-step at the first sample bin is causedby a fixed DLL latency when wrapping the sampling from the last cell to the first. With the servo-locking DLL the INL isconstrained to be zero at the last cell.

Time [ns]0 2 4 6 8 10 12 14 16 18 20

Am

plitu

de [m

V]

-200

-150

-100

-50

0

50

100

150

200

Figure 13: A 10.24 GSa/s capture of a 400 MHz sine input is shown (black dots) after linearity correction and time-basecalibration. A fit (red dotted line) is applied to the data.

The brute force ‘zero-crossing’ time-base cali-402

bration method is employed [24]. This technique403

counts the number of times a sine wave input404

crosses zero voltage at each sample cell. With405

enough statistics, the corrected time per cell is ex-406

tracted from the number of zero-crossings (Nzeros)407

using408

< ∆t >=Tinput < Nzeros >

2Nevents(5)409

where Tinput is the period of the input and Nevents410

is the number of digitized sine waveforms. A typi-411

cal PSEC4 time-base calibration uses 105 recorded412

events of 400 MHz sinusoids.413

The variation of the time-base sampling steps is414

∼13% as shown in the left plot of Figure 12. Due415

to a relatively large time step at the first cell, the416

average sampling rate over the remaining VCDL417

cells is 10.4 GSa/s, slightly higher than the nominal418

rate.419

The non-linearity of the PSEC4 time-base is420

shown in the right plot of Figure 12. Each bin in421

the plot is indicative of the time-base step between422

10

Time [ns]0 2 4 6 8 10

Am

plitu

de [V

]

0

0.05

0.1

0.15

0.2

0.25 Rising-edge Fit:

/ndf: 19.5/212χ: 5.591 ns0t

: 537 psσ

t_diffEntries 1595Mean 200.1RMS 2.579

Time Difference [ps]190 195 200 205 210 215 220 225

Ent

ries/

750

fem

tose

cond

s

0

20

40

60

80

100

120t_diff

Entries 1595Mean 200.1RMS 2.579

Fit Parameters:

mean: 200.0 ps

sigma: 2.55 ps

Figure 14: LEFT: An example PSEC4 digitized pulse and off-line fit that was used for the timing resolution measurement.A 1.25 ns FWHM Gaussian pulse was split to two channels of the chip. The digitized waveform (black dots) is captured at10.24 GSa/s and is shown after applying the time-base calibration constants. The timing was extracted using a Gaussian-functional fit to the leading edge of the waveform (red line). A voltage error of 1.5 mV, which corresponds to the RMS baselinefluctuations, is included on each sample point of the waveform to obtain the χ2 value. RIGHT: The PSEC4 2-channel timingresolution. The timing resolution is 2.6 ps RMS when running at 10.24 GSa/s. A fast pulse was split to two channels of thechip, as shown on the left. The time difference between the two channels was extracted by fitting the digitized waveforms.

the binned cell and its preceding neighbor cell. The423

relatively large DNL in the first bin, which corre-424

sponds to the delay between the last (cell 256) and425

first sample cells, is caused by a fixed DLL latency426

when wrapping the sampling from the last cell to427

the first.428

A digitized 400 MHz sine wave is shown in Fig-429

ure 13 after applying the time-base calibration con-430

stants.431

3.7. Waveform Timing432

The effective timing resolution of a single mea-433

surement is calculated by waveform feature extrac-434

tion after linearity and time-base calibration. A435

0.5 Vpp, 1.25 ns FWHM Gaussian pulse was cre-436

ated using a 10 GSa/s arbitrary waveform gener-437

ator (Tektronix AWG5104). The output of the438

AWG was sent to 2 channels of the ASIC us-439

ing a broadband-RF 50/50 splitter (Mini-Circuits440

ZFRSC-42). This pulse, as recorded by a channel441

of PSEC4, is shown on the left in Figure 14.442

A least-squares Gaussian functional fit is per-443

formed to the leading edge of the pulse. The pulse444

times from both channels are extracted from the fit445

and are subtracted on an event-by-event basis. A446

2-channel RMS timing resolution of 2.6 ps is found447

as shown on the right in Figure 14.448

3.8. Performance Summary449

The performance and key architecture parame-450

ters of PSEC4 are summarized in Table 1.451

4. Application to Large-Area Photodetec-452

tors453

The first application of PSEC4 is the front-end454

waveform digitization of large-area photodetectors455

with picosecond-level time resolution [25, 26]. The456

LAPPD MCP-PMT is a 20×20 cm2 (8×8 in2) her-457

metically packaged photodetector with a 30 chan-458

nel RF microstrip anode signal pick-off [27]. The459

1-dimensional transmission line anode design is op-460

timized for precise spatial resolution with an effe-461

cient use of electronics channels. The (x,y) position462

of the incident particle or photon is extracted by us-463

ing the differential times of waveforms at the two464

microstrip terminals (x), and the relative charge465

captured on neighboring strips (y) [27]. Waveform466

sampling, matched to the MCP bandwidth, allows467

11

Table 1: PSEC4 architecture parameters and measured performance results.

Parameter Value Comment

Channels 6 die size constraintSampling Rate 4-15 GSa/s servo-locked on-chipSamples/channel 256 25 ns recording window at 10.24 GSa/sAnalog Bandwidth 1.6 GHz ∼2.5 dB distortion at 1.3 GHzCrosstalk 7% max. over bandwidth

<1% typical for signals <800 MHzNoise 700 µV RMS (typical). RF-shielded enclosure.Effective ADC Resolution 10.5 bits 12 bits loggedADC time 4 µs max. 12 bits logged at 1 GHz clock speed

250 ns min. 8-bits logged at 1 GHzADC clock speed 1.4 GHz max.Dynamic Range 1 V after linearity correctionReadout time 0.8n µs n is number of 64-cell blocks to read (n = 24 for entire chip)Sustained Trigger Rate 50 kHz max. per chip. Limited by [ADC time + Readout time]−1

Power Consumption 100 mW max. average powerCore Voltage 1.2 V 0.13 µm CMOS standard

Figure 15: The initial PSEC4 application: a high-channel density waveform digitization of a large-area Micro-Channel Plate(MCP) RF microstip anode. The two readout boards use five PSEC4 ASICs each to digitize 30 anode strips at both terminals.The active area of the central detector is 20×20 cm2.

12

Time [ns]5 10 15 20 25

Vol

tage

[V]

-0.35

-0.3

-0.25

-0.2

-0.15

-0.1

-0.05

0

0.05

0.1

Figure 16: PSEC4 digitization of 20×20 cm2 MCP pulses.The pulses are recorded on both ends of a microstrip anodeusing the PSEC4 evaluation board (Fig. 5). The amplitudecorresponds to ∼10 photo-electrons.

for both the time and charge extraction to deter-468

mine the (x,y) position, in addition to the time-of-469

arrival and energy of the incident particle or pho-470

ton.471

A compact, detector integrated data acquisition472

(DAQ) system was designed for the LAPPD MCP-473

PMTs. The front-end microstrip anode waveform474

digitization board shown in Figure 15, in which five475

PSEC4 ASICS are used on each end to capture476

waveforms from all 30 strips. The board maintains477

a 50Ω impedance between the anode output and478

the chip input. The back-end FPGA and clock-479

distribution boards (not shown) can be mechani-480

cally mounted behind the LAPPD MCP-PMT.481

The ‘single-tile’ readout configuration is shown482

in Figure 15. Typical MCP pulses from this config-483

uration, as recorded by PSEC4, are shown in Fig-484

ure 16. Depending on the event rate of the applica-485

tion, the detector active area may be increased by486

serially connecting the microstrip anodes of adja-487

cent LAPPD MCP tiles using a common front-end488

PSEC4 digitizer board and DAQ system [27].489

5. Conclusion490

We have described the architecture and perfor-491

mance of the PSEC4 waveform digitzing ASIC.492

The advantages of implementing waveform sam-493

pling IC design in a deeper sub-micron process are494

shown, with measured sampling rates of up to 15495

GSa/s and analog bandwidths of 1.5 GHz. Poten-496

tial 0.13 µm design issues, such as leakage and dy-497

namic range, were optimized and provide a 1 V498

dynamic range with sub-mV electronics noise. A499

one-time timebase calibration is required to get pre-500

cise waveform timing with 2-3 picosecond resolu-501

tion. The first application of the PSEC4 ASIC is502

the compact, low-power front-end waveform sam-503

pling of LAPPD MCP-PMTs.504

6. Acknowledgements505

We thank Mircea Bogdan, Fukun Tang, Mark Za-506

skowski, and Mary Heintz for their strong support507

in the Electronics Development Group of the En-508

rico Fermi Institute. Stefan Ritt, Eric Delagnes,509

and Dominique Breton provided invaluable guid-510

ance and advice on SCA chips.511

This work is supported by the Department of En-512

ergy, Contract No. DE-AC02-06CH11357, and the513

National Science Foundation, Grant No. PHY-106514

601 4.515

References516

[1] J.-F. Genat, G. Varner, F. Tang, H.J. Frisch, “Signal517

Processing for Pico-second Resolution Timing Measure-518

ments”, Nucl. Instr. Meth. A 607 (2009) 387-393.519

[2] D. Breton, E. Delagnes, J. Maalmi, K. Nishimura, L.L.520

Ruckman, G. Varner, J. Va’vra, “High Resolution Pho-521

ton Timing with MCP-PMTs: A Comparison of Com-522

mercial Constant Franction Discriminator (CFD) with523

ASIC-based waveform digitizers TARGET and Wave-524

Catcher”, Nucl. Instr. Meth A 629 (2011) 123-132.525

[3] S. Kleinfelder, “Development of a Switched Capacitor526

Based Multi-Channel Transient Waveform Recording527

Integrated Circuit”, IEEE Trans. Nucl. Sci. 35, (1988)528

151-154.529

[4] G. Haller, B. Wooley, “A 700 MHz Switched Capacitor530

Analog Waveform Sampling Circuit”, SLAC-PUB-6414531

(1993).532

[5] S. Ritt, “Gigahertz Waveform Sampling: An Overview533

and Outlook”, 12th Pisa Meeting on Advanced Detec-534

tors, 23d May 2012.535

13

[6] G.S. Varner, L.L Ruckman, J.W. Nam, R.J. Nichol,536

J. Cao, P.W. Gorham, M. Wilcox, “The Large Ana-537

log Bandwidth Recorder and Digitizer With Ordered538

Readout (LABRADOR) ASIC”, Nucl. Instr. Meth. A539

583 (2007) 447-460.540

[7] E. Delagnes, Y. Degerli, P. Goret, P. Nayman, F. Tou-541

ssenel, P. Vincent, “SAM: A new GHz sampling ASIC542

for the H.E.S.S.-II Front-End Electronics”, Nucl. Instr.543

Meth. A 567 (2006) 21-26.544

[8] K. Bechtol, S. Funk, A. Okumra, L. Ruckman, A.545

simons, H. Tajima, J. Vandenbroucke, G. Varner,546

“TARGET: A Multi-Channel Digitizer Chip for Very-547

High-Energy Gamma-Ray Telescopes”, J. Astroparticle548

Physics 36 (2012) 156-165.549

[9] S. Kleinfelder, “Gigahertz Waveform Sampling and Dig-550

itization Circuit Design and Implementation”, IEEE551

Trans. Nucl. Sci. 50, (2003) 955-962.552

[10] G.S. Varner, P. Gorham, J. Cao, “Monolithic Multi-553

Channel GSa/s Transient Waveform Recorder for Mea-554

suring Radio Emissions from High Energy Particle Cas-555

cades”, Proc. SPIE Int. Soc. Opt. Eng 4858 (2003) 31.556

[11] C. Broennimann, R. Horisberger, R. Schnyder, “The557

Domino Sampling Chip: A 1.2 GHz Waveform Sam-558

pling CMOS Chip”, Nucl. Instr. Meth. A 420 (1999)559

264-269.560

[12] S. Ritt, “The DRS Chip: Cheap Waveform Digitization561

in the GHz Range”, Nucl. Instr. Meth. A 518 (2004)562

470-471.563

[13] J. Milnes, J. Howorth, “Picosecond Time Response564

Characteristics of Micro-channel Plate PMT Detec-565

tors”, SPIE USE, V. 8 5580 (2004) 89-100.566

[14] P. Eraerds, M. Legre, A. Rochas, H. Zbinden, N. Gisin,567

“SiPM for fast Photon-Counting and Multiphoton De-568

tection”, Optics Express, Vol. 15 (2007) 14539-14549.569

[15] S. Ritt, “The Role of Analog Bandwidth and570

S/N in Timing”, talk at The Factors that571

Limit Timing Resolution in Photodetectors,572

<http://psec.uchicago.edu/workshops/573

fast timing conf 2011/>, University of Chicago, Apr574

2011.575

[16] R.H. Dennard, F. H. Gaennsslen, H. N. Yu, V.L576

Rideout, E. Bassous, A.R. LeBlanc, “Design of Ion-577

Implemented MOSFETs with Very Small Physical Di-578

mensions,” IEEE J. Solid-State Circuits SC-9 (1974)579

256-268.580

[17] Y. Taur et. al., “CMOS Scaling into the Nanometer581

Regime”, Proc. IEEE. Vol. 85, No. 4, (1997) 486-504.582

[18] IBM Corporation, “CMRF8SF Model Reference583

Guide”, V.1.4.0.10 (2008).584

[19] The MOSIS Service. Wafer Electrical Test Data and585

SPICE Model Parameters. Run: V18B. Available586

on-line (accessed 4 Feb. 2013):587

<http:://www.mosis.com/pages/Technical/588

Testdata/ibm-013-prm>589

[20] E. Oberla, H. Grabas, M. Bogdan, H. Frisch, J.-F.590

Genat, K. Nishimura, G. Varner, A. Wong, “A 4-591

Channel Waveform Sampling ASIC in 0.13 µm CMOS592

for Front-End Readout of Large-Area Micro-Channel593

Plate Detectors”, Physics Procedia 37 (2012) 1690-594

1698.595

[21] M. Cooney, M. Andrew, K. Nishimura, L. Ruckman,596

G. Varner, H. Grabas, E. Oberla, J.-F. Genat, “Multi-597

purpose Test Structures and Process Characterization598

using 0.13 µm CMOS: The CHAMP ASIC”, Physics599

Procedia 37 (2012) 1699-1706.600

[22] H. Chang et al., “A Wide-Range Delay-Locked Loop601

With a Fixed Latency of One Clock Cycle”, IEEE J.602

Solid-State Circuits 37 (2002) 1021-1027.603

[23] O. Milgrome, S. Kleinfelder, M. Levi, “A 12 Bit Analog604

to Digital Converter for VLSI Applications in Nuclear605

Science”, IEEE Trans. Nucl. Sci. 39, (1992) 771-775.606

[24] K. Nishimura, A. Romero-Wolf, “A Correlation-Based607

Timing Calibration & Diagnostic Technique for Fast608

Digitization ASICs”, Physics Procedia 37 (2012) 1707-609

1714.610

[25] The Large-Area Picosecond Photo-Detectors Project611

web page: <http://psec.uchicago.edu>612

[26] M. Wetstein, B. Adams, A. Elagin, J. Elam, H. Frisch,613

Z. Insepov, V. Ivanov, S. Jokela, A. Mane, R. Obaid, I.614

Veryovkin, A. Vostrikov, R. Wagner, A. Zinovev et al.,615

to be submitted to Nucl. Instr. Meth. A (2013).616

[27] H. Grabas, R. Obaid, E. Oberla, H. Frisch, et. al., “RF617

Strip-Line Anodes for Psec Large-Area MCP-based618

Photodetectors”, to be published Nucl. Instr. Meth. A619

(2013).620

14