ELG 2135 ELECTRONICS I SECOND CHAPTER ...rhabash/ELG2135Ch2.pdfThe first operational amplifier was...

ELG 2135

ELECTRONICS I

SECOND CHAPTER:

OPERATIONAL AMPLIFIERS

Session Winter 2003

Dr. M. YAGOUB

Second Chapter: Operational amplifiers II - 2_________________________________________________________________________________________________________________________________________________________

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After reviewing the basic aspects of amplifiers, we will introduce a circuit representing the behavior

of an ideal amplifier, namely the operational amplifier that is also commonly called the Op Amp.

A – INTRODUCTION

I - History

The first operational amplifier was in the form of an integrated circuit called the « µA 709 ». This

unit was made up a relatively large number of transistors and resistors all on the same chip.

It is a very popular circuit because of its versatility (we can do almost anything with op amps) as we

can see later.

II – The op amp terminals

From a signal point of view, the op amp has three terminals: two input terminals and one output

terminal (figure II-1).

Moreover, as amplifiers require dc power to operate, we add two additional terminals named « 4 »

and « 5 » for the positive (V+) and negative (V-) dc voltage respectively (figure II-2):

⇔

1 __

2 +3

1 __

2 +3

4

5

V+

V-

1 __

2 +3

4

5

Figure II-1

Figure II-2


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The two dc power supplies as batteries with a common ground, which is the reference grounding

point in op-amp circuits.

B – IDEAL OPERATIONAL AMPLIFIERS

The op amp is designed to sense the difference between the voltage signals v1 and v2 applied at its

two input terminals that is the quantity v2 - v1 multiplied by the amplification factor A. The output

voltage at the third terminal is then

( )123 vvAvvo −== (1)

Note:

1 - Quantity v1 means that the voltage v1 is applied between terminal 1 and ground.

2 - If terminal 1 is grounded, we obtain a usual amplifier of input signal v1 and gain A.

The ideal op amp is assumed to have any input current: i1 = i2 = 0. This assumption implies that the

input impedance of an ideal operational amplifier is infinite.

As the output voltage is given by (1), it is independent of the output current delivered to a load.

Then, the output impedance of an ideal operational amplifier is supposed to be zero. These

conclusions lead to the following equivalent circuit (figure II-3):

Figure II-3


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Note:

1 - Output voltage vo is in phase with v2 (the two voltages have the same sign) and out of phase with

v1 (opposite signs). For this reason, we call:

Terminal 1: Inverting input terminal (distinguished by a “-“ sign)

Terminal 2: Noninverting input terminal (distinguished by a “+“ sign)

2 - The op amp responds only to the difference signal. This property is called the common-mode

rejection. The ideal op amp has infinite common-mode rejection.

3 - The op amp is then a differential-input, single ended-output amplifier

4 - Furthermore, gain A is called the differential gain or the open-loop gain.

5 - Gain A remains constant down zero frequency up to infinite frequency. That means an infinite

bandwidth for the ideal op amp.

C – INVERTING CONFIGURATION

I – Closed loop gain

By considering the following amplifier configuration (figure II-4),

Figure II-4


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we note that the resistance R2 is connected from the output terminal back to the inverting (or negative)

input terminal. We speak of R2 as applying negative feedback. In addition, R2 closes the loop around

the operational amplifier. We have then a closed-loop gain G:

i

ovv

G = (2)

Figure II-5-a shows the equivalent circuit of the inverting configuration.

Figure II-5


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If we assume that the output voltage is finite, then the voltage between the input terminals should be

negligibly small (because the gain A approaches infinity)

1212 0 vvA

vvv o ≈→≈=− (3)

We speak then of a “virtual short circuit” between the two input terminals or a “virtual ground”.

Here “virtual” means that there is no physical shorting wire between 1 and 2 (terminal 1 is virtually not

physically grounded). The current through R1 is then equal to the following relation

11

11 R

vR

vvi ii ≈

−= (4)

Note: This current cannot go to the op amp (infinite input impedance), so it will flow through R2 to the

low impedance terminal 3.

Applying Ohm’s law gives the output voltage

21

211 0 RRv

Rivv io −=−= (5)

Thus the closed loop gain is (figure II-5-b) :

1

2RR

vv

Gi

o −== (6)

Because of the minus sign, this gain is referred to the inverting configuration.

Note: The gain depends only on external passive components, i.e., resistances R1 and R2. So, we can

make the closed-loop gain as accurate as we want. We can start out with a very large gain A,

and then applying negative feedback to obtain the predictable gain R2/R1.


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II – Rigorous determination of the closed-loop gain

We obtained G using the assumption that the open-loop gain A is finite. Knowing that

A

vvv o=− 12 (7)

we can have a more rigorous relation for equation (3)

Av

v o−=1 (8)

The current through R1 can now be found from

( )11

1 RA/vv

RA/vv

i oioi +=

−−= (9)

and

21

21 RR

A/vvA

vRiA

vv oiooo

+−−=−−= (10)

The closed-loop gain is then equal to

( ) A/R/RR/R

vv

Gi

o

12

1211 ++

−== (11)

It is obvious that if A is infinite, G approaches the ideal value expressed in relation (6). In other

words, relation (11) can be replaced by relation (6) if

ARR

<<+1

21 (12)


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III – Input and output resistances

Assuming an ideal op amp with infinite open-loop gain, the input resistance of the closed-loop-

inverting amplifier is (figure II-5-a)

111

RR/v

viv

Ri

iii === (13)

Thus to make Ri high, we should select a high value for R1. However, if the required gain R2/R1 is

also high, then R2 could become impracticably large. Since the output is A(v2 - v1) (Figure II-5-a),

the output resistance is zero. Putting all of the above together, we obtain the circuit shown in Figure II-

6 as the equivalent circuit model of the inverting amplifier configuration.

IV – Alternative circuit to increase the input resistance

A solution to avoid a small value of the input resistance is to consider the following circuit (Figure

II-7)

Figure II-6

Figure II-7


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Assuming

01 =−=A

vv o (14)

and a finite output voltage, we can write

111

121

0Rv

Rv

Rvv

ii iii =−

=−

== (15)

Thus the voltage vx at node x is equal to

ii

x vRRR

Rv

Rivv1

22

1221 0 −=−=−= (16)

This in turn enables us to find the current i3 :

iiixi v

RRR

Rv

RRR

Rv

Rv

Rviii

+=+=

−+=+=

31

2

131

2

131324

10(17)

and then the output voltage

iixo vRR

RR

RvRRRivv

+−−=−=

31

2

14

1

244

1 (18)

Thus the voltage gain is given by

+−−=

3

2

1

4

1

2 1RR

RR

RR

vv

i

o (19)

which can be written in the following form

++−=3

4

2

4

1

2 1RR

RR

RR

vv

i

o (20)


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So if an input resistance of 1 MΩ is desired, we select R1 = 1MΩ. Then, with the limitation of using

resistors no greater than 1MΩ, a value of R2 = 1MΩ gives a ratio of 1 for the first term in the gain

expression. To obtain a gain of –100, R4 = 1MΩ and R3 = 10.2 kΩ could be appropriate values.

This value is to compare with the one obtained using the configuration shown in Figure II-5-b. In

this case, with the same value of G (G = -100) and R1 (R1 = 1MΩ), the designer should select a

feedback resistance 100MΩ which is not practical.

D – OTHER APPLICATIONS OF THE INVERTING CONFIGURATION

I – Configuration with general impedances

Let us consider general impedances Z1(s) and Z2(s) instead of resistances R1 and R2 (s = jω) as

shown in figure II-8, we have the closed-loop transfer function

( )( )

( )( )sZsZ

tVtV

i

o

1

2−= (21)

II – Inverting integrator

By placing a capacitor in the feedback path (in place of Z2) and a resistance at the input (in place of

Z1), the circuit realizes the mathematical operation of integration (Figure II-9).

Figure II-8


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Let the input be vi(t), the virtual ground causes the input current to be equal to

( ) ( )R

tvti i=1 (22)

This current flows through the capacitor C. Thus

( ) ( )∫+=t

cc dttiC

Vtv0

11 (23)

where VC is the initial voltage on C at t = 0. As the output voltage is –vc(t) we have

( ) ( )∫−−=t

ico dttvRC

Vtv0

1 (24)

This relation shows that the output is proportional to the time-integral of the input, with Vc being

the initial condition of integration and CR the « integrator time constant ».

Note:

This circuit is also known as the Miller integrator.

The operation of the integrator circuit can be described in the frequency domain

( )( )

( )( ) RCjsRCR

sC/sZsZ

tVtV

i

oω

111

1

2 −=−=−=−= (25)

Figure II-9


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Magnitude and phase of this expression are then

=→=

RCVV

RCVV

dBi

o

i

oωω

1log20110 φ = + 90o (26)

The bode plot for the integrator magnitude resposne canbe obtained by noting that as ω double

(increase by an octave) the magnitude is halved (decreased by –6dB) (Figure II-10).

Thus the Bode plot is a straight line of slope –6dB/octave. This line intercepts the 0-dB line at

1dB 0 =→=i

o

dBi

oVV

VV

⇒RCint1

=ω (27)

which is the integrator frequency.

III – Alternative circuit to the integrator

We can observe that in dc (zero frequency) the magnitude is infinite. So the op amp is operating at

dc with an open loop (capacitor impedance is infinite at dc). This is a source of problem because anyt

tiny dc component inthe input source will theoritically produce an infinite output. Of course, the

ampligfier will saturate at a voltage close to the op amp positive or negative powwer supply.

Figure II-10


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As it is impossible to predict an input signal without any dc part (pure sine waveform) an alternative

circuit is required for the integrator. In order to limit the dc gain, a parallel resistance RF (Figure II-11)

is connected in parallel with the capacitor.

The dc gain will be then

RR

VV F

DCi

o −= (28)

Unfrtunatly, introducing the resistance will make the integrator not ideal. The transfer function is

now equivalent to that of a low pass filter with

CRFdB

13 −=ω (29)

Resistance RF should be selected as large as possible.

IV – Differentiator circuit

Interchanging the location of the capacitor and the resistor of the integrator circuit results in the

circuit in Figure II-12 which performs the mathematical function of differentiation.

Note: Here the term Differentiator means the derivation not the difference.

Figure II-11


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Considering Figure II-12, we have

( )dt

)t(vdRCtv i

o −= (30)

The frequency domain transfer function can be found as

( )( ) RCjsRCtVtV

i

o ω−=−= (31)

Magnitude and phase are

( )RCVV

RCVV

dBi

o

i

o ωω 10log20=→= φ = - 90o (32)

The Bode plot of the magnitude response can show that the magnitude doubles for an octave

increase in ω (Figure II-13).

Figure II-12

Figure II-13


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The RC product is the « differentiator time constant ».

Note I:

The differentiator circuit acts as a high pass filter.

Note II:

As for the ideal integrator, an ideal differentiator is unstable and impractical. Any variation of

the input voltage implies a line with a very high slope. An additional resistance is required to

reduce the “noise magnifier” characteristic of an ideal differentiator.

V – Weighted summer

Another application of the inverting configuration is the summer (Figure II-14).

In this circuit, we have a feed back resistance Rf and a number n of input signals each applied to a

corresponding resistor R1, …Rn. The corresponding currents are then

( ) ( ) ( ) ( )n

nn R

tvti,,

Rtvti == K

1

11 (33)

The input current is the sum of all these currents

( ) ( ) ( )tititi n++= K1 (34)

Thus, the output voltage is

( ) ( ) ( ) ffo RtiRtitv −=−= 0 (35)

Figure II-14


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Or:

( ) ( ) ( ) ( )

+++−= tv

RR

tvRR

tvRR

tv nn

fffo L2

21

1(36)

That is, the output voltage is a weighted sum of the input signals v1, …, vn. This is circuit is the

weighted summer where the weights are the resistances R1 to Rn.

E – NON INVERTING CONFIGURATION

If the input signal is applied directly to the positive input terminal of the op amp, we have the non-

inverting configuration (Figure II-15).

I – Input-output relationship

The gain A of the non-inverting configuration is

012 ==−A

vvv o (37)

The current flowing through the resistance R1 is

11 R

vi i= (38)

which is the same current for R2 (Figure II-16).

Figure II-15


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Thus:

+=

12 R

vRvv iio (39)

and

1

21RR

vv

Gi

o +==

+=→

1

21R

RRvv io (40)

We have a voltage divider. The gain is positive: it is the gain of the non-inverting configuration. The

input resistance is ideally infinite and the output resistance is zero. The equivalent circuit is shown in

Figure II-17.

Figure II-16

Figure II-17


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II – Rigorous determination of the closed-loop gain

Relation (40) has been obtained with the assumption that the gain A is infinite. If this gain is finite,

we have

( )( )

AR/R

R/R

ARR

RR

vv

Gi

o12

12

1

21

2

11

1

11

1

++

+=

++

+== (41)

The denominator is identical to that for the case of the inverting configuration (equation (11)). This

IS no coincidence; it is a result of the fact that both the inverting and the non-inverting configurations

have the same feed back loop. The numerators are different. The approximation between (40) and (41)

can be expressed as

1

21RRA +>> (42)

F – APPLICATIONS OF THE NON-INVERTING CONFIGURATION

I – Voltage follower

The property of high input impedance is a very desirable feature of the non-inverting configuration.

It enables using this circuit as a buffer amplifier to connect a source with a high impedance to a low

impedance load. Moreover, by setting

02 =R and ∞=1R (43)

we obtain a unity gain amplifier. This circuit is referred to as a voltage follower, since the output

“follows” the input with the properties

oi vv = ∞=inR 0=outR (44)


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Note:

Since the non-inverting configuration has a gain greater than or equal to unity, depending on the

choice of R2/R1, some prefer to call it “a follower with gain”.

Its configuration (Figure II-18-a) and equivalent electrical circuit (Figure II-18-b) are as follows:

II – Analog Voltmeter

Figure II-19 shows a circuit for an analog voltmeter of very high input resistance that uses an

inexpensive moving coil meter.

III – Difference amplifier

In order to obtain the difference between two signals (e.g., to compare a signal to a reference), we

can use a difference amplifier (Figure II-20).

Figure II-18

Figure II-19


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To apply superposition, we first reduce v2 to zero and then find the corresponding output voltage vo1.

Next, we reduce v1 to zero and evaluate vo2 (Figure II-21).

With v2 = 0 (Figure II-21-a), we have

11

21 v

RRvo −= (45)

Resistances R3 and R4 do not affect the gain expression since no current flows through either of

them. Thus, with v1 = 0 (Figure II-21-b), we have

+

+=

1

2

43

422 1

RR

RRRvvo (46)

Since R3 and R4 play a voltage divider, we recognize the non-inverting configuration.

Figure II-20

Figure II-21


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The superposition principle tells

++

+−=

+

++−=+=

43

1221

1

2

1

2

43

421

1

221 1

11R/RR/Rvv

RR

RR

RRRvv

RRvvv ooo (47)

thus the circuit is a difference amplifier because:

• if v1 = v2 = 0 we have vo = 0

• If we select:

3

4

1

2RR

RR

= (48)

the gain is equal to

( )121

2 vvRRvo −= (49)

However, for practical considerations, the condition (48) gives an alternative circuit (Figure II-22)

with

31 RR = and 42 RR = (50)

The input differential resistance is then defined as

ivvRin12 −

= (51)

Figure II-22


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Using the virtual short circuit, the above relation can be changed to

iRiRvv 1112 0 ++=− ⇒ 12RRin = (52)

Note that if the amplifier is required to have a large differential gain, then R1 will be relatively small

(equation (49)) and the input resistance will be correspondingly small (equation (52)). Difference

amplifiers are used mainly in the design of instrumentation systems.

IV – Instrumentation amplifier

Let us consider the case of a transducer that exhibits between each of the two wires and ground two

close signals (for example: v1 = 1V and v2 = 1.001V). In order to compare efficiently the small signal

difference, a usual circuit is not convenient (it is very difficult to detect efficiently a 1 mV voltage in a

1V voltage). The required circuit, known as the instrumentation amplifier, must reject the large

interference signal, which is common to the two wires (i.e., 1V) and amplify the small difference (or

differential) signal (Figure II-23).

For this circuit, we have

21d

cmv

Vv −= and22d

cmv

Vv += (53)

This situation denotes the common mode signal Vcm and the differential signal Vd:

( )V 20012 /.Vcm = and mV 1V 0010 == .vd (54)

Figure II-23


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V – Improved circuit for the instrumentation amplifier

As the instrumentation amplifier is deduced from the differentiator amplifier configuration, it

presents the same disadvantage namely a low input resistance and a gain that cannot be varied easily. A

much superior instrumentation amplifier circuit is shown in Figure II-24.

Figure II-24


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This circuit consists of two stages (Figure II-24-a). The first stage is formed by ideal op amps A1

and A2 and their associated resistors, and the second stage is formed by ideal op amp A3 together with

its four assiciated resistros. Analysis of the circuit (Figure II-24-b) shows that the current flowing

through R1 is identical to the one flowing through R2. Thus:

1

21R

vvi −= ⇒ ( ) ( ) ( )

1

212

1

211

1

21221 R

vvRR

vvRR

vvRvv oo−

+−

+−

=−

⇒ ( )211

221

21 vvRRvv oo −

+=− (55)

Then, the output voltage of the second stage is

( ) ( )121

2

3

421

3

4 21 vvRR

RRvv

RRv ooo −

+

=−

−= (56)

Thus, the instrumentation amplifier has a differential voltage gain

3

4

1

2

12

21RR

RR

vvvA o

d

+=

−= (57)

Moreover, if the two input voltages are identical (vd = 0), the output voltages of the two first op

amps are equal and give the following input common mode signal vcm

21 oocm vvv == (58)

Thus, if the second stage difference amplifier is properly balanced it will produce a zero poutput

voltage in response to vcm.

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