Elements of discrete devices synthesis (module T170M012) 2012 Kaunas university of technology...

Elements of discrete devices Elements of discrete devices synthesissynthesis

(modul(modulee T170M012) T170M012)

20201212

KaunKaunasas university of technologyuniversity of technologyEleElectronic and measurement systems dep.ctronic and measurement systems dep.

Doc. dr. Žilvinas NakutisDoc. dr. Žilvinas Nakutis

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Goal of the synthesisGoal of the synthesis

TranslTranslateate higher abstraction level higher abstraction level presentationpresentation ( (for example for example algoritmalgoritmicic) ) to to the lower abstraction level presentation the lower abstraction level presentation ((for example logic gatesfor example logic gates))

LogiLogicc s synthesisynthesis – RTL – RTL descriptiondescription (VHDL, (VHDL, Verilog) transformaVerilog) transformation to logic gatestion to logic gates

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Variety of logic device descriptionsVariety of logic device descriptions

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Digital logic synthesisDigital logic synthesisDigital logic synthesis is designing of logic gate circuit

according to the given logic expression or truth table.

Task:

Draw the circuit of the devices, described by the truth table

(Digital design with CPLD applications and VHDL, 2000 psl. 68).

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Sum-of-Products and Product-of-Sums forms

Product term is the member in logic equation representing logic multiplication of two or several signals, for example A & B.

Minterm is the member representing logic multiplication of all input signals or inverted input signals

Sum term is the member representing logic sum of two or several signals, for example A | B | D

Maxterm is the member representing logic sum of all input signals or inverted input signals

Sum-of-products (SOPSOP)

(A & B & C)+(!A & !B & C)+(A & B & !C)

Product-of-sums (POSPOS)

(A+B+C) & (A+!B+!C) & (A+B+!C)

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SSum of products um of products (SOP) (SOP) formform

Minterms Y=1

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Schematics from Schematics from SSum of products um of products formform

ALT

_IN

BU

F

not1

AND3

and1

AND3

and2

AND3

and3

OR3

or1

ALT

_IN

BU

F

not2

ALT

_IN

BU

F

not3

CBA

BCA

CBA

Y

ABC

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TaskTask: : synthesis of synthesis of XOR XOR andand NXOR NXOR gatesgates

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Product of sums Product of sums (POS)(POS) form form

Minterms !Y=1

Invert both sides and apply De Morgano rule

Task: Propose how to derive the POS form directly from truth table

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SumarySumary of of SOP SOP and and POS formPOS formss

Need to do reduction


Features of boolean algebraFeatures of boolean algebra

ComutativityComutativity::AA & B = B & A, & B = B & A, AA + B = B + A + B = B + A

Associativity:Associativity: ( (AA & B) & C = A & (B & C), & B) & C = A & (B & C), ( (AA + B) + C = A + (B + C), + B) + C = A + (B + C),

Distributivity:Distributivity: AA & (B + C) = A & B + A & C. & (B + C) = A & B + A & C.

Task: Check the associativity of the XOR (^) logic function.

Using features of boolean algebra SOP and POS form can be reduced in order to minimize number of needed gates.


Theorems of Boolean algebraTheorems of Boolean algebra

De Morgan tDe Morgan theoremsheorems

Other rulesOther rules


BBooleanoolean (bit) algeb (bit) algebaa t theoremsheorems


FormForms reduction using Karnaugh s reduction using Karnaugh mapsmaps

Karnaugh maps (K-maps) methods is used to generate optimized (simplified) logic expression from the truth table.

Karnaugh (French mathematitan Maurice Karnaugh) diagram (angl. Karnaugh map or K-map,KV-map (other inventor Edward W. Veitch)– is another form of truth table, where each combination of logic inputs (minterm) is represented by the corresponding cell.

Edward W. Veitch used the method in 1952, Maurice Karnaugh – in 1953.

Karno diagramos sudaromos taip, kad gretimuose jos kvadratėliuose skirtųsi tik vieno loginio kintamojo reikšmė, o visų kitų sutaptų.

Predko, Myke. Digital Electronics Demystified, McGraw-Hill, 2004 (Ebrary bibliotekoje)Predko, Myke. Digital Electronics Demystified, McGraw-Hill, 2004 (Ebrary bibliotekoje)

http://www.facstaff.bucknell.edu/mastascu/eLessonsHTML/Logic/Logic3.html


Key termsKey terms Karnaugh map A graphical tool for finding the maximum SOP or POS

simplification of a Boolean expression. A Karnaugh map works by arranging the terms of an expression in such a way that variables can be canceled by grouping minterms or maxterms.

Cell The smallest unit of a Karnaugh map, corresponding to one line of a truth table. The input variables are the cell’s coordinates, and the output variable is the cell’s contents.

Adjacent cell Two cells are adjacent if there is only one variable that is different between the coordinates of the two cells. For example, the cells for minterms ABC and ABC are adjacent.

Pair A group of two adjacent cells in a Karnaugh map. A pair cancels one variable in a K-map simplification.

Quad A group of four adjacent cells in a Karnaugh map. A quad cancels two variables in a K-map simplification.

Octet A group of eight adjacent cells in a Karnaugh map. An octet cancels three variables in a K-map simplification.


K-maps exampleK-maps exampleInitial function


Rules for finding Rules for finding circlecircles (contourss (contours))

1.1. One circle can include only the number multiple to 2One circle can include only the number multiple to 2nn adjacent adjacent cells cells ((for example for example 33 cells can not compose a circle cells can not compose a circle).). This way we This way we can circle 1, 2, 4, 8, etc. adjacent cells.can circle 1, 2, 4, 8, etc. adjacent cells.

NoteNote: : Adjacent cells are also those that are at the opposite sides Adjacent cells are also those that are at the opposite sides of the mapof the map..


Rules for finding Rules for finding circlecircles (2)s (2)

2.2. Circles may intersectCircles may intersect, , ii..ee. . one cell can be one cell can be included in to two or more circlesincluded in to two or more circles. . If there exists If there exists the circle containing only cells that are already the circle containing only cells that are already included in to other circles then this circle is included in to other circles then this circle is redundant and not needed for the following redundant and not needed for the following steps.steps.


Rules for finding Rules for finding circlecircles (3)s (3)

3.3. Start circling groups larger than 2. In the Start circling groups larger than 2. In the example bellow groups from 4=2example bellow groups from 4=22 2 are circled.are circled.


Rule for writing the optimized logic Rule for writing the optimized logic expression from expression from KK-map-map

Logic expression is derived in the Logic expression is derived in the SOPSOP from. from. Each product term corresponds to one circle in Each product term corresponds to one circle in the K-map.the K-map.

The product term corresponding the circle is The product term corresponding the circle is composed from input signals whose value are composed from input signals whose value are constant (0 or 1) in all the cells of the circleconstant (0 or 1) in all the cells of the circle. .

If the signal value is equal to 0 than inverted If the signal value is equal to 0 than inverted signal substituted in the expression; when the signal substituted in the expression; when the signal value is 1, then signal enters expression signal value is 1, then signal enters expression directly.directly.


Write the optimized logic Write the optimized logic expression from expression from KK-map (example)-map (example)

Y=(!B*C)+(B*!С) +(A*С) Y=A+C

Y=(!B*C)+(B*!С) +(A*!С)


KK-map application example-map application example


TaskTask No.No.1 1 (synthesis using (synthesis using KK-maps)-maps)

BCBC

AA

0000 0101 1111 1010

00 11 00 11 11

11 00 11 11 11

Y = (!A*!C) + (A*С) + B


TaskTask No.2No.2 (synthesis using (synthesis using KK--maps)maps)

CCDD

AABB

0000 0101 1111 1010

0000 11

0101 11 11 11

1111 11 11 11

1100 11 11

Y = (A*!B*D) + (B*!D) + C*D


KK-maps application with -maps application with don’t care outputdon’t care outputs s (denoted by X)(denoted by X)

BCBC

AA

0000 0101 1111 1010

00 00 00 11 00

11 11 11 11 XX

Y = (A*!B) + (B*С)

Y = (B*С) + A

Only cells with 1’s are circled

Cells with 1’s and X’s are circled

Note: Both equations are correct, but the second needs less gates for implementation


Disadvantages of K-mapsDisadvantages of K-maps

Suitable for manual optimization but hard Suitable for manual optimization but hard to implement as computer programto implement as computer program

Working manually with large K-maps Working manually with large K-maps typing errors can occur oftentyping errors can occur often

Suitable up to Suitable up to 6 6 input signalsinput signals, , practically practically usable up to usable up to 44 input signals input signals


Other algorithms for logic functions Other algorithms for logic functions minimizationminimization

Quine–McCluskey algoritQuine–McCluskey algorithhm (m (http://en.wikipedia.org/wiki/Quine-McCluskey_alhttp://en.wikipedia.org/wiki/Quine-McCluskey_algorithmgorithm):): Can be described mathematically in the way suitable Can be described mathematically in the way suitable

fro implementation in computer programfro implementation in computer program Suitable for small number of inputs/outputs because Suitable for small number of inputs/outputs because

computational requirements grow exponentially with computational requirements grow exponentially with the number of inputs/outputsthe number of inputs/outputs

Espresso heuristiEspresso heuristicc logi logicc minimiz minimizerer - de-facto - de-facto standarstandardd


Espresso heuristiEspresso heuristicc logi logicc minimizminimizerer

Introduced in 1980 in Introduced in 1980 in Brayton’Brayton’ss Berkeley universit Berkeley universityy It is a computer programIt is a computer program, , that utilizes heuristicthat utilizes heuristic

minimizaminimizationtion algori algorithmsthms The optimal minimization result is not guarateedThe optimal minimization result is not guarateed Computational requirements are much less compared to Computational requirements are much less compared to

other algorithmsother algorithms PraPracticaly no constraints on the numbercticaly no constraints on the number of of

inputs/outputsinputs/outputs. . The task was solved with several tens of The task was solved with several tens of ininputsputs/out/outputs.puts.

The circuit is mapped to (synthesized from) the selected The circuit is mapped to (synthesized from) the selected basic gates. Therefore, the method is well suited for basic gates. Therefore, the method is well suited for CPLD CPLD and and FPGA sFPGA synthesisynthesis

The aThe algoritlgorithhmm has many modifications has many modifications Implemented in many synthesis programsImplemented in many synthesis programs


Logic Friday – Logic Friday – free program for logic free program for logic synthesis based onsynthesis based on Espresso algorit Espresso algorithhmm

ExampleExample: : Truth Truth table of decoder table of decoder of 7-segment of 7-segment indicatorindicator


Selection of basic gatesSelection of basic gates

Wanted Wanted implementation implementation using using 2NAND2NAND andand NOTNOT gatesgates


SSynthesis result ynthesis result ((total total 30 30 gatesgates) )


Selection of other basic gatesSelection of other basic gates

Wanted Wanted implementation implementation using using 2NOR2NOR andand NOTNOT gatesgates


SSynthesis result ynthesis result ((total total 3366 gatesgates))


Multi-level sMulti-level synthesisynthesis

At the beginning synthesis tools design a At the beginning synthesis tools design a multilevel network from the Register-Transfer-multilevel network from the Register-Transfer-Level (RTL) descriptionLevel (RTL) description

The network is then optimized with the The network is then optimized with the technology independent approachtechnology independent approach

Finally, Finally, optimizoptimized logic expressions are ed logic expressions are mapped mapped to the circuit of logic gatesto the circuit of logic gates. . The mapping The mapping process encounters constraints concerning process encounters constraints concerning available gates (AND, OR, etc.) and available gates (AND, OR, etc.) and requirements of delays, power consumption, die requirements of delays, power consumption, die area, etcarea, etc..


SSynthesis for ynthesis for FPGAFPGA

Using Using multiplemultiplexorsxors Using Using Look Up TablesLook Up Tables (LUT) (LUT)


Logic synthesisLogic synthesis, , usingusing multiple multiplexorsxors (MUX)(MUX)

http://dropzone.tamu.edu/~wshi/475/MIT_Logic_Synthesis.pdf


Implementation of combinational Implementation of combinational logic using logic using MUXMUX


MultipleMultiplexors are universal devicesxors are universal devices


General General strustructure of MUXcture of MUX


Distributed decoding logicDistributed decoding logic

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