Electrostatic Discharge in Semiconductor Devices ... · Electrostatic Discharge in Semiconductor...

Electrostatic Discharge in SemiconductorDevices: Protection Techniques

JAMES E. VINSONAND J. J. LIOU, SENIOR MEMBER, IEEE

Invited Paper

Electrostatic discharges (ESDs) are everywhere—in our homesand businesses. Even the manufacturers of the electronics experi-ence ESD failures in their factories. Electronic devices are sensitiveto ESD. ESD results in failure of our computers, calculators, andcar phones. There are ways to protect these sensitive components.This paper looks at ESD protection from a two-pronged approach:reducing the likelihood of having an ESD event and improving therobustness of the devices themselves. The first approach focuses onreducing the amount of charge that is developed and controlling theredistribution of any charges that are developed. The second ap-proach reviews ways to improve the circuit robustness by improvingindividual circuit elements and by adding additional elements forcharge flow control and voltage clamping.

Keywords—Air ionizers, electrostatic discharge, ESD protection,ESD safe packaging, ESD safe workstation, floor finishes, inputprotection, static clamps, static dissipation, transient clamps.

I. INTRODUCTION

A. ESD Environment

Electrostatic discharge (ESD) is a subclass of the failurecauses known as electrical overstress (EOS). This class ap-plies electrical stimulus to a part outside of its designed tol-erance. ESD is a charge driven mechanism because the eventoccurs as a result of a charge imbalance [1]. The current in-duced by an ESD event balances the charge between two ob-jects. Our previous paper [2] gave an overview on the variousaspects of the ESD event. This paper will cover the specificsof protection techniques for preventing the ESD damagesin semiconductor devices. The ESD event has four majorstages: 1) charge generation; 2) charge transfer; 3) chargeconduction; and 4) charge-induced damage. ESD protectionlooks first to minimize the charge generation and slow the

Manuscript received February 26, 2000; revised June 20, 2000.J. E. Vinson is with Reliability Engineering, Intersil Corporation, Mel-

bourne, FL 32902 USA (e-mail: [email protected]).J. J. Liou is with the Electrical and Computer Engineering Department,

University of Central Florida, Orlando, FL 3286-2450 USA (e-mail:[email protected]).

Publisher Item Identifier S 0018-9219(00)10760-1.

charge transfer by controlling the environment where partsare handled and stored. The next aspect focuses on the circuitelements. Here, protection techniques look for ways to makethe individual elements more robust to the currents inducedwhile at the same time adding additional circuit elements toalter the conduction paths the charge takes through a circuit.

B. Real-World Events

The movement of objects generates ESD events by pro-viding the charging mechanism to produce a charge imbal-ance. No work area is immune to ESD events. The areas in-clude office environments, homes, laboratories, wafer fabri-cation facilities, and assembly/test sites. People as well asequipment generate ESD events. People are charged to highvoltages when they walk across the carpet. If a shock is feltfrom the ESD event, then the event had more than 3000 Vof potential [3]. Computer monitors in homes and officesare sources for inductive charging of parts and produce ESDevents in parts and equipment used around them [4].

These two sources of ESD generated events—peopleand equipment—produce current discharges that are quitedifferent in shape, peak current, and duration. In fact, ESDfrom a person can be very different based on the footwearworn, whether they are sitting or standing, and whether theyhave a metal object (tool) in their hand. Chase and Unger,in [5], showed that the selection of footwear defines theperson’s capacitance which ranged from 100 to 500 pF. If4 C were developed by the charging process, the inducedvoltage would range from 800 V for the 500-pF case to4000 V for the 100-pF case. The generated voltage is thedriving force behind the ESD event. The capacitance of aperson could double if they were sitting versus standing[6]. In addition to these inconsistencies, Calvinet al., in[7], showed that real-life ESD from people can consist ofmultiple discharges with each one progressively smaller inmagnitude. Holding a metal object during an ESD event canlower the series resistance of the discharge increasing thecurrent generated by the event [8]–[10]. The large variability

0018–9219/00$10.00 © 2000 IEEE

1878 PROCEEDINGS OF THE IEEE, VOL. 88, NO. 12, DECEMBER 2000

Fig. 1. Human body model ESD schematic diagram with parasitic elements.

Fig. 2. HBM ESD current waveforms resulting from parasitic elements.

in real-life ESD events makes it clear that a set of standardsis needed to judge a circuit’s response to ESD.

The integrated circuit industry has standardized on threebasic models related to ESD events. The models are basedon the charge storage location. These are: 1) the human bodymodel (HBM); 2) the machine model (MM); and 3) thecharged device model (CDM). Each model is described bystandards or draft standards. The ESD Association of Rome,NY, publishes one such group of standards. The three stan-dards are ESD STM5.1-1998 Sensitivity Testing—HumanBody Model (HBM)—Component Level; ESD S5.2-1999Sensitivity Testing—Machine Model (MM)—ComponentLevel; and ESD DS5.3—1996 Charged Device Model(CDM) Nonsocketed Mode—Component Level. Thesestandards were accurate at the time of this writing, but thereader should contact the ESD Association directly for thelatest revision. These methods of testing are intended tosimulate the average ESD event. As such, results obtainedusing these test methods are for comparisons of the robust-ness of various designs and not as an absolute measure of aparts capability in the real-world environment [11].

A schematic diagram of the HBM model is shown in Fig. 1[12], [13]. A plot of the current pulses as a function of theseelements is shown in Fig. 2. The inductance controls the risetime of the current pulse. The parasitic capacitor C1 providescurrent overshoot. The parasitic capacitor C2 can generate anadditional current pulse if the device under test (DUT) has aprotection element that suddenly changes state such as a sil-icon controlled rectifier (SCR). C2 represents the test boardcapacitance. Modern ESD testers are designed to minimizethese parasitic elements however many times the user designsand builds the DUT socket for their device. The user musttake care not to introduce stray impedance into the currentpath, or undesired results would occur.

C. Damage Caused

The currents induced by ESD are extremely high. In Fig. 2,the HBM-generated current peaks are in excess of 2 A. CDMand MM ESD generate currents even higher than this. Thesecurrent levels are in excess of the normal operational cur-rents. It is this current, directly or indirectly, that causes the

VINSON AND LIOU: ELECTROSTATIC DISCHARGE IN SEMICONDUCTOR DEVICES 1879

Fig. 3. Current-induced damage mechanisms.

physical damage observed in an ESD failure. Direct damageis caused by the power generated during the event. It meltsa section of the device causing failure. Indirectly, the currentgenerates a voltage by the ohmic resistance and nonlinearconduction along its path. Small voltages are generated whenjunctions are operated in forward bias mode, but large volt-ages are generated when they are in reverse bias mode. Thereverse bias conduction causes thermal damage at lower cur-rent levels because the power dissipation is higher from thehigher voltage across the junction. In addition, the voltagegenerated by this event weakens dielectrics by charge injec-tion. The limiting case for this charge injection is dielectricrupture.

Electrical testing of damaged parts shows increases inleakage current. The high currents generated during an

Fig. 4. Voltage-induced damage mechanisms.

ESD event damage electrical junctions as well as rupturedielectrics materials. The damage caused by ESD is a resultof five damage mechanisms. More than one damage mecha-nism may be active in a single failure. The current induceddamage mechanisms are thin-film fusing, filamentation,and junction spiking. The voltage-induced mechanisms arecharge injection and dielectric rupture. These mechanismsare illustrated schematically in Figs. 3 and 4 for the current-and voltage-induced mechanisms, respectively. An overviewof these damage mechanisms is presented here.

Thin-film resister damage is shown in Fig. 5. This is aphoto of the input structure on a silicon-on-sapphire (SOS)logic part. This photo illustrates a limitation of this design.The ESD current entered the bond pad and traveled throughthe resistor to the active device. The 90bend in the resistorcaused current crowding along the inside edge of this resistor.The temperature of the polysilicon rose by joule heating untilit melted and damaged the resistor. The inside edge no longerconducts. The resistor fused at this point. It is important toconsider the large currents present during an ESD event andlay the structure out to account for the larger currents. Sharpcorners should be avoided for both current paths and voltagefields. The sharp corners cause current crowding as well ashigh electric fields. High electric fields increase the proba-bility of having charge injection and dielectric rupture.

Filamentation damage is difficult to see in a transistor. It istypically seen based on the electrical signature. A degraded


Fig. 5. Blown polysilicon resistor.

– trace is observed resulting in a leaky junction. The ex-treme case of filamentation is junction spiking. This is illus-trated in the zener diode of Fig. 6. Fig. 6 shows the residualmetal left at the surface of the device. The device was thinnedfrom the backside and the silicon removed. This photo wastaken from the backside. This device experienced an EOSevent that allowed the metal to flow from the cathode con-tact to the anode contact shorting the zener diode.

The first voltage generated damage mechanisms is chargeinjection. This failure will not leave a physical damage siteobservable by typical deprocessing techniques. The chargestate of the dielectric material changes. These damage sitesare typically reversible by an unbiased bake or ultravioletlight irradiation. Both of these techniques allow the trappedcharge to be recombined. A junction with a trapped chargebecomes leaky. This may be mistaken for filamentationdamage. The main difference is that filamentation damagecannot be bake recovered. If significant charge is injected ata localized site, the dielectric will rupture. An oxide rupturesite is shown in Fig. 7. The rupture site was enhanced by asilicon etch, making it more clearly visible.

II. PROTECTIONREQUIREMENTS

A. The Need

A typical laboratory, manufacturing floor, or wafer fabri-cation area is capable of generating ESD voltages rangingfrom several hundreds of volts to well over 20 000 V if nocontrols are put in place. This is caused by the people andequipment used in the area as well as the atmospheric en-vironment of the lab. The people are charged as they walkacross the synthetic carpet and tile. Triboelectric chargingapplies a charge to their shoes, inducing a charge on theirbody. More details about the different charging mechanismis contained in our first paper [2]. The key aspect about theenvironment is the amount of humidity in the air. The amountof moisture in the air defines its electrical resistance. In dryareas, larger charges can build up before they are dissipated.This increases the risk of ESD damage. We have all experi-enced this in winter, when it is easier to shock yourself whilewalking across the carpet and touching a doorknob.

Fig. 6. Zener diode with junction spiking.

Fig. 7. Oxide rupture in capacitor oxide from ESD.

The manufacturing of integrated circuits consists of manysteps, but these can be grouped into functional areas. Thefirst grouping is wafer fabrication. Our earlier paper [2] de-scribed some of the effects charge generation and ESD canhave on an IC. These include particle contamination causedby electrostatic adhesion and damage to masks used to pro-duce the circuits as well as damage to the circuits themselves.The next grouping of operation is assembly. This functionalarea takes the wafers and separates the individual circuits,placing each of them in a package. Even in this operation,the die cannot escape large potential voltages. One exampleoccurs during the die separation process. Typically, a waferis placed on a sheet of sticky film and then the die are sawnapart. The sticky film is an insulator and does not contami-nate the wafer or die with foreign materials. The sticky natureof the film keeps the individual die in place during sawing.The die must now be removed from the tape, as shown inFig. 8. The film is stretched to provide larger separation be-tween the die and a vacuum wand selects the die for use.The removal process triboelectrifies the tape and die. Withoutproper protection, voltages in excess of 10 000 V can occur.The high voltages can attract particles to the die surface aswell as produce an ESD discharge event damaging the cir-cuit. Protection from these two phenomena comes in the formof air ionizers. These devices bathe the work area, the film,and the die with a balance of negative and positive ions toneutralize any developed charge.


Fig. 8. Die remove from film used during sawing.

It is important to compare the voltage levels generated byESD with the sensitivity levels of unprotected devices. Thiscomparison is necessary to determine the impact of ESD. Anexample of how sensitive unprotected devices are is found inthe MOSFET. The gate oxide thickness in these transistors isshrinking with each generation. A voltage of 10 V is capableof rupturing a 10-nm-thick gate oxide under dc conditions.In an transient condition this voltage will be slightly higher(15 V). In either condition, it is easy to see why handlingan unprotected device in an unprotected environment is verydangerous. The voltages produced are many orders of mag-nitude greater than the devices are able to handle. They canbe easily damaged. It is important to include ESD preventionin a work area and ESD protection on the circuit.

B. ESD is Probabilistic

ESD is a probabilistic event. The environment where theparts are handled has a probability of generating a voltage. Itcan be visualized as each voltage level has a probability ofbeing found at any point in time. This aspect is representedin Fig. 9 by curve “A.” Four key items define the probabilityof finding a selected voltage. The first is the type of pro-tection equipment present to control static charges. This in-cludes room ionizers, local ionizers, as well as ESD smocksand wrist straps. The second aspect of this probability is thereliability of the protection equipment. If any piece of pro-tection equipment fails the probability of having a highervoltage generated increases. The third aspect is the main-tenance practice to keep the protection equipment workingat peak performance. Some topical antistatic coating mustbe renewed on a periodic basis to keep them working well[14], [15]. If the maintenance intervals are too long, thenthe coating will not dissipate the charges as well and highervoltage levels will result. The last aspect determining theprobability, and the most important, is the employee’s dis-cipline to use the protection equipment properly. It does notmatter how well the equipment functions or how much equip-ment is present; if it is not used properly, then it cannot per-form its function.

Anotheraspect indefining theprobabilityofhavinganESDevent create a damaged unit is the ability of the device to with-standanESDeventofafixedmagnitude.ThisisshowninFig.9as curve “B.” As we saw earlier, an unprotected gate oxide isvery poor at protecting itself. A typical way of providing pro-tection for this sensitive element is to put an ESD protectionstructure in series with this gate oxide. The ESD event must

Fig. 9. ESD as a probability function.

travel through the protection structure to reach the gate oxide.The job of the protection structure is to clamp the voltage gen-erated by the charge as well as divert the charge away fromsensitive elements. The capability of this protection structureis the circuit’s first line of defense. Three items impede theprotection elements’ ability to provide a level of protection.The first is in its design. The design has a limitation of its own.It is only capable of providing protection up to a fixed levelbased on its size, layout, and schematic diagram. The secondis in the variability of the process. The last aspect is the de-fect density within the process. Process variability relates tohow well the electrical parameters of the protection circuit arecontrolled from one wafer fabrication lot to another and fromone wafer to another. Consistency is important for protectionelements. Each one must look like every other one. The bestprotection element can be rendered inoperative if a defect ispresent [2]. The current or voltage induced by an ESD eventis focused at the defect rather than dissipated uniformly. Thisfocused energy damages the device more quickly, resultingin a lower ESD threshold. Uniform electric fields and currentconduction are important for optimum protection.

TheshadedareaofFig.9iswheretheenvironmentpresentsavoltagethatishighenoughtocausedamagetotheproduct.Thisoverlap determines the probability of failure. It is difficult toquantify these two distribution functions. This discussion waspresented more as an aid to the reader to understanding thatboth aspects of protection must be addressed. The goal of anyprotection activity is to minimize the overlap area. The envi-ronment must be made safer for devices as well as the devicesthemselves must be made more robust to an ESD event. Re-moving charge-generation sources as well as providing a con-trolled discharge path for any charges that are developed im-prove the environment. Adding additional circuit elements todivert the charge in an ESD event as well as improving the un-protected elements’ ability to absorb charge improve the ESDthresholds of circuits. The administration of these two activ-ities is the topic of the next section, followed by a review ofenvironmental protection and circuit protection.

III. ESD ADMINISTRATION

Several authors [3], [16]–[22] have revealed how theyimplemented an ESD protection program at their facility.A common theme was that fixing the environment wasnot enough to ensure success. A successful ESD programrequires a two-prong approach to reduce the occurrenceof ESD events and to harden the circuits to these events.


Reducing ESD events includes reducing both the numberof occurrences and the magnitude of each occurrence. Theprobability discussion illustrates this. It was also clear fromthese papers that starting and sustaining an ESD programis not a small feat and should not be entered into without astrong commitment from the people that control the money,time, and equipment necessary to be successful. Welscheretal., in [3], detailed why ESD will be a continuing problem.They attribute it to the continuing advancement of tech-nology producing ever more sensitive components and theautomation of manufacturing coupled with the delay inproduction of ESD controls to keep up with this automation.There are three major aspects to a successful ESD protectionprogram. These are commitment, implementation, and con-tinuous improvement. Each of these aspects is continuouslyrenewed throughout the life of the program.

A. Organizational Commitment

The most important aspect of setting up and maintainingan ESD program is the commitment from management tosupport it and the employees to implement it. This includesall levels of management and all functional areas. Designengineering and manufacturing must agree. Areas have dif-ferent responsibility but the same goal—reduce ESD losses.ESD protection must involve all areas of the manufacturingprocess. The process starts with venders of raw materialsused in building the product and the supplies and equipmentthat must be used in its manufacture. It ends with the productbeing shipped to the customer and how he receives and usesthe product. A supportive organization is distinguished byhow the circuit and process designers view ESD circuit pro-tection. Supportive organizations have embraced the need forESD and are willing to abide by the rules and procedures setforth for ESD protection. They work closely with the ESDsteering committee to design-in protection to the circuit’sarchitecture. In this cooperative environment, the circuit isproperly protected. An unsupportive organization views ESDrequirements as an obstacle to overcome. They may make anattempt to include ESD protection, but it always takes up toomuch die area or impairs the circuit’s performance. Whenthe circuit does not meet the ESD objective the design teamdeclares it is “good enough” because it does not have time tofix it and make the market window. Many times the desire forquick revenues overrules the need to fix the circuit. Later inthe product’s life cycle, manufacturing is stuck with the yieldloss and cycle time stretchouts because of ESD failures. Thisresults in the customer’s poor image of the delivery processand the reliability/quality of the parts. In the customer’s fac-tory, the parts become harder to handle because of the extraESD safety precautions needed to keep the products fromfailing. Management’s support does not mean just lip ser-vice, but a commitment to supply the necessary personneland resources (including time) to get the job done correctly.It also means supporting the ESD team to ensure complianceto the plan when necessary.

Compliance to ESD requirements is a must. They are notESD suggestions, but ESD requirements. The need for ESDthreshold testing and design requirements must be formal-

ized into the product design process though a design spec-ification. This allows the requirements to be communicatedto all designers uniformly. To aid in meeting these require-ments, the designer must be given the tools and structures touse and simulate ESD events. These tools are used to predictESD thresholds in the design process. When a design doesnot meet the requirements, a corrective action plan should bedeveloped to address how the part can be improved. Failureanalysis (FA) is a necessary part of this process. FA showswhere the weak link is in the circuit. A workable action planwith defined dates of completion is required. This plan de-fines what has to be done, who is responsible, and when it isto be completed. It may also detail whether the part can besold as is and what extra measures are required to manufac-ture the units with minimum yield loss due to ESD damagewhile the fix is being developed.

Getting management approval may require a cost analysisor similar review to help them see the benefits of imple-menting an ESD program. These cost savings and benefitsincluded higher yield, improved outgoing quality, better cus-tomer satisfaction, and decreased field failures. Preliminaryfunding may be required to perform a site survey and com-petitive analysis to define what the cost and savings would beas well as determine what the competitors are doing. Duringthis review, it is important to document where improvementsare needed so this survey can be used as the basis of an imple-mentation plan. The survey should also measure the culturalaspects of the plan and gauge the attitude of the workforceand management about ESD and its impact. The cultural as-pects may be the most difficult factors to change.

To gain and maintain commitment from management andthe organization, it is important to communicate the bene-fits of having and maintaining a fully implemented ESD pro-gram. Payback and cost savings are key drivers for fundingany new project. A review of the failure causes both in thefactory and in the field can show a significant number of fail-ures attributed to ESD damage. Several authors have reportedgreater than 25% of all failures related to EOS damage [2],[23]. Reduction in these product losses and the subsequentrework savings are easily quantified. A more difficult costsavings to quantify is the loss of confidence from your cus-tomers because of ESD related failures. These failures causeshipment delays and reworks.

Routing reports showing ESD failures per factory turnsor a similar measure is a metric one could use to show im-provement with respect to ESD robustness. These metricsand other information help rally support for the ESD pro-gram and must be routinely communicated. The ESD pro-gram committee must continue selling itself and its impor-tance to the organization. Just like a company without ad-vertisements will lose market share, so will an ESD programlose support without feedback to its usefulness.

B. Implementation Plan

From the site survey, a detailed and exhaustive implemen-tation plan is devised. It is important not to develop a piece-meal plan. Each part of the ESD program is an element ofthe whole program and not a piece unto itself [19]. The pro-


gram is only as effective as its weakest piece [20]. It is im-portant to set realistic goals for the areas and for the circuits.The goals should be obtainable with the tool set available. Ifhigher threshold levels are required in a circuit to meet thevoltage levels present in an area, then improvements must bemade in the circuit protection. Research and development ofnew protection elements for designers to use must be a part ofthe implementation plan. If better protection is not possible,then that area must have more equipment and procedures inplace to lower the voltages generated. The goals may not bethe same for all functional areas as well as for all types ofcircuits. It depends on what types of devices are handled ineach area as well as what the device type is. Some devicesare easier to protect than others. It is equally important toengineer the program so human error is minimized. Dangel-mayer in [19], [22] terms this “human factors engineering.”Here, he uses the example of a grounding strap on the shoeto dissipate charge from a person. The strap was difficult toput on correctly. This made it ineffective in providing the de-sired protection. The dissipation element was integrated intoa special shoe, allowing all workers to use the equipment cor-rectly because everyone knows how to put on a shoe.

The ESD Program Committee is a multidisciplined teamcomposed of representatives from each functional area.These people are champions of ESD in their respectiveareas. They provide feedback to the Committee as well asgive unique insight into the best ways to improve ESD forthese areas. The Committee has a strong technical focus toassist in developing and reviewing ESD protection elementsand procedures. Their technical focus is on the improvementof the wafer fabrication process, circuit design, and handlingequipment and procedures to improve ESD in the circuitsthat are built. The ultimate goal is reducing the number offailures caused by ESD to zero.

A common part of each program is a full-time ESD Coor-dinator. This person acts as a champion for the plan as wellas a consultant for the organization. He is also the ProgramManager for the plan’s implementation and upkeep. TheESD Program Committee reports to him. Dangelmayerin [19] and [22] recommend this person be a part of theQuality Organization reporting to the corporate staff. Thisprovides the Coordinator with a global responsibility nottied to either the manufacturing or engineering organiza-tions. Communication from the coordinator to managementand the organization is key to the plan’s success [22]. TheCoordinator must have a wide background and be wellversed in ESD protection as well as program management.

The second most important aspect of an ESD program istraining. Training includes education on how ESD occurs andwhat damage it inflicts as well as proper handling of sensi-tive parts and the use of protection equipment. Our first papercan serve as an outline for a description of ESD and how itoccurs. Reviews of selected failure analysis reports can bebeneficial to drive home the point about how and what typeof damage can be introduced. Once an operator can asso-ciate a part they have handled with a type of damage it maymake them more careful. Education should include constantreminders of the need for ESD safety. These could come in

the form of posters and signs to help remind people that ESDsafety is important. Handbooks are useful as guides to properoperation of equipment and safe handling practices. A check-list of things needing to be done can be used. The key is tokeep the information fresh in their minds and make it perti-nent to the products they are handling. Make the informationpersonal so they see the importance of following the proce-dures to protect the parts they are handling.

Centralizing information resources is important to keeppeople from repeating mistakes [17]. Lessons learned onone project should be easily assessable to the next projectwhether or not team members are shared between projects.This level of documentation takes discipline of the teambut is time well spent if it saves several weeks of learningby the new team. One aspect of this discipline is for a newteam to seek out previous knowledge rather than trying toreinvent it all. Build on previous success and learn fromprevious mistakes. The explosion of the Internet and theuse of intranets to share information provide an excellentvehicle to share knowledge between workgroups and anexcellent tool to gather and disperse ESD information. Aninternal web server can be set up to enter and retrieve ESDinformation. The reader should talk with the local computeradministrator or information technology group about addingESD information to a company’s internal web server.

Most of the previous discussions were about training forthe people that handle product or come into contact withproduct, but this is not the limit of training. These people mayhave the most immediate impact but training is also neededfor others; however, it must be tailored to their needs. Man-agers are trained so they recognize the importance of ESDsafety and continue to provide support in the form of dol-lars and resources. Designers need to be trained on the bestavailable protection techniques to use and process designersshould be trained on how to provide protection in the ad-vanced processes. The key thing here is training is for every-body, but everybody does not receive the same training. Thecontent of the training must be targeted toward the group andfocused on bringing about a measurable change in behavior,not just filling the mind with more information [19].

C. Continuous Improvement

The last aspect of an ESD program is continuous improve-ment. This aspect is vital to the long-term success of the pro-gram. If the program stagnates it will die [21]. There are sev-eral aspects to continuous improvement. These include anaudit program, a failure feedback program, and a technologyimprovement program. The first thing people think of whenthe word audit is used is an IRS tax audit. Obviously thisis not the type of audit expected here, but some of the samefears and anxieties can arise. An audit program ensures com-pliance to the documented procedures and rules. Unfortu-nately, some auditors use this as an opportunity to displaytheir power over an individual or group and punish or dis-cipline them. This atmosphere creates significant tension be-tween the auditor and the one being audited. It does not resultin the desired action. The auditor is an instructor designed to


improve the compliance to the specification and to interpretthe specification [21]. An audit when viewed from this per-spective is not adversarial and is more likely to accomplishthe desired results—compliance to the specifications. Auditshelp encourage improvements and also spot problems thatcan lead to product failure [20]. An example of this is wherea technician, by using the equipment, determines a better wayto use it. The procedure can be updated in the specificationand the improved procedure implemented for all stations touse. An audit may consist of several stages or levels. Braude,in [20], recommended a three-stage audit: daily self-checks,monthly local audits, and a yearly third-party audit. An in-dependent group should perform the audit whether it is doneinternally or externally. The audit results should be postedand published for accountability purposes.

A failure feedback program identifies where ESD failuresoccur and what types of parts are being affected. In somecases it can also identify what type of ESD event occurred(HBM, MM, or CDM) to case the failure. The program mayreside in the failure analysis or reliability groups, or it couldbe in the quality organization or as a part of the ESD ProgramCommittee’s responsibilities. It should encompass both in-ternal and external failures. This program can produce a goodmeasure of how effective an ESD program is by showingthe reductions for ESD-generated failures. As the programmatures a reduction in the number of ESD-related failuresshould be seen. It may also highlight areas that are weak interms of ESD or areas where protection equipment needs ser-vicing or replacement. This may come in a sudden increasein the number of ESD-related failures through a functionalarea. This helps locate the source of the ESD event so it canbe corrected. The second aspect of this effort is to identifyweak parts from an ESD viewpoint. These may be candidatesfor redesign or for special handling procedures. The key as-pect is that failure analysis should be performed to determineif ESD is causing yield loss, and these results should be usedto improve the environment or part.

Technology improvements are an important part of contin-uous improvement. The process and circuits continue to im-prove in complexity and speed. These improvements makethem more susceptible to ESD damage. If the developmentof new protection techniques is neglected, technology willquickly outstrip the ability to provide protection. The searchfor new protection techniques is not limited to the integratedcircuits. New ways of preventing charge generation and con-trolled discharge of developed charges also evolves. As thesetechniques and equipment become available, they should beevaluated and integrated into the overall strategy if deemedappropriate. A good ESD program will not focus on one as-pect of ESD protection, but will provide a unified focus forall areas.

Improvements in technology include integrating new cir-cuit elements into the process architecture as well as lookingfor weaknesses caused by process advances. A researchand development (R&D) effort to improve ESD should bea part of the overall organization’s research budget. Thiseffort is focused on development and implementation ofnew circuit architectures to provide protection. These topics

are discussed later. Improvements in ESD production do nothappen by themselves. It takes a team of individuals andthe resources to experiment with new ideas and designs todetermine the best structures.

IV. ENVIRONMENTAL PROTECTION

An ESD event requires the existence of a voltage differ-ential between two bodies. If low impedance connects thesebodies, then the voltage is rapidly equalized, leading todamage of one or both bodies. If a high impedance connectsthem, the charge transfer is more controlled and does notcause damage. These are the two concepts used in environ-mental controls: minimize the voltage level generated andoptimize the transfer impedance between bodies but do notallow a condition where someone could be shocked. Theseconcepts are illustrated in the following sections looking atthe various areas parts are handled during manufacture.

A. Room-Level Controls

Control measures used at the room level are designed tominimize the voltages developed in a work area. This is typ-ically a large laboratory, test area, or wafer fabrication area.The conductivity of the air is the primary line of defense inthese types of area. It is difficult to sustain a charge on anobject if the charge is bled off through the air. There aretwo ways to control the air’s conductivity: humidity levelsand ionization. The amount of moisture in the air determinesits conductivity. This is easily illustrated by comparing theease one can be shocked by static electricity in the winterversus the summer. In the winter, the air is dryer because itholds less moisture when it is cold. In a home, this low-mois-ture content air is heated, allowing it to be even lower rela-tive humidity. The low-moisture content allows charges togrow on people without being dissipated. In general, higherlevels of humidity produce lower levels of generated and sus-tained charge [24]–[26]. The higher humidity also allows thecharges to be dissipated more quickly. The upper limit onhow humid an area may be is governed by equipment oper-ational specifications and personal comfort. The typical safeworking range is 30%–70% relative humidity.

Another way to control air conductivity is by injectingconductive species in the air. The charge must be injectedin balance (equal numbers of positive and negative species)so no net charge is introduced [27]. Room ionizers do this,as illustrated in Fig. 10. There are two types of air ionizersbased on how they produce ions. These are electrical and nu-clear ionizers [28]. Electrical ionizers produce ions by coronadischarge, whereas nuclear ionizers produce ions by nucleardecay [27]–[29].

Ionizers are more effective at controlling charges than hu-midity; in fact, ionization can cause a 20reduction in thedecay time of charge compared to humidity alone [27]. Ion-izers neutralize objects and people entering a work area aswell as maintain the work area neutral [28]. Ionizers are nota panacea for charge control but are an important part of atotal ESD program and should be used in conjunction withother protection techniques [30], [31].


Fig. 10. Ionizers for room-level control of charge generation.

The two most important parameters for ionization equip-ment are neutralization time and ion balance [31]. Neutral-ization time is the time it takes to neutralize a fixed amount ofcharge. This is a measure of the effectiveness of the ionizer.The ion balance provides a measure of the ionizer’s ability togenerate an equal number of positive and negative ions. If animbalance occurs, potential gradients will form. This is thevery thing the ionizers try to eliminate! Two other aspects ofionizers are the generation of stray electric fields and ozone.Stray electric fields interfere with some sensitive measure-ment equipment and their effect should be evaluated [31].Ozone is a byproduct of all ionizers [28], [31]. The produc-tion levels must be controlled and monitored to ensure a safeworking environment. As with all protection devices, propermaintenance is a must to keep the ionizers in balance andproduce the correct level of ions for neutralization.

Another room-level control is conductive flooring. Floorsand carpets are major sources of charging in a manufacturingarea [32]. The use of antistatic finishes can reduce chargegeneration, but their effectiveness is dependent on thequality of the installation and proper maintenance [33], [34].In addition, the footwear chosen should be matched withthe flooring [34]. Chase and Unger in [32] showed leathershoes to be the best because they had a high capacitanceand low-charge generation. The addition of a toe and heelground strap can greatly reduce the voltage levels obtained[34]. The user should evaluate each flooring/footwearoption carefully. Some antistatic coatings are worse thancommercial floor finishes [32].

B. Workstation Controls

Once the area controls are in place, it is necessary to movethe protection attention to the area where parts are beinghandled—the workstation. An example of a workstation isshown in Fig. 11. The work surface is the main place thatneeds attention. The parts rest here waiting further testing or

Fig. 11. Workstation with necessary controls for ESD.

inspection. The surface should neither induce a static chargeon the parts nor provide a rapid discharge path. The most ef-fective work surface is a static dissipative surface with a sheetresistance of 10–10 per square [34], [35]. The surfaceshould be impregnated with conductive material rather thanhave a topical spray to make it static dissipative. The top-ical spray can wear off and may leave residual material onthe parts, causing corrosion [36]. These work surfaces mustbe connected to a common ground by a low-resistance con-nection [4]. The common ground prevents voltage gradientsfrom developing. The low-resistance connection does not im-pede fault detectors from removing power should a shockhazard present itself. If a high resistance is used, the groundfault circuit may not trip and high voltages could be presenton the work surface shocking the personnel using the work-bench [4].

The use of conductive work surfaces (stainless steel forexample) presents a hazard for the parts as well as a shockhazard for people [34]. The part can be rapidly dischargedbecause the metal surface acts as a large charge sink. The sur-face can absorb a large amount of charge without changingits surface potential significantly. With little or no series re-sistance the part may discharge very quickly, resulting in ex-tremely high currents and power dissipation.

As we saw with floor finishes and ionizers, proper main-tenance is necessary for continued performance. The surfacemust be cleaned periodically and the connections checked forproper grounding. If topical sprays are used, they must be re-newed on a periodic basis.

Other furniture at the workstation needs to be evaluatedfor its ability to charge and discharge. The sitting surface ofchairs used at a workstation should neither charge nor in-duce a charge on the operator. A charged chair can cause the


Fig. 12. Person with necessary ESD protection equipment in place.

person to charge by induction as well as cause electromotiveinterference (EMI) to radiate from the legs of the chair as thepotential discharges in the seat cushion [37], [38].

Inductive charging is a real concern at the workstation.Any charged surface can induce a charge on the parts beingworked, causing them to be damaged. Because of this,all materials that charge and other charged sources mustbe removed from the workstation. These include papers,computer monitors, cups, plastics, and synthetic materials.A more complete description of inductive charging is foundin our first paper [2].

C. Personal Controls

Part handlers must take special care while doing their jobs.Fig. 12 shows a person with the necessary ESD equipment inplace. They also must employ special equipment that keepsthe charge levels on their bodies to a low level. The first lineof defense are grounding straps [39]–[41]. These can be ap-plied to the wrist and/or shoe. The purpose of these is to re-move charges that developed on a person’s body in a con-trolled manner. There are two types of wrist straps: contin-uously monitored and periodically monitored [42]. For thefirst, the wrist strap is connected to a piece of equipmentthat continuously checks the strap’s connection to the personwearing it. The second must go to a special checking sta-tion to ensure the strap is working properly. The continuouslymonitored straps cost more initially but provide a real-timefeedback to the operator if a grounding problem occurs. Lostwork time resulting from the need for periodic monitoringcan provide a payback in about a year for the extra cost.

The ability of the wrist strip to function correctly is largelydependent on its ability to contact the skin’s surface [39].The wrist strap should be in direct contact with the skin.Body hair, skin dryness, and clothing can interfere with thiscontact. There are specially formulated creams that can helpimprove the electrical contact. As with all ESD preventativeequipment, it is important that these straps are properly main-tained.

Clothing can aid in the fight against ESD damage or itcan hinder. People handling ESD-sensitive equipment mustrealize that the synthetic fibers used in many clothes generatecharge. This charge can then damage equipment. Sweaters

Fig. 13. Protective carrier with conductive inserts.

worn in the winter can charge our bodies just by the normalmovements such as reaching for a tool. The use of specialsmocks that have conductive fiberswoveninto them can helpreduce the risks from this type of clothing [43]–[46].

Proper training is important for people handling sensitiveequipment or parts. They need to realize that the safety mea-sures take time to work and should allow time for their bodiesto stabilize prior to picking up a sensitive component. Youshould not remove your sweater and then pick up a sensitivecomponent. Remove your sweater away from the workbench,then walk over to the workbench and connect the groundingstrap and turn on any other safety equipment. Allow a fewmoments for the area to stabilize, and then start working onthe parts.

D. Packaging and Storage

The storage and transportation of parts from one area ofmanufacturing to another or from the manufacturer to the enduser are critical areas for protection. The protection measurescome in the form of carriers and containers. At the lowestlevel, a part may require a supportive carrier to prevent me-chanical damage during handling. An example is a clip usedto hold the leads in place during electrical testing, as illus-trated in Fig. 13. It is important that the clip does not generateor hold charge. The added complication is that the part mustbe tested with the clip in place, so the clip must not alter theelectrical characteristics of the part it is attached to. To ac-complish this, static dissipative inserts can be placed aroundthe leads. The resistance is high enough to prevent distortionof the electrical characteristics of the part but low enough soany accumulated charge is dissipated in a controlled manner.

The containers may take the form of tubes, bags, boxes,or reels. Special coatings or metal foils can be used in thesecontainers to reduce the generated static or provide a shieldagainst external fields [47]–[53]. It is important to knowthe limitation of protection provided with each method oftransportation. ATT implemented a policy that shippingtubes could not be used for devices with CDM200 V andno tape and reel for CDM 1000 V on corners and 500 Von all others [3]. Another attribute to consider in selectionof the proper container is whether the coating poses a threatof contaminating the parts with a foreign substance that maypromote corrosion [36]. A careful study and trial periodshould be done for each package style change.

E. Automatic Test Equipment

The increased use of automatic handlers for electrical testand robotics for automatic assembly has highlighted a defi-


Fig. 14. Temperature rise in a bulk and SOI transistor for a 2000-V HBM pulse; darker gray indicateshotter region.

ciency with these tools. They generate static charges and candamage parts [54]–[60]. The use of plastics and other syn-thetic parts in the pathway allows triboelectrification to occurto the parts. Once the parts become charged, they can rapidlydischarge as they come into contact with a grounded test heador metal surface, resulting in a CDM ESD event. The key isto realize that the equipment must be properly grounded toprevent charges from developing on it, and insulators aroundwhere the parts travel must be replaced with static dissipativeor antistatic material [57], [58]. The use of local air ionizersmay aid in reducing the charge levels produced if insulatorsare required for proper operation of the equipment [61].

V. CIRCUIT PROTECTION

The first thing to remember when evaluating a circuit orprocess for ESD robustness is that ESD is a charge-drivenevent [1]. The movement of that charge or the current pro-duced causes the damage. It does this by two effects: Jouleheating and charge injection. The current passing through re-sistance in the current path causes joule heating. This heatsthe structure, resulting in damage. The resistance in the cur-rent path also causes the second aspect. As the current passesthrough these resistive elements, a voltage drop proportionalto the current and resistance is established. This voltage cou-pled with the geometry yields the electric field present in thestructure. The electric field causes charge injection and di-electric rupture. These two aspects, heat generation and elec-tric field strength must be minimized to provide robust circuitto ESD events. Circuit protection involves much more thanjust the schematic of a protection network. It also encom-passes the wafer fabrication process, circuit elements, and

their interaction with the layout. All of these play into circuitprotection and each will be discussed in the following sec-tions.

A. Wafer Processing Issues

The first step in developing a circuit protection strategyis to assess the technology used to manufacture the part.Each technology has strengths and limitation. For example,technologies that use insulated substrates to improve perfor-mance [silicon on sapphire (SOS), silicon on insulator (SOI),or gallium arsenide (GaAs)] have difficulty removing theheat that is produced by an ESD event. This is illustrated inFig. 14. The same size circuit element was used with the onlydifference being the insulating substrate rather than a bulksubstrate. The SOI device has a temperature rise of 300Cmore than the bulk transistor for the same discharge energyand the temperature contours are grouped much tighter. Theheat is generated by the current flow during an ESD event.As this current flows through the reversed biased drain–bodyjunction, the electrical insulation acts as a thermal barrier.This lowers the heat flow and thermal mass that can absorbthe energy, making these technologies more difficult to pro-tect.

Not only is the heat flow an issue, but also electric fieldis important. Fig. 15 shows the electric field at the gate edgefor a LOCOS (local oxidation) bulk transistor and an SOStransistor. The SOS transistor is built on an island of siliconcalled a silicon mesa. The poly gate extends along the edgesas well as on the top. At the corner of the mesa, the gateoxide has the highest field. This is the most likely point offailure. The sidewall slope can be improved to minimize this


Fig. 15. Electric field distribution in the gate oxide between bulkLOCOS transistor and SOS transistor at transistor edge.

Fig. 16. Circular gate structure used on SOS protection elements.

field but at the expense of larger mesa size and increasingthe parasitic effects of the side wall transistor. This type oftransistor cannot be used in an ESD protection circuit. It istoo sensitive to voltage transients. A more effective design isto use a circular gate structure, as shown in Fig. 16. In thisdesign, the gate does not cross the mesa edge.

The continuing technological advancement in the ICindustry also stands in the way of ESD protection [62]. Thetechnology may scale to higher levels of integration but thesources of ESD, like human beings, are not scaling. Theypose the same threat to a more sensitive device. Four areasof scaling make a technology more sensitive to ESD events.These include interconnect lines, junction depths, oxidethickness, and the activation of parasitic devices. Scalingis the reduction of feature size to improve integration andperformance. These advances have a negative effect on ESDperformance. Packing more transistors into a smaller spacerequires the interconnecting lines to be scaled. These finerlines can handle less current. Several authors [63]–[71] havediscussed metal lines’ ability to withstand different currentstress; however, Vinson, in [71], discusses a physics-basedmodel that is appropriate for the adiabatic case such as anESD event. This is discussed in more detail later.

The junctions formed in the process are also affected byscaling rules. Junctions typically become shallower as theprocess scales. This can cause problems in diffused resistorsand cross-unders. The shallow junctions are more easilyspiked (metal penetrating the junction shorting it out) ifESD current flows through them. Diffused resistors shouldbe formed in a well of similar doping so if the metal doesspike through the more heavily doped layer, the spike willnot short out the isolation. This is illustrated in Fig. 17 foran n-well process.

Fig. 17. Diffused resistor built in an n-well to improve ESDtolerance to junction spiking.

Fig. 18. Excessive voltage generated because of high bus andclamp resistance during event.

In a similar fashion, the gate oxides scale and, to a smallerdegree, so do the interlevel oxides. As mentioned earlier, theelectric field is an important aspect of the damage process.A thinner oxide produces a higher electric field for the samevoltage level. This allows dielectric rupture to occur at lowervoltages. There is not much that can be done to strengthena dielectric except use one with a higher dielectric strength.Extra elements must be included to clamp the voltage levelsbelow the rupture strength. In addition, one should paycareful attention to the resistance of the ESD current paths.If the internal resistance of the clamp and bus structuresare too high, internal voltages are generated. These couldrupture dielectrics. This aspect is illustrated in Fig. 18. Ifthe diode is made too small, its external voltage rises abovethe breakdown of the gate oxide resulting in rupture. It isbest to avoid thin gates on input–output (I/O) pins and alsominimize bus and component resistance. The metal busline must be kept from melting. If it melts, the dynamicresistance doubles and contributes to damaged oxides [71].

The last aspect of scaling is the most difficult to analyze.As geometry shrinks and spacing between devices decreases,parasitic transistors may form. These parasitic elements maynot be present during normal circuit operation but will be-come active and conduct because of the high currents andhigh bias applied during an ESD event. A conservative ap-proach is needed in spacing where areas of opposite polaritydiffusions are close to each other. Look for parasitic bipolar,MOS, and SCR structures in the layout.

The last aspect of wafer processing issues deals withthe effect of process enhancements on ESD robustness.Three recent advances that can degrade ESD performanceare LDD—lightly doped drains used to improve hot carrierperformance; silicided junctions used to reduce contactresistance; and thin epitaxial starting material used to reduce


Fig. 19. NMOS transistor with LDD implant and silicided drainand source regions.

latch-up susceptibility. The LDD structure is illustrated inFig. 19. The lightly doped drain area reduces the electricfield at the oxide surface. This reduces the generation of hot(high energy) carriers at the surface. Some of these “hot”carriers can be injected in the oxide shifting the transistorthreshold. The LDD structure gives rise to added resistancein the channel and also produces higher holding voltage oncesnapback is triggered. Both of these reduce the ESD currenthandling ability of the transistor [73]–[75]. Correcting theeffects of LDD implants on ESD protection element requiresthat the LDD implant be blocked or carefully engineered toaccount for the high currents during an ESD event.

A silicided transistor is also illustrated in Fig. 19. The sili-cide is a thin layer of tungsten, titanium, or cobalt depositedon exposed silicon and heated to form a silicide. The sili-cide is a thin layer of low-resistivity material at the surface.It is typically on the order of a few hundred or a few thou-sand angstroms, depending on the process. The current flowsmainly in the silicide layer because of the high ratio in resis-tance between the silicide and the silicon. The low resistanceof the silicide does not allow the current to spread well acrossthe transistor’s full width. It tends to crowd in a small portion.Because of this, it is recommended that a silicided transistorbe kept narrow in width ( 30- m) to more easily balance thecurrent across the width [76]. Another technique is to maskoff a section of the drain so no silicide is present between thecontacts and the gate edge. This adds a small resistance inseries that provides a ballast resistor to aid in balancing thecurrent.

The use of thin epitaxial material is another exampleof how process improvements degrade ESD performance.Snapback is caused in n-MOSFETs when lateral currentstrigger on a parasitic n-p-n transistor. This is illustrated inFig. 20 for both thick and thin epitaxial silicon. An epitaxiallayer of silicon is grown on top of heavily doped silicon toencourage the vertical current path with all of the lateralcurrents flowing in the heavily doped layer. Lateral currentsproduce voltage drops from the current flow and the siliconresistance. This voltage can bias the body–source diodetriggering on the n-p-n transistor. By thinning the epitaxiallayer, the effective resistance is reduced so a higher currentis required for latchup. The triggering of the parasitic bipolarinto snapback is also what takes the transistor into a lowerpower dissipation mode during an ESD event. If the triggercurrent increases, so does the power dissipation, making thetransistor less robust to an ESD event. The gain or beta ofthis parasitic bipolar element contributes to the snapback

Fig. 20. Thin and thick epitaxial layers effect on latchup and ESDperformance.

characteristics. The process architecture determines thecharacteristics of this element. An example of this behavioris presented later in the paper.

It is clear that all aspects of wafer fabrication need to beevaluated with regard to how these changes affect the ESDperformance of the circuit elements and parts built on thisprocess. These effects must be considered during the designof the process and its integration into the design and layouttools used to bring a circuit into silicon.

B. Circuit-Level Issues

The entire design team, including designers, marketing,manufacturing, reliability, and the end customers, must re-alize that tradeoffs are required when designing ESD into acircuit. Areas of concern cover the input impedance, perfor-mance of the circuit, and the die size. A bare circuit (smallestdie size, no protection elements) typically has a very poorESD performance. As we will see in a later section, ESDperformance is improved when circuit elements are addedto divert the charge flow away from sensitive elements andto clamp voltages generated by this charge. These added ele-ments increase the input impedance. Added input impedanceis especially not tolerated for very fast transitioning signalsbecause ESD protection networks look like a low-pass filter.Fig. 21 shows a typical ESD protection element found on aninput pin. The element closest to the gates of the MOSFETsclamps the voltage to a level low enough to protect the gateoxide from rupture. The current flow is through the resis-tance that allows a voltage drop from the input further pro-tecting the gate. A supply clamp (not shown but discussedlater) completes the circuit to a common pin. This circuitpresents itself as an filter to any input waveform. Higherfrequencies are shunted to the supply pins where lower fre-quencies are passed to the gates. Fig. 22 shows the impedanceas a function of input frequency for a sine wave input. Thecurrent handling capability of the diodes and therefore theESD level obtained is largely dependent on the diode size.Larger diodes provide better heat dissipation as well as loweron resistance. The problem is larger diodes also have highercapacitance. This causes larger amounts of the input signalto be shunted to the supply pins. There is a tradeoff between


Fig. 21. Simple input protection network.

the frequency of input signals and the level of ESD protec-tion. This is most noticeable for very high-frequency circuitsthat operate in the RF range.

As mentioned earlier, ESD performance can be improvedby increasing the physical size of an element. This improvesits current and power handling ability. A problem occurswhen a die shrink is required to reduce cost. The cost toproduce one wafer is typically fixed and difficult to change.The unit cost is made up of the wafer and manufacturingcost amortized over the number of good die per wafer. Thenumber of good die per wafer is dependent on the yieldand the number of gross die on a wafer. The die yield isdriven by defect density, which is a decreasing function ofarea. Larger die yield lower than smaller die. When a die ismade smaller by shrinking the geometries of each element,a twofold cost saving occurs. The yield goes up from thesmaller die and the total number of possible die on a waferincreases. The problem is the sources of what causes ESDdo not scale with die size. They are fixed and still generatethe same voltages and charge levels. This condition presentsa problem. The ESD protection cannot shrink and givethe same level of protection. ESD protection structures aretypically located around the bond pads. In designs that arebond-pad limited, the die size cannot shrink without the sizeof the pads shrinking. Bond-pad limited means the numberof bond pads required on the die drives the die size. Thecircuitry interior to the die does not drive the die size. Thisproblem can be overcome by using active area bonding.This is a technique where the ESD protection network isincorporated under the bond pad. Bernier and Teems, in[77], and Andersonet al., in [78], report on their experiencewith active area bonding. The key thing to remember isthat active area bonding can be done but, again, tradeoffsand special considerations must be made. Because of theextra stress placed in the corners of plastic encapsulated die,active area pads cannot be used in the corners and specialprovisions need to be made in the metal layers under the padfor the force developed during bonding.

The type of circuit function plays an important role in howeasily the device can be protected. As an example, digital cir-

cuits are more easily protected than a mixed-signal analog.Digital circuits typically have one supply voltage. The in-puts switch between zero and the supply voltage. In the liter-ature, digital circuits are the types of circuits with very large(4–10 KV) ESD threshold levels. Analog and mixed-signalparts with multiple supply lines and sensitive input stagesare more difficult to protect. The inputs are high-impedanceJFET transistors. Circuit performance requirements preventadding input impedance to these pins. Multiple supplies poseanother challenge because now you must provide protectionbetween all combinations of supplies without introducingextra leakage on the supply lines. As the number of suppliesincreases, this becomes very difficult and adds a lot of area tothe die size. An extreme case is very high-speed RF circuitsoperating in the gigahertz frequency range. There is verylittle written about RF ESD protection [79]–[82]. RF ESDprotection follows other ESD design techniques but there arejust more constraints placed on the design [79].

The operational environment also poses a challenge to theESD protection designer. A typical environment is consid-ered benign if the part is operated in a office and does notcome into direct contact with people or other sources of EOSonce it is assembled into a board or system. This is the eas-iest environment to design for. In this case all of the toolsand devices are available for ESD protection. One problemenvironment is where the circuit is to operate in a hot-plug-ging application. This means that the parts are plugged intoa system while the power is still applied. This type of circuitrequirement adds another level of complexity to the ESD pro-tection. In a typical application, the ESD protection is trig-gered when the part is not operational and no power is ap-plied. The protection circuit is asked to absorb the energy inthe ESD event itself. Most protection techniques incorporatesome form of clamp, as discussed later. The clamp is trig-gered in response to a rapid change in voltage or current. Itmay also trigger at a predefined voltage level. The problemwith hot insertion is the power-up transient seen by the de-vice is mistaken as an ESD event. In this case, the full energyavailable from the power supply is passed into the protectioncircuit. The net result is the protection circuit is destroyedand the part fails. In this type of circuit, the protection clampmust be a voltage-level triggered clamp or a transient triggerclamp that is only triggered if the voltage is above the op-erational voltage. The second clamp is a more effective butmuch more complex clamp structure.

Some circuits must work in an environment where theinput voltage levels exceed the supply lines. Examples ofthese are multiplexers and switches. The inputs are speci-fied with a 25-V overvoltage rating, even though the sup-plies are rated at 15 V. Having inputs exceeding the supplylines poses challenges because typical protection techniques,as shown in Fig. 21, cannot be used. One technique is to allowthe inputs to be tied to an isolated bus on chip. This is illus-trated in Fig. 23.

Parts in a radiation environment also pose limitations onthe designer in their choice of ESD protection circuit. Thetransient currents produced by ionizing radiation can triggerprotection networks while the device is operating. This can


Fig. 22. Input impedance of an input protection network as a function of frequency for Fig. 21.

Fig. 23. ESD protection networks for input voltages that exceedsupply levels.

lead to soft errors (changes in functional behavior that arereset after the radiation event) to physical destruction ofthe device. Destruction can occur when the ESD networkturns on with power applied. The energy available from thesupply line is much greater than that found in an ESD event.The ESD structure is destroyed shorting or opening internalnodes. The type of physical damage observed is in the formof melted metal and silicon.

The last area of operational environment is the special caseof line drivers and receivers. This group of parts must operatein an environment outside of the system and interface withoutside equipment. Typically these devices tie long cablestogether. The long length of cable can produce high-voltagetransients and make it more prone to receiving an ESD event.The pins that connect to the outside world need higher levelsof protection and may be rated at 10 KV rather than 2 or 4 KV.

It is clear that the environment plays a large part in se-lecting what type of protection is needed and the best way toimplement it. The next section covers the technique used toincorporate protection into a circuit design.

C. Protection Techniques

Implementing an ESD protection circuit first requires areview of the building blocks in a process and an under-standing of the limitation of each element from an ESD per-spective. Voldmanet al., in [72], described the results of aSEMATECH working group that is defining a strategy forcharacterization, evaluation and benchmarking the ESD ro-bustness of technologies. This group is defining standardizedtest structures. The reader is encouraged to keep up with theprogress of this working group.

In a semiconductor wafer process, the elements of interestinclude interconnect traces, resistors, inductors, diodes, tran-sistors, and capacitors. These are the physical building blocksfor a circuit and an ESD protection network. The parasiticn-p-n in a NMOS FET, for instance, plays an important rolein its high-current behavior. When it goes into snapback, thevoltage across the device drops, reducing its power dissipa-tion. It is important to know the high-current behavior of theelements so an adequate protection scheme can be designed.

Metal lines form both the interconnect channels betweencircuit elements as well as the inductors used on somecircuits. These metal traces have two issues when viewedfrom an ESD perspective: fusing and electromigrationdegradation. Vinson, in [71], describes a simple adiabaticmodel for predicting aluminum line failure from EOSphenomenon. He shows the line fails because of an eruptionof aluminum vapor. This is caused by a section of the lineabsorbing enough energy to vaporize. The volume occupiedby aluminum vapor is significantly larger than the volumeoccupied by solid aluminum. The silicon dioxide cannotwithstand the pressures developed. The model is based onthe enthalpy and temperature-dependent resistivity of alu-


minum. The model presented was developed in MathCAD.For most ESD events, 15m is adequate to prevent fusing[76]. Larger lines may be required to minimize the voltagedrop during an ESD event. The large currents can gen-erate voltages capable of rupturing dielectrics and causingjunctions to break down. As an example, a CDM eventcan generate current in excess of 7 A. A metal line with aresistance of 1 would have 7 V dropped just across theline not including any protection element. This extra voltagecould be dangerously close to the rupture limit of the gates.The additional voltage from a protection element wouldcause the dielectric to rupture.

Larger metal lines may also be required to minimizethe heating of the line. Thermal heating takes the line pastaluminum’s melting point. Once the event is over, the linecools very quickly. This action alters the grain structure ofthe metal and changes its electromigration performance.Banerjeeet al., in [83], reported on an aluminum metal struc-ture with TiN top and bottom caps. The EM performancedegraded with ESD. The finer grains produced from rapidcooling after the event cause this. These two factors mustbe taken into account when designing an ESD protectionnetwork, so adequate metal is placed in the ESD network toallow it to function without reliability degradation.

Resistors are another circuit element to consider. They aretypically used to drop the voltage or as isolation elements inprotection networks. In their thin-film form, they are madefrom polysilicon or alloys of NiCr or SiCr. They can also bediffused resistors made by placing a lightly doped diffusionin the substrate. Resistors fail in one of two ways—fuseopen or short out. Most of the thin-film resistors fail byfusing open. The energy in the event melts a region, causinga physical separation of the resistor terminating the currentflow. Large voltage spikes are induced when this separationoccurs. The voltages spikes are caused by the inductanceinto the current path and the very quick decay of the currentflowing in the path once fusing takes place. Fig. 24 showsan example of the energy to blow a resistor. The constantminimum energy region is where adiabatic fusing takesplace. ESD events produce damage in this area because ofthe very fast events. Slower EOS events allow some energyto escape to the surrounding area, therefore the increasedenergy and time required for fusing. Fig. 25 shows the– characteristic for a resistor that shorts. This is typical

of diffused resistors. The resistor element has a region ofelectron velocity saturation and eventually enters secondbreakdown. Second breakdown causes a physical changein the device structure. Part of the device melts. Fig. 5 alsoshows how geometry can reduce the point where secondbreakdown occurs. The 90bend in the resistor causedcurrent crowding, allowing this region to reach secondbreakdown at a lower total current than expected.

The MOS transistor has a parasitic bipolar transistorburied within it [85]. Fig. 26 shows the cross section of atypical NMOS transistor. As mentioned earlier, this tran-sistor plays a significant role in the conduction of currentduring an ESD event. Fig. 27 shows a typical conductioncurve for this device. With the gate voltage at zero, the drain

Fig. 24. Energy to blow a typical resistor.

Fig. 25. I–V characteristic (high current) for a diffused resistor.[84]

Fig. 26. Cross section of n-channel MOSFET.

Fig. 27. I–V characteristic (high current) for an n-channelMOSFET.

voltage increases with little or no drain current until thedrain–body junction enters avalanche breakdown, as shownby the point . The avalanche current flows to thesubstrate and out through the body/source contact. The bodyresistance allows a voltage to develop between the bodyregion near the drain and the body contact. This voltage canforward bias the body source diode, injecting more chargeinto the base region. Once this occurs, snapback soon followsand the drain voltage drops significantly. The sustainingvoltage and sustaining current are shown in Fig. 27.This point defines the voltage and current level necessary to


maintain the snapback condition. Voltages or currents belowthis level will shut off the snapback condition. These levelsshould be kept above the operating voltage of the device soit is not possible to sustain snapback during normal deviceoperation. As the current increases, the drain voltage alsoincreases. The internal resistance of the device causes thisincrease. The voltage and current increase until secondbreakdown is reached at , . In a similar fashion tothe diffused resistor, the device destroys itself. It is desiredto have when a protection element is made upof multiple parallel transistors. If , then the firstleg of a parallel structure to break down will carry all of thecurrent and be destroyed before the other transistors can turnon. This defeats the purpose of having multiple transistorsin parallel. Another condition that causes problems is when

. This condition often occurs in technologieswith insulating substrates such as SOS. Once the devicebreaks down, it is destroyed. This type of transistor wouldnot be good to use for ESD protection.

One way of providing protection to the circuit is toimprove the elements themselves so they can handle theESD current. Improving unprotected elements involves:1) reducing the current density of the conduction path; 2)reducing the electric fields induced; and 3) reducing thethermal impedance or increasing the thermal mass at thepower dissipation point. In the case of thin-film fusing, itis as simple as increasing the width of a thin-film resistoror metal line. This accomplishes two tasks. First, the widerline lowers the resistance and the power dissipation. Second,the extra volume increases the thermal mass of the line[71]. It can then absorb more energy without going intosecond breakdown or fusing open. Another option is to usea different material that has a higher melting/vaporizationtemperature. The difficulty with this approach is these typesof metals also have a higher resistivity. The higher resistivityis undesired when high currents are involved. In the caseof diffused versus polysilicon resistor, another factor mustbe considered. A polysilicon resistor is surrounded by adielectric that acts both as an electrical insulator as well as athermal insulator. A diffused resistor can dissipate the heatbetter than a polysilicon resistor because it sits in siliconrather than on oxide.

Increasing their size and providing more uniform currentflow across the device improve transistors and diodes. Asmentioned earlier, large protection transistors are made upof many parallel transistors. It is important to balance thecurrent flow across all of the transistors in the string. Thiscan be accomplished by placing small resistances in serieswith the drain contacts. In the case of a MOSFET transistor,as shown in Fig. 28, the silicide is omitted from a sectionof the transistor near the gate. This places a small resistancein series with the channel. The resistance helps balance thecurrent through the transistor during an ESD event. This ac-tion keeps one spot of the transistor from absorbing all ofthe ESD energy. For technologies without silicide, the con-tact to gate spacing is important. This spacing should be atleast 2–3 m for submicrometer technologies and 4–6m forlarger channel length (1–2m) technologies [76]. Geometry

Fig. 28. ESD improvement individual circuit element.

effects are very important for diodes. Their design should besymmetric with no irregularities that would allow the currentor electric field to be focused in one area.

The other method to increase ESD robustness is to addadditional circuit elements to divert the charge around thecore circuit and clamp the voltage to an acceptable level.The core circuits are the elements used to perform the func-tion the circuit was designed to do. The ESD protection net-work must prevent the damaging ESD current from flowingin this circuitry. In addition to diverting the charge, the pro-tection network must limit the voltages developed to a lowenough level so no core circuits enter breakdown. If any corecircuits enter breakdown, then the ESD current would flowthrough them, causing damage. Most circuits use a combina-tion of improving individual elements and adding additionalelements to achieve the desired performance. The obviousquestion is where should one place the extra components andwhat types of components are necessary. The placement ofcomponents requires an understanding of the current pathsused by ESD.

As mentioned earlier, ESD events come in three versions:HBM, MM, and CDM. The first two, HBM and MM, aretwo terminal events. ESD current enters one terminal andexits another. The current flows through the device under test(DUT). In an ESD tester, testing each combination of twopins simulates this effect. Each independent supply is treatedas a single pin even if multiple pins for that supply exist onthe packaged part. CDM is different in that the charge for theevent is stored internal to the package. CDM is a single pinevent. The part is charged and is discharged through a singlepin. Fig. 29 illustrates this. Fig. 30 shows the current wave-form for a CDM event. Included in the figure is an HBMwaveform for comparison. As shown, the CDM event is veryfast and significantly higher in current. The fast event andhigh peak current makes it difficult for protection networksto protect circuits. The quickness of the event means the pro-tection networks must turn on quickly. The higher current re-quires the series impedance to be very low to reduce the gen-erated voltages. Dielectric rupture is a more common failuremode with CDM ESD. In a typical nonsocketed CDM tester,the DUT is placed on an insulating surface above a metalplate. The package style and design play an important role inthe CDM ESD threshold for a part. The capacitance, resis-tance, and inductance of the package determine the rise time,current peak, and duration of the ESD event. The importantinformation to note is that ESD events enter or exit the part at


Fig. 29. CDM event discharge path.

Fig. 30. CDM event current discharge waveform.

the connections to the outside world. The protection networkmust divert the charge as it enters or leaves the package so itmust be placed at or near the bond pads to be most effective.It is also important to note that each pin must be protectedto every other pin, including all of the supply pins. It doesnot matter whether they are outputs, inputs, I/Os, or supplypins—they all need some form of protection.

A good protection element will minimize the voltage al-lowed internal to the unit as well as provide a low-impedanceshunt path for the current. This allows the charge to flowthrough the protection element and not the circuit being pro-tected. By doing this, the energy is dissipated away from thecircuit being protected. The protection element should be ca-pable of handling multiple events without itself being de-stroyed. It should also not interfere with the operation of thecircuit it is protecting. Given this discussion a perfect protec-tion element will have these characteristics:

1) zero on-resistance;2) zero clamp voltage;3) instantaneous turn-on time;4) infinite energy absorption;5) only trigger during ESD events, not during operation;6) transparent to circuit operation (i.e., no parasitics);7) consume zero area on the die.Zero on-resistance allows it to shunt large amounts of cur-

rent with no voltage rise from an ohmic voltage drop. Zeroclamping voltage is only valid if 5) is also true, otherwisedamage could occur during circuit operation. A more prac-tical limit on the clamping voltage would be just above the

Fig. 31. ESD protection by adding circuit elements.

operating supply voltage of the part being protected. The lastitem is included because many times a tradeoff in cost versusprotection level must be made. In this case, the cost is diearea. It is clear that a real clamp of this type cannot be built,but these criteria provide a list of optimizations and compro-mises to use when building a protection element.

Fig. 31 illustrates a simple ESD protection network. Thenetwork consists of a resistor and diode. This is not the bestnetwork but illustrates the point of protection. If a negativepulse with respect to ground enters the part, the current willflow from ground through the diode and resistor. The voltageacross the n-channel MOSFET gate oxide will be limitedto one diode drop plus the drop from the internal re-sistance of the diode. This keeps the gate oxide from rup-turing. The remaining voltage is dropped across the resistor.For the opposite polarity, the diode is in reverse breakdown.The voltage across the gate oxide will be clamped at thediode breakdown point, plus the internal drop and theremaining voltage is dropped across the resistor. The diodewould be able to handle much more current in the forward di-rection than in the reverse direction because the voltage dropis much less in the forward than in the reverse conductiondirection. A better approach is illustrated in Fig. 32. Here,two diodes are placed on the input and a protection networkis connected between the supply pins. In this arrangement,the diodes on the input pins can conduct in the forward di-rection and the supply clamp allows the conduction betweenthe supplies. It should be noted that the internal resistancebetween each of these elements must be minimized to re-duce the voltage developed across the interconnect. A dis-tributed supply clamp may be required. This provides mul-tiple clamps spaced across the die to lower the impedancebetween pins.

The protection networks being described here are clamps.Clamps can come in many different varieties. A simpleclamp was used in Figs. 31 and 32—the diode. As discussed,the diode has good power handling ability in the forwarddirection but is a poor clamp in the reverse current direction.Clamps can be grouped into two categories: static andtransient. As the name implies, static clamps provide astatic or steady-state current and voltage response. A fixedvoltage level activates static clamps. As long as the voltage


Fig. 32. More effective ESD protection architecture than Fig. 31.

Fig. 33. Static clamps.

is above this level, the clamp will conduct current. Fig. 33illustrates and Table 1 describes a sample of static clamps.As can be seen, static clamps can be composed of a singlecircuit element or a combination of circuit elements. Adiode, MOSFET, or SCR is typically used as the protectionelement located on the input or output pin. A combinationclamp is used as the supply clamp. The supply clamp maybe a single clamp or multiple clamps distributed across thedie. Using multiple clamps provides the added benefit ofreducing the parasitic resistance between the supply clampsand the pin clamps. Transient clamps take advantage of the

Table 1Static Clamps

rapid changes in voltage and/or current that accompaniesan ESD event. During this transient, an element is turnedon very quickly and slowly turns off. This type of clampconducts for a fixed time when it is triggered. Annetwork determines the time constant. These clamps aretypically triggered by very fast events on the supply lines.A sample of transient clamps is illustrated schematically inFig. 34 and discussed in Table 2.

For the MOSFET transient clamp shown in Fig. 34, boththe normal MOS and parasitic BJT (snapback) can be oper-ational at the same time. When an HBM ESD pulse with arelatively fast rise time is introduced to the clamp circuit, thecapacitor will initially be a short circuit, which turns on theMOS device quickly. Consequently, a large drain current as-sociated with the HBM ESD will pass through the MOS de-vice in this initial transient. At the same time, the high voltageassociated with the ESD pulse applied to the drain can giverise to avalanche multiplication near the reverse-biased drainjunction. This results in a flow of avalanche-generated holesto the substrate and a voltage drop across the substrate re-sistance. As this voltage drop approaches 0.7 V, the parasiticn-p-n BJT in the MOSFET is turned on resulting in snapback.The dc – curve for this event is shown in Fig. 27. Duringthe initial stage of an ESD event, the MOSFET acts like ashort circuit with a very high total drain current consisting ofthe collector current from the parasitic BJT, the drain current


Fig. 34. Dynamic clamps.

Table 2Transient Clamps

from the normal MOS, and the generation current from theavalanche multiplication. In the next sequence, the capacitorwill be charged through the resistor, and the charging rate de-pends on the time constant of the clamp circuit. As thevoltage across the capacitor increases, VGS of the NMOS de-creases, and the capacitor acts as an open circuit when fullycharged. The MOS device is turned off, while the parasiticBJT is still on, when VGS decays below its threshold voltage.This leads to a quick decrease in the drain current and a rel-ative uniformity in the drain voltage during the subsequentstage of the ESD event (i.e., the voltage across the circuit isclamped to a fixed value). Eventually, the parasitic BJT isturned off when the ESD pulse decays to a value below thecritical voltage for avalanche. For an ESD pulse with a rel-atively small rise time, the voltage drop across the resistorconnected to the gate in the clamp circuit may not be highenough to turn on the NMOS in the initial stage, and only theparasitic BJT is operational during the ESD event. Fig. 35shows the transient drain voltage and current measured forsuch a clamp circuit.

Both have advantages and disadvantages. The static clamptypically occupies less space and is composed of fewer ele-

Fig. 35. Measured time-dependent (a) drain voltage and (b) draincurrent of the MOSFET transient clamp with a MOSFET of 1.5-�mchannel length and 80-�m channel width subjected to an HBM ESDstress.

ments. If a static clamp falsely triggers while power is appliedto the part, it will be destroyed. Transient clamps, on the otherhand, can be designed to turn on very quickly and handlelarger transient events. The disadvantage is that they will alsorespond to any fast event, even noise. If they falsely triggerwhile the part is powered, they could interfere with circuitoperation and it is likely that the part will be destroyed.

The selection of what type of clamp to employ in a designis based on several criteria. The first criterion is what circuitelements are available in the process. The next would relateto the environment the circuit must operate in. This was dis-cussed earlier. An SCR is not usable where hot switching orionizing radiation is expected. The other criteria needed areits current handling capability and its turn-on time. Turn-onis especially important for CDM ESD because this type ofESD is a very fast event. Many clamps may not be able to re-spond quickly enough to provide protection against this typeof ESD event.

The design of the clamp needs to consider the clampingvoltage level and internal resistance. Clamping voltage de-fines what level of protection is provided to the dielectrics inthe process. This includes gate oxides and interlevel oxides.The internal resistance defines the voltage rise as a result of


the ESD current pulse and contributes to the power dissipatedin the clamp.

The thermal impedance of the camp to a heat sink (sub-strate) is also important because this determines the internaltemperature rise and ultimately the failure point of the clamp.A device with lower thermal impedance will have a higherESD threshold.

All of these can be combined into a figure of merit used todescribe an ESD structure. This figure a merit is the voltageper micrometer of width or voltage per square micrometerarea. The voltage listed here is the ESD threshold of thestructure per unit width or area. For example, if a structurewere listed as 10 V/m, it would require a 200-m deviceto achieve a 2000-V protection threshold. Providing the bestESD thresholds with the smallest devices requires selectionof devices with high ESD figures of merit.

It should be noted that these structures might not scalelinearly. Earlier, it was noted that some designs do not turnon uniformly. This effectively shrinks the available width orarea of the structure, making its figure of merit lower. Caremust be used when making a selected clamp larger than whenit was characterized.

VI. CONCLUSION

ESD protection is necessary for all circuits. Protection re-quires a systematic approach with a commitment from theentire organization. A dedicated team is required to driveESD improvement. ESD protection follows a two-prongedapproach to improve both the environments that parts arehandled in as well as the robustness of each part. The envi-ronment is improved by reducing the amount of charge devel-oped and by controlling the discharge of any charge that is de-veloped. Circuits are improved by designing elements betterable to handle the ESD currents and by providing an alter-nate path (a shunt) for the charge to travel as it passes throughthe part. This shunt protects the sensitive elements in the de-vice by clamping the voltage developed during the event anddiverting the current away from the core circuit. The ESDprogram is a dynamic system ever evolving as new tech-niques and technologies are developed. If it does not grow, itwill die. Only if the entire organization participates and sup-ports the program can the true benefits of higher yield, betterthroughput, and more satisfied customers be realized.

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James E. Vinson received the B.E.E. degreefrom Auburn University, Auburn, AL, in 1982,the M.S. degree in electrical engineering fromNorth Carolina State University, Raleigh, NC,in 1984, and the Ph.D. degree in electricalengineering from the University of CentralFlorida, Orlando, in 1998. His areas of studywere in radiation effects and electrical overstressfailure mechanisms in semiconductor devices.

In 1984, he joined Intersil Corporation (for-merly Harris Semiconductor), Melbourne, FL.

He is currently a Senior Principal Engineer in the Reliability Group. He haspublished numerous papers on reliability, failure analysis, and single eventphenomena, including two invited papers at international conferences.His responsibilities include reliability investigations and qualification,as well as failure analysis of both analog and digital circuits built usingbipolar and complementary metal–oxide–semiconductor technology formilitary and space customers. He serves as a Design Consultant for ESDand EOS robustness in new circuits. His current research interests includefailure mechanism modeling for failures caused by electrical overstress andelectrostatic discharge, as well as dielectric reliability.

J. J. Liou (Senior Member, IEEE) receivedthe B.S. (honors), M.S., and Ph.D. degrees inelectrical engineering from the University ofFlorida, Gainesville, in 1982, 1983, and 1987,respectively.

In 1987, he joined the Department of Elec-trical and Computer Engineering, Universityof Central Florida, Orlando, where he is nowa Professor. His current research interests aresemiconductor device modeling, simulation, re-liability, and characterization. He has published

four textbooks, more than 160 journal papers, and more than 110 papers(including 24 invited papers) in international and national conference pro-ceedings. He has held consulting positions with research laboratories andcompanies in the United States, Japan, Taiwan, and Singapore. He servesas a technical reviewer for various journals and publishers, and serves asa technical program committee chair or member for several internationalconferences. He has so far supervised and graduated 23 M.S. and Ph.D.students, all of whom are working in microelectronics companies, suchas Intel, Motorola, Lucent Technologies, and Intersil. In the summers of1992–1994, he was selected as a Member of Summer Research Faculty atthe Air Force Research Laboratory, Wright-Patterson Air Force Base, Ohio,where he conducted research on AlGaAs–GaAs heterojunction bipolartransistors. In the fall of 1997, he took a sabbatical leave and worked asa Visiting Professor at the Electrical Engineering Department, NationalUniversity of Singapore.

Dr. Liou has received eight different awards on excellence in teaching andresearch from the University of Central Florida. He is an associate editor fortheSimulationjournal in the area of VLSI and circuit simulation, and is a re-gional editor (in the USA) forMicroelectronics Reliability,an internationaljournal published by Elsevier.


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