Electrostatic Discharge Analysis of Multi Layer … Events/IEEESEMMLCCESD.pdfElectrostatic Discharge...

Cyrous Rostamzadeh, Senior IEEE Member, February 17, 2011

Electrostatic Discharge Analysis of Multi Layer Ceramic

Capacitors

Cyrous Rostamzadeh, Robert Bosch LLC – USAFebruary 17, 2011


Mr. Kimball WilliamsThank you for your Colossal Contributions and Dedication to

IEEE EMC Society.You have educated, trained, inspired, managed and encouraged

many of the EMC Engineers and Technicians in the SE Michigan area.

You are well respected by everyone throughout the EMC Society and Automotive Community.

I had the privilege to prepare this presentation, per your invitation, and I hope you will continue to guide the EMC Society long after your retirement from the Professional

Responsibilities as of February 2012, thank you.


Mr. Kimball Williams


A privilege for me to be educated, mentored, collaborated

with some of the finest minds of EMC…


Dr.Clayton Paul

Dr. Al Reuhli (IBM)


2001

1994

Dr. Howard JohnsonSignal Integrity


Professor Flavio CanaveroPolitecnico di Torino

Professor Christos ChristopouplosUniversity of Nottingham


Professor Sergio PignariPolitecnico di Milano

Professor Farhad RachidiSwiss Federal Institute of Technology (EPFL)


Professor James DrewniakProfessor James DrewniakMissouri ST UniversityMissouri ST University

Professor David PommerenkeProfessor David PommerenkeMissouri ST UniversityMissouri ST University

Dr. Bruce Archambeault Dr. Bruce Archambeault IBM, RTPIBM, RTP

Henry Henry OttOtt


Gordon Mapes, Phil Bator, Andy Macko, Mike Bosley,Arnie Nielsen,Gordon Mapes, Phil Bator, Andy Macko, Mike Bosley,Arnie Nielsen,Terry North, Victor Lau, Mark Steffka, Kimball Williams, Howard Terry North, Victor Lau, Mark Steffka, Kimball Williams, Howard Kendall, Don Seyerle, Rick Grunow, Jim Muccioli, Thorsten SchneiKendall, Don Seyerle, Rick Grunow, Jim Muccioli, Thorsten Schneider, der, Tom Livernois, Rick Lombardi, Richard Wiese, Bill Sperber, ScottTom Livernois, Rick Lombardi, Richard Wiese, Bill Sperber, Scott Lytle, Lytle, Keith Frazier, Lloyd Elsworth, Laura Ball, Larry Banasky, Larry Keith Frazier, Lloyd Elsworth, Laura Ball, Larry Banasky, Larry J. J. Boguslawski, Chingchi Chen, Samuel R. Connor, Prof. Marcello Boguslawski, Chingchi Chen, Samuel R. Connor, Prof. Marcello D'Amore, Dr. Phil Fanson, Bill Gilmore, Poul Anderson, Dr. FlaviD'Amore, Dr. Phil Fanson, Bill Gilmore, Poul Anderson, Dr. Flavia a Grassi, Dr. Todd Hubing, Dr. Chris Holloway, Professor Michel IaGrassi, Dr. Todd Hubing, Dr. Chris Holloway, Professor Michel Ianoz, noz, Dr. Thomas A. Jerse, Rob Kado, Richard Kautz, Jarek Tracz, JackDr. Thomas A. Jerse, Rob Kado, Richard Kautz, Jarek Tracz, Jack King, King, Joe Kramer, Roy Leventhal, Filippo Marliani, Scott Mee, Prof. AnJoe Kramer, Roy Leventhal, Filippo Marliani, Scott Mee, Prof. Antonio tonio Orlandi, Vipul Patel, Sreeniwas Ranganathan, Andrew J. Shune, JaOrlandi, Vipul Patel, Sreeniwas Ranganathan, Andrew J. Shune, James mes P. Spivey, John P. Sundeen, Daniel M Traynor, Dr. Al Wexler, Dr.P. Spivey, John P. Sundeen, Daniel M Traynor, Dr. Al Wexler, Dr. David David Hill, Dr. Perry Wilson, Doug Smith, Dr. Erping Li, Dustin WillimHill, Dr. Perry Wilson, Doug Smith, Dr. Erping Li, Dustin Willim, Mark , Mark Wisnewski, Matthew Yager, Paul Sarna, Jack Meyer, Mark MilesWisnewski, Matthew Yager, Paul Sarna, Jack Meyer, Mark Miles……


Back to basics…

Electric Currents


Electric Currents


Conduction Current

Displacement Current

Conduction Current & Displacement Current



Conduction Current >> Magnetic Field

Displacement Current >> Electric Field


Motivation and ObjectivesMulti layer Ceramic Capacitors are utilized for ESD

Protection of Connector I/O Pins→ Low Cost, Small Footprint (i.e., 0603 - X7R Class II) ideal for High Density Electronic Control Modules.

ButNeed to determine ESD Robustness or any Degradation due to ESD:

Pre_ESD and Post_ESD Impedance vs. Frequency Characterization. Optical Examination of Dielectric Structure after ESD Exposure.


Motivation and ObjectivesIn this Work

Electrostatic Discharge according to IEC61000-4-2Human Body Model up to 25 kV (100 pF , 2 kΩDischarge Network)MLCC (0603 package 1.6 mm X 0.5 mm) 680 pF and 10 nF (100 Volts), X7R Type II (-55oC -> +125oC)In addition, MLCC (0805 package)Discharge to PCB Mounted MLCCDischarge to Non-PCB Mounted MLCC


MLCC ProcessMLCC Process

Cyrous Rostamzadeh, Senior IEEE Member, February 17, 2011 tnAC rεε 0=


Ceramic MLCC TypesCeramic MLCC TypesC0G, X7R, X5R, X8R, X8LC0G, X7R, X5R, X8R, X8L

Class I – Most stable over Temperature and Voltage, & Frequency but Lowest Volumetric Efficiency (C0G or NPOC0G or NPO)

Class II – Lower Accuracy and Stability (+/- 15%, -55 0C –> 125 0C)X7RX7R

Class III – Highest Volumetric Efficiency, but Poor Accuracy & Stability


MLCC CharacteristicsMLCC Characteristics

An Electrical ModelAn Electrical Model……


1nF

10nF

Linear Scale

fCjX C π2

1=


1nF

10nF

Logarithmic Scale

fCjX C π2

1=


fCjX C π2

1=

What is in a ModelWhat is in a Model……C


RfCj

Z +=π21

Building a ModelBuilding a Model……

Heat


fLjRfCj

Z ππ

221

++=

Building a ModelBuilding a Model……

Heat


10nF

, |Z|

10nF

, |ESR|

fCj π21

fLj π2

Describing MLCC with MatlabDescribing MLCC with Matlab


10 mΩ

100 mΩ

1 nF Superior for freq. > 50 MHz

0603 (100 V) MLCC Characteristics


CjX−δ

Dissipation FactorDissipation Factor

ESR

Impedance PlaneImpedance Plane

QXESRDF

C

1)tan( === δ

DF = Resistive power Loss in ESR / Reactive Power oscillating inDF = Resistive power Loss in ESR / Reactive Power oscillating in CapacitorCapacitor

Loss


ESR is a function of FrequencyESR is a function of Frequency


Temperature FactorTemperature Factor


an ESD Eventan ESD Event……


ESD voltages as high as 30 kV has been observed in automotive environment.

ESD is rich in high-frequency (> 3 GHz) !ESD event can create currents in excess of 30 Amps!ESD currents can destroy IC’s, PCB traces and other

components.ESD can create time-varying Magnetic Field: 25 A/m.ESD can create time-varying Electric Field as high as: 10 kV/m.ESD can create Susceptibility Problems.


ESD phenomena involves Electrical & Thermal TransportsElectrical & Thermal Transports on

the Scale of nanometers (nm), Circuits and Electronics on the

Scale of micrometers (µm), Semiconductor Chip designs

range from picoseconds (ps) to microseconds (µs), Electrical

Currents of interest range from mA to 10’s of Amperes.

Voltages range from Volts to kiloVolts (kV). Temperatures

vary from room temperature to melting temperatures of

1000’s 0K…


Must Quantify the Scale in Space & TimeSpace & Time

ESD phenomena involves:

Microscopic to Macroscopic Scales.

ESD is a Thermo-Electric Transport of Material

Physics


Capacitance – ESD Charge Storage Element


⎟⎟⎠

⎞⎜⎜⎝

⎛−

=

21

114

rr

C πε

r1

r2

( ) pF 50C sphere,diameter

meter 1 toarea surfacea has humana pF, 111/1085.8 space, freefor and ,r

BodyHuman

122

≈⇒≈×=

×=∞⇒ −

rCmFif ε

Charge Storage CapacitanceCharge Storage Capacitance


FreeFree--Space CapacitanceSpace Capacitance

1 pFAn object a size of marble

700 µFEarth’s Capacitance

50 pFHuman Body Capacitance

In addition, we must consider In addition, we must consider Parallel Plate Parallel Plate CapacitanceCapacitance due to the proximity of an object due to the proximity of an object to the surroundingto the surrounding


100 pF

50 pF to infinity

50 - 100 pF

500 Ω to 10 kΩ

Self-Capacitance

Human Body Model (HBM)Human Body Model (HBM)



Therefore, the Capacitance of a Human Body is Therefore, the Capacitance of a Human Body is the Combination of Freethe Combination of Free--Space Capacitance Space Capacitance ++ParallelParallel--Plate Capacitance and can vary fromPlate Capacitance and can vary from

50 pF to 250 pF50 pF to 250 pF


kVtoVkR

pFC

HB

HB

HB

25 0 10 500

25050

=Ω−Ω=

−=

VHB



mJ 30 Energy

)000,25(1010021

21 2122

≈

×××== −CVEnergy

For a Human Body of 100 pF Capacitance, Charged Up

to 25 kVolt, Energy Released Per Discharge…….



The Discharge of a Human (via a small, hand-held metal piece) is basis for the current waveform most often used IEC 61000-4-2 standard.



GM3097 (July 2006)

Ford EMC_CS_2009

Chrysler CS-11809ISO 10605 (2001) & IEC 61000ISO 10605 (2001) & IEC 61000--44--22 Standards with some Modifications.

Ambient Temperature: 23 +/- 3oC Relative Humidity 20 to 40% Prefer 20oC and 30% RH.Contact Rise Time: tr < 1 nsAir Discharge Rise Time: tr < 20 ns. Discharge Networks: 150 pF/2 kΩ and 330 pF/2 kΩ

OEM ESD Test SpecificationsOEM ESD Test Specifications


ESD Impact…


IC’s fail due to Excessive Voltage or EnergyEnergy

Excessive VoltageExcessive Voltage can cause

Dielectric BreakdownDielectric Breakdown in IC’s

such as Oxide Barriers.


Excessive Energy can cause Thermal Failure

by “Melting Silicon” or “Metallization” of IC.

Melting Temperature of Silicon ~ 1,420Melting Temperature of Silicon ~ 1,42000CC

Melting Temperature of Metallization ~ 600Melting Temperature of Metallization ~ 60000CC


ESD Mathematical Analysis


⎟⎟⎠

⎞⎜⎜⎝

⎛ −•

⎟⎟⎠

⎞⎜⎜⎝

⎛+

⎟⎟⎠

⎞⎜⎜⎝

⎛

•+⎟⎟⎠

⎞⎜⎜⎝

⎛ −•

⎟⎟⎠

⎞⎜⎜⎝

⎛+

⎟⎟⎠

⎞⎜⎜⎝

⎛

•=4

3

3

2

2

2

1

1

1

1 exp

1

exp

1

)(τ

τ

ττ

τ

τ t

t

t

kit

t

t

kiti n

n

n

n

, exp/1

1

2

2

11 ⎟

⎟

⎠

⎞

⎜⎜

⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛−=

nnkττ

ττ

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛⎟⎟⎠

⎞⎜⎜⎝

⎛−=

nnk

/1

3

4

4

32 exp

ττ

ττ

τ4 = 58 nsτ2 = 1.7 nsI2 = 10.1 Ampn = 3τ3 = 6 nsτ1 = 1.3 nsI1 = 21.9 Amp


HBM ESD Time ConstantHBM ESD Time Constant

nspFCR

HB

HBHBHB

150 100 1500 =×Ω==

ττ

Similar to Thermal Diffusion Time of many

materials used in semiconductor industry


ESD is a Non-Linear Electro-Thermal Physical Event.

Very Difficult to Model Accurately.

Simple Linear Model is insightful.


ESD Modeling…


ESD Generator Model


VGen = 8 kVESD Generator Model


VHBM = 25 kVESD HBM Model


• VHBM = 25 kVESD HBM Model


ESD Protection Schemes


ESD Protection Devices1. TVS (Transient Voltage Suppressor)2. MOV Multilayer Zinc Oxide3. Diode4. Capacitor5. Spark Gap6. Filters7. Ferrites


Avoid Avoid Direct ConnectionDirect Connection from an exposed external from an exposed external point to an Integrated Circuit.point to an Integrated Circuit.

ESD Strategies

““E ~ 30 mJE ~ 30 mJ””


ESD Strategies

In no case should there be a directIn no case should there be a direct

connection from an Integrated Circuitconnection from an Integrated Circuit

to an exposed external point.to an exposed external point.


ESD Strategies

Divert or limit the ESD Energy awayDivert or limit the ESD Energy away

from Circuit Inputs using Filters orfrom Circuit Inputs using Filters or

Transient Suppressors.Transient Suppressors.


ESD Capacitor Mounting Strategy

• How far from Connector Pin…

• PCB layer stackup…

• Y-Connection…


ESD Capacitor Failure Mode

Voltage – Pressure

Current – Force

Dielectric Breakdown


SolutionSolutionESD Strategies


ESD Strategies SolutionSolution


Use LOW Capacitance Protection

ESD Strategies


TVS Diode family for ESD Protection of LIN BusTVS Diode family for ESD Protection of LIN Bus


TVS Diode Bias ImpactTVS Diode Bias Impact


IHF


IC absorbs a % of ESD Current!IC absorbs a % of ESD Current!


l > λ

ESD““Fast Transient ElectromagneticsFast Transient Electromagnetics””

Structure “Electrically Large”

Frequency ~ 3 GHz

Field Collapses to 25 Field Collapses to 25 -- 40 V within 40 V within ““50 ps 50 ps –– 5 ns5 ns””


High Frequency Design Practice ESD


Spark Gap “Protection Mechanism”


Spark Gap


Vs/m 105-2 Constant Process

)()()(

length arc d Process; SurfacePressure Normalat Vs/m 108 Constant

)()()(

:Process" Discharge Gas" LawTopler

4-0

4-0

×≈=

⋅⋅

=

=×≈=

⋅⋅

=

∫

∫

Surfacea

dIdatUtI

Toplera

dIdatUtI

M

t

surfM

arcsurf

T

t

gasT

arcgas

ζξ

ζξ

Spark Gap Physics


PSPICE Model for Spark Gap


0201 0402 0603 0805 1206 1210 1812 1825 2220 2225

MLCC Package SizeMLCC Package Size


06030603


ESD Capacitors ESD Capacitors –– Mounting StrategyMounting Strategy


Strategic Insertion Topology of MLCC ConceptStrategic Insertion Topology of MLCC Concept……

MurataMurataTDKTDK

EPCOSEPCOS


FlashFlash

µµCC

RegulatorRegulator

IGN.IGN.

+5 V+5 V

ESD Capacitors – Mounting Strategy


TVS Diode Mounting Strategy


ESD Capacitors Mounted @ PCB Connector Pins


ESD Event (High Frequency Current through ESD MLCC)

PCB Mounted MLCC Exposed to HBM ESD


Connector Area ESD Capacitors


Electrical Characteristics


180 pF/50V, C0G – X7R


1 nF/50 V, C0G – X7R


X7R


ESR - function of Frequency


MLCC Supported via 2 cm2 cm Long Wires Exposed to HBM ESD


MLCC GeometriesMLCC Geometries

2.ESD Enhanced

1.Standard MLCCplates do notoverlap over

indicated regions


When not intersecting When intersecting

The Electric Flux Density is higher on the terminal electrode edge.


Departure from a Simple MLCC Electrical Model…

0.1 x 1012 Ω1.471 x 1012 ΩR3

34.57 Ω753.73 ΩR2

0.329 kΩ5.15 kΩR1

4.10 pF4.10 pFC2

10 nF680 pFC1

1.730 nH931 pHL2

91 pH49 pHL1

10 nF680 pFNOMINALVALUES @ 1 kHz

C

ESR

ESL


R3 R3 -- InsulationInsulation / Leakage Resistance

0.1 x 1012 Ω1.471 x 1012 ΩR3

34.57 Ω753.73 ΩR2

0.329 kΩ5.15 kΩR1

4.10 pF4.10 pFC2

10 nF680 pFC1

1.730 nH931 pHL2

91 pH49 pHL1

10 nF680 pFNominalValue @ 1 kHz

C

ESR

ESL

1.471 x 1012 Ω


L1 is the series parasitic inductance associated with plate connections.L2 is the equivalent series inductance. It is also known as LESL. R1 is the equivalent series resistance (also known as RESR) and represents the actual Ohmic resistance of the plates. This value is typically very low. It causes a power loss of I2R1. Its contribution to the total dissipation factor is

D1 = 1/ωR1C1


C1 is the nominal capacitance.

R2 is the dielectric loss: A parallel resistance arising from two phenomena; molecular polarization and interfacial polarization (dielectric absorption). Dielectric loss is a complex phenomenon that can change with frequency in most any manner that is not abrupt. Its contribution to the total dissipation factor can be approximated by

D3 = 1/(ωR2C2)


C2 is the parallel dielectric absorption capacitor.R3 is the leakage resistance, or insulation resistance: A parallel resistance due to leakage current in the capacitor. This value is typically very high. It causes a power loss of V2/R3. Its contribution to the total dissipation factor is

D2 = 1/(ωR3C1)


Z

ESR

10nF/50V – X7R


ESR

Z 680pF/50V – X7R


MLCC Pre-ESD & Post ESD

ImpedanceCharacterization


Pre-ESD


Pre-ESD, Post-ESD

“R” Behavior

10nF


“R” Behavior

Pre-ESD, Post-ESD680pF

600 600 ΩΩ


Post-ESD680pF, 10nF


Capacitor ratio: 10 nF / 680 pF = 14.7

Insulation resistor ratio:

0.1 x 1012 Ω / 1.47 x 1012 Ω = 1/14.7

680 pF vs. 10 nF

10 10 nFnF 680 pF680 pF


Same Package Size, i.e., 0603Same Package Size, i.e., 0603

CC , , Insulation RInsulation R

C = 680 pF, R = C = 680 pF, R = 1.47 x 1012 ΩC = 10 C = 10 nFnF, R = , R = 0.1 x 1012 Ω


Post-ESD, R3 - Leakage Resistance ‘Degradation’

13

31

21~

|| :

CRf

RCsFrequencielowAt

π

Pre-ESD: C1 = 680 pF, R3 = 1.471 x 1012 ΩPost-ESD: C1 = 680 pF, R3 = 500 Ω (40 Hz – 200 kHz)Pre-ESD: C1 = 10 nF, R3 = 0.1 x 1012 ΩPost-ESD: C1 = 10 nF, R3 = 500 Ω (40 Hz – 20 kHz)


Post-ESD5.7nF, 0805


ESD ImpactESD Impact


MLCC Post ESD Optical Imaging


MLCC X7R Grind and PolishStep 1 Voids Present

MLCC X7R Grind and Polish Step 1Voids, Delamination, and StressCracks present – Polarized light.


MLCC X7R Grind and PolishStep 2 Void size increasing

Delamination and Stress Cracks Present – Polarized Light.

MLCC X7R Grind and Polish Step 2Voids, Delamination, and Stress

Cracks and Edge Cracks are present – Polarized light.



Delamination and Stress Cracks Present – Polarized Light.

MLCC X7R Grind and Polish Step 3Voids, Delamination, Note: Residual

Stress in material around Void.– Polarized light.



Delamination - Polarized Light.

MLCC X7R Grind and Polish Step 4Voids, Delamination, and Stress Cracks present – Polarized light.


MLCC X7R Grind and PolishStep 5 Void size increasingDelamination – Bright Field.

MLCC X7R Grind and Polish Step 5Voids, Delamination, Void Size

Increasing – Polarized light.


MLCC X7R Bubble Discovered end cap


MLCC C0G Void / Micro Cracks MLCC C0G Void / Micro CracksPolarized DIC


Z

ESR


ESR

Z


Conclusion0603 style MLCC’s exposed to +/- 15 kV ESD, develop

permanent damage to their dielectric material (severe leakage, low frequency resistor type behavior up to 200 kHz).

0805 style MLCC’s in excess of 10 nF, will withstand ESD damage.

A parallel combination of low capacitance TVS or MOVwith a 10 nF, 0603 MLCC an “EMC design guideline” to perform as an RF filter and ESD protection @ module connector pins.


Thank you for yourThank you for your

ParticipationParticipation

Electrostatic Discharge Analysis of Multi Layer … Events/IEEESEMMLCCESD.pdfElectrostatic Discharge...

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