Electronic System Design GroupInstrumentation DepartmentRob HalsallRutherford Appleton Laboratory19...
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Electronic System Design Group Instrumentation Department Rob Halsall Rutherford Appleton Laboratory 19 July 2002 Electronic System Design Group CMS Tracker FED Update 25th July 2002 09:00 - 12:00
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Electronic System Design GroupInstrumentation DepartmentRob HalsallRutherford Appleton Laboratory19 July 2002 Front End Module Layout 9U Envelope - Active Components Opto Rx NGK 45 mm Double Sided Single Sided 130 mm 27 x 27 mm 12 x 12mm 9 x 9 mm 5 x 3 mm 33 x 40 mm FPGA XC2V1000- XC2V3000 FG676 FPGA XC2V40 CS144 ADC AD9218 ST48 DIFF OP-AMP AD9218 RM8 N.B. No Passives Shown
Transcript of Electronic System Design GroupInstrumentation DepartmentRob HalsallRutherford Appleton Laboratory19...
Electronic System Design GroupInstrumentation Department Rob HalsallRutherford Appleton Laboratory 19 July 2002
Electronic System Design Group
CMS Tracker FED
Update
25th July 200209:00 - 12:00
Electronic System Design GroupInstrumentation Department Rob HalsallRutherford Appleton Laboratory 19 July 2002
0V
CMS Tracker FEDFunctionality
TTC
Front End FPGA
12x Opto Rx
PD
Arr
ay
4x ProgDelay
1
Synch &Processing
TTCrx
FE 1
9
VME
QDR SSRAM2
5V 3.3V 1.5V
DualADC
3.3V
DualADC
1
6
0V
Front End FPGA
12x Opto Rx
PD
Arr
ay Synch &Processing
FE 88 Dual
ADC
DualADC
85
48
12 way FR
Readout &Synch Control
ASIC
ASIC
ASIC
FPGA
12 way FR
12
1
1
TempSense
TempSense
4x ProgDelay
FPGA
1
4
4x ProgDelay FPGA
4x ProgDelay FPGA
1
4
TempSense
TempSense
3.3V 3.3V
1.5V5V
-5V
spare
PD
Boundary Scan SystemACE
Hot swapPSU
&DC-DC
Back End FPGA
TempSense
12x trim dac
12x trim dac
BufferSwitchMatrix
Compact Flash
VME64xInterface
FPGA
Test Connector
SWSW
Hot swap cycle
Live extract request
E2PROM
Vref
DAQ
TTS
Spare
1.5V
3.3 V5.0 V
2.5V
-5.0V
2.5V
12
1
Vref
Electronic System Design GroupInstrumentation Department Rob HalsallRutherford Appleton Laboratory 19 July 2002
Front End Module Layout9U Envelope - Active Components
Opto Rx NGK
45 mm
Double SidedSingle Sided
130 mm
27 x 27 mm
12 x 12mm
9 x 9 mm
5 x 3 mm
33 x 40 mm FPGAXC2V1000-XC2V3000FG676
FPGAXC2V40CS144
ADCAD9218ST48
DIFF OP-AMPAD9218RM8
N.B. No Passives Shown
Electronic System Design GroupInstrumentation Department Rob HalsallRutherford Appleton Laboratory 19 July 2002
CMS Tracker FEDBoard Layout Overview
ROFPGA
VMEFPGA
FED
Channel Link800MByte/s
DAQ
TTS
Electronic System Design GroupInstrumentation Department Rob HalsallRutherford Appleton Laboratory 19 July 2002
CMS Tracker FED System OverviewBack End Layout Preliminary
mR
mR
mRmR
mRmRFET
3V3
FET5V0
FET12V0
VMEJ1
VMEJ2
VMEJ0
2250
122
501
2250
122
501
2250
122
501
2250
122
501
2250
1
244
244
5906
5906
DC-DC1.5V / 20ASVP SVP
SVP
SVP
SVP
VMEFPGA
BE
FPG
A
Pin Diode QDRTTCrx
QDR
40240 4043
4043
4043
FUSE
7073 4002
40027073
ISOLATED +5V IN
ON+5V IN
SYSACE
COMPACTFLASH
XC18V04
X24165
DC-DC-5V / 4A
mRmRmR
FET1V5 • NB Single sided only shown
Electronic System Design GroupInstrumentation Department Rob HalsallRutherford Appleton Laboratory 19 July 2002
CMS Tracker FED System OverviewBoard Layout
FED
mR
mR
mR
mR
mR
mR
mR
mR
mRFET3V3
FET1V5
FET5V0
FET12V0
VMEJ1
VMEJ2
VMEJ0
2250
122
501
2250
122
501
2250
122
501
2250
122
501
2250
1
244
244
5906
5906
DC-DC1.5V / 20ASVP SVP
SVP
SVP
SVP
VMEFPGA
BE
FPG
A
Pin Diode QDRTTCrx QDR
40240 4043
4043
4043
FUSE
7073 4002
40027073
ISOLATED +5V IN
ON+5V IN
SYSACE
COMPACTFLASH
XC18V04
X24165
DC-DC-5V / 4A
