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04.10.08

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t e c h v i e w

04.10.08 ELECTRONIC DESIGN

MicroSemi’s PD64001 PSE controller sup-ports current levels up to 720 mA (36 W atthe input to the CAT5 cable, 30 W at the PD,assuming 50 V at the PSE) using 802.11attwo-event classification. Designs requiring upto 60 W can use a four-pair architecture usingtwo devices. The PD64001 was sampling inFebruary, and it will be in production by theend of the quarter.

The Akros AS1135 is a PD controller imple-menting the two-event physical-layer classifi-cation functionality of the 802.3at standard.Two-event classification allows the PD torecognize whether it is connected to Type1 (802.3af/13W) or Type 2 (802.3at/30W)power sourcing equipment. It also informs

the PSE that it’s safe to increase power deliv-ered to the PD from 13 to 30 W.Furthermore, the AS1135 provides “AT

Detect” functionality on a logic output pin.This enables the system microcontrollerto self-configure the networked appliancebased on the power delivery capability of thenetwork. It’s possible to set the switchingfrequency of the integrated dc-dc controlleranywhere between 100 and 500 kHz. It iscurrently sampling as well.

The availability of real PoE Plus chips posesat least two interesting questions. The firstis how enthusiastic PD OEMs will be aboutimplementing a scheme that requires them towrite additional application software to com-municate status information to the PSE—forexample, “My user will/will not require video-screen operation for this call, so give me myfull power allotment now.” The second ishow enthusiastic IT managers will be aboutsupporting a phone system whose powercapabilities were sized based on statisticalanalyses of usage.

Answering the first question, AkrosCEO Simon Prutton says that the company isdealing with video-over-IP OEMs that

are now developing products that will usethe new chips. With respect to the second,he says that Ethernet switch makers are goingforward with product development, althoughthey seem to be hedging their bets bybuilding in a robust safety factor when theysize their power supplies.

DON TUITE

AKROS SILICON • www.akrossilicon.comMICROSEMI • www.microsemi.com

ED ONLINE 18558

SERDES IP Releases Tackle Top SpeedsHigh-speed design and serial buses used for chip-to-chip communications seem togo hand in hand nowadays. Whether you’re talking signal integrity, printed-circuit board (PCB) routability, or a slew of other factors, it just makes sense. Therefore, theready availability of reliable serializaer/deserializer (SERDES) intellectual property (IP) is imperative.

Avago SERDES Offerings From eSilicon

Protocol standards Data rate(Gbits/s)

90 nm 1 (G, G-OD)

65 nm 2 (G+, G+OD)

Gigabit Ethernet 1.25 * *

PCI Express Gen 1 and 2 2.5 and 5.0 * *

10GBase-CX4 3.125 (x4 lanes) * *

XAUI/10GBase-KX4 3.125 (x4 lanes) * *

CEI-6G6.25 (LR and SR;

MR) * *

XFI (10-Gbit Ethernet) 10.3125 *

Fibre Channel(8x, 4x, 2x, 1x)

1.0626, 2.125,4.25, 8.5

* *

Fibre Channel(10GFC Serial) 10.51875 *

Chip-to-Chip/Backplane 5.0, 6.25, 7.5,

10.3125*

1. Frequencies higher than 6.25G require G-OD process 2. Frequencies higher than 7.5G require G+OD process

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Tundra Semiconductor’s Silicon Logic Engineering (SLE)division addresses this need with an Interlaken IP core capableof 150 Gbits/s(see the figure). Originally developed by Cortina

Systems, the Interlaken protocol is a royalty-free specificationthat combines the SPI-4.2 and XAUI architectures, which haveseen high adoption rates in networking systems.

SLE’s core is fully scalable, making it a good fit for future net- work equipment designs, such as switches, routers, and storagedevices. Each one of its 24 lanes is capable of 3.125 to 6.375Gbits/s. When all 24 lanes are chugging at full speed, the raw

data rate equals just over 150 Gbits/s, which is the fastest ratepossible according to SLE.

Other features include support for up to 64k channels, a con-

tinuous meta frame for programming frequency allowing forlane alignment, and 64B/67B data encoding and scrambling.SLE’s Interlaken IP core should pop into just about any ASIC,and it works with off-the-shelf SERDESs from most vendors.It’s available through SLE’s sales channel.

If network storage is your game, then you realize that data bandwidth and processing expectations have skyrocketed over

the past few years, with power con-sumption and form factor expected toremain constant. Again, the trend is toinclude a high-speed SERDES to helpmeet these requirements.

Recently, eSilicon partnered with Avago to license its embedded SERDEScores targeted at the network storage,communications, and high-perfor-mance computing markets. The multi-tude of SERDES offerings includes 90-and 65-nm CMOS processes availablefrom TSMC.

This sixth-generation suite of offer-ings has been road tested in many products. Avago offers its cores at ratesfrom 1.0625 to 10.51875 Gbits/s, andthe company claims they provide strongsignal integrity and jitter performance.Other features include an adaptive feed- back equalizer in the receiver, program-mable transmitter pre-emphasis, and a bit error rate of less than 10-17. A broadselection of Avago SERDES cores overa range of data rates and protocol stan-dards is available from eSilicon(see thetable). DANIEL HARRIS

SILICON LOGIC ENGINEERING

siliconlogic.com/asic_fpga_interlaken_core.aspESILICON

esilicon.com/offerings/avago.phpED ONLINE 18559

TX

Data

Control

Debug

Flow control

Data

Control

Flow control

Statistics

Format

Statistics

Debug

MUX

Stat isti cs

Format MUX

Debug

Flow-controlformat

Flow-controlformat

Lane 0Lane 1Lane 2

… … …

Lane N

Lane 0Lane 1Lane 2

…

Lane N

TX SERDES data 0TX SERDES data 1TX SERDES data 2

TX SERDES data N

Flow-control clkFlow-control syncFlow-control data

Debug

Cong

Interrupt Cong

RX

RX SERDES data 0RX SERDES data 1RX SERDES data 2

RX SERDES data N

Flow-control clkFlow-control syncFlow-control data

SLE’s InterlakenIP core scalesfrom one to 24lanes, with eachlane capableof raw datarates between3.125 and 6.375Gbits/s.

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