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ElectromagneticInterference Stress Testing PhD. Thesis, 1998 Leesa Marie MacLeod Department of Electrical and Computer Engineering University of Toronto Abstract An electronic system subjected to the stress of electromagnetic interference may fail to operate normally. just as it may fail under the stress of high temperam. Elevated temperature has traditionally been used as a stress test to "bum-in" electronic systems. The premise is that design flaws and substandard components that would eventually cause a system to fail will cause failure sooner under the burden of a stress test In this way sys- tems that are sub-standard can be eliminated from the production stream. In this work, electromagneticinterference. rather than elevated temperature, is used as the stress. The focus of this work is on measuring and interpreting the electromagnetic inter- ference required to cause failure as a function of interference frequency and applicator position over the target printed circuit board. In order to measure this failure threshold, an electromagnetic interference stress testing appantus is designed, including the required hardware and software. The applicator characteristicsand the program used to diagnose failures are found to be the key aspects of a successfulstress test The interpretationof the measured failure threshold is aided by theory developed in this work The theory predicts the dependence of the induced voltage at various positions along a printed circuit board track on the interference frequency and the applicator position. This theory can be used to predict the position on the target track of the device most likely to be causing the failure. Experiments validate both the stress testing apparatus and the theory used to locate failures. Three failures are studied in this work The fmt failure occurs due to rectifca- tion at a tri-stated driver. The second is a failure due to a weak componellt: a memory chip functions normally without stress, but retrieves incorrect data when subjected to elec- tromagnetic interference. The final failure is due to timing violations caused by delays induced by electromagnetic interference. For each of these failures, the theoretical predic- tion of frequency and applicator position effects is verified by comparison with measure- ments. The combination of theory and experiment described above validates the use of electromagneticinterference as a stress test Such a test can be used to locate faulty com- ponents and design flaws on printed circuit boards.

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Page 1: Electromagnetic Interference Stress Testing · 2020. 4. 7. · Electromagnetic Interference Stress Testing PhD. Thesis, 1998 Leesa Marie MacLeod Department of Electrical and Computer

Electromagnetic Interference Stress Testing

PhD. Thesis, 1998 Leesa Marie MacLeod

Department of Electrical and Computer Engineering University of Toronto

Abstract

An electronic system subjected to the stress of electromagnetic interference may fail to operate normally. just as it may fail under the stress of high temperam. Elevated

temperature has traditionally been used as a stress test to "bum-in" electronic systems. The premise is that design flaws and substandard components that would eventually cause a system to fail will cause failure sooner under the burden of a stress test In this way sys-

tems that are sub-standard can be eliminated from the production stream. In this work, electromagnetic interference. rather than elevated temperature, is used as the stress.

The focus of this work is on measuring and interpreting the electromagnetic inter-

ference required to cause failure as a function of interference frequency and applicator position over the target printed circuit board. In order to measure this failure threshold, an

electromagnetic interference stress testing appantus is designed, including the required hardware and software. The applicator characteristics and the program used to diagnose failures are found to be the key aspects of a successful stress test The interpretation of the

measured failure threshold is aided by theory developed in this work The theory predicts the dependence of the induced voltage at various positions along a printed circuit board track on the interference frequency and the applicator position. This theory can be used to

predict the position on the target track of the device most likely to be causing the failure. Experiments validate both the stress testing apparatus and the theory used to locate

failures. Three failures are studied in this work The fmt failure occurs due to rectifca- tion at a tri-stated driver. The second is a failure due to a weak componellt: a memory chip functions normally without stress, but retrieves incorrect data when subjected to elec-

tromagnetic interference. The final failure is due to timing violations caused by delays induced by electromagnetic interference. For each of these failures, the theoretical predic-

tion of frequency and applicator position effects is verified by comparison with measure- ments.

The combination of theory and experiment described above validates the use of electromagnetic interference as a stress test Such a test can be used to locate faulty com- ponents and design flaws on printed circuit boards.

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Acknowledgments

I would like to thank my supervisors, Professor Keith Balmain and Professor Saf- wat Zaky, for sharing their expertise with me and for encouraging me to think clearly and to write clearly. I also wish to thank the staff of the Electromagnetics Group: Gerald Dubois, Peter Kremer, and Bibiana Pang. Peter Kremer contributed greatly to the success of this work by constructing the scanner hardware. Thanks also to Peter Pereira of the Computer Group for information on the 68000 board and to Jaro Pristupa of the Electron- ics Group for help with the HSpice sohare . For sharing with me their thoughts on mat- ters technical and non-technical. I thank my fellow graduate students including Peter Aaen, Ramesh Abhari, Tmg Chu. Mina Danesh, Karam Noujeim. Tien Pham. Micah Stickel, and Xidong Wu. I gratemy acknowledge fmancial support from the Natural Sci- ences and Engineering Research Council of Canada, the NSERCIBell CanadaiNortel Industrial Research Chair in Electromagnetics, the Information Technology Research Cenh-e, and the University of Toronto. Finally, I would like to thank my parents, John and Carol MacLeod, and my soon-to-be-husband, Karam Noujeim, for their constant support and encouragement

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Table of Contents

............................................................ Abstract ii ... .................................................. Acknowledgemenh m List of Acmnyms .................................................... vi

Chapter 1 INTRODUCTION .................................................... 1

............................................... 1.1 Literature Review 2 . 1.1.1 Susceptibility testing present practices .......................... 2

1.1.2 Susceptibility of individual components ......................... - 2 1.1.3 Stress testing and reliability .................................... 5

.................................. 1.1.4 Electromagnetic stress testing 6 1.1.5 University of Toronto susceptibility scanner ....................... 7

............................................. 1.2 Research Objectives 8 ................................................ 1.3 Thesis Structure 9

Chapter 2 ............................................ SCANNER APPARATUS 10

.................................. 2.1 Susceptibility Scanner Hardware 11 ............................ 2.2 Susceptibility Scanner Control Software 13

................................................... 2.3 Applicator 15 .................................... 2.3.1 Applicator figures of merit 15

........................................ 2.3.2 Capacitive applicator 16 2.3.3 Coaxial inductive applicator .................................. 18

................................... 2.3.4 Planar inductive applicator 19 2.3.5 Planar inductive applicator characteristics ........................ 20

.................................................. 2.4 Typical EUT 27 ................................................. 2.4.1 Hardware 27

........................................ 2.4.2 Diagnostic routines -29 2.5 Susceptibility Maps of the EUT ................................... 30

.................................................. 2.6 Conclusions 32

Chapter 3 FREQUENCY AND COUPLING POSITION EFFECTS .................. 33

................................................ 3.1 Static Analysis 34 .......................................... 3.1.1 Inductive coupling 34

3.1.2 Distributed source (inductive coupling) .......................... 36 3.1.3 Thevenin equivalent approach (inductive coupling) ............... -37 3.1.4 Capacitive coupling ........................................ -39 3.2 Dynamic Analysis ............................................. 40 3.2.1 Inductive coupling .......................................... 40 3.2.2 Capacitive coupling ......................................... 43 3.3 Digital Component Equivalent Impedances ......................... 44 3.3.1 Receiver .................................................. 44 3.3.2 Driver ................................................... -44 3.4 Conclusions .................................................. 47

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Chapter 4 ..................................... SIGNAL HANDOVER FAILURE 48 .................................... 4.1 Failure as Observed on EUT -48

4.2 Frequency and Applicator Position Effects on EUT Failure Threshold .... 50 ................................................... 4.2.1 Theory 51

4.2.2 Measurement ............................................. -55 4.2.3 Comparison of theory with measurement ........................ 56

.................................................. 4.3 Test Board -57 4.4 Failure Mechanism ............................................. 62

................................................. 4.5 Conclusions -64

Chapter 5 WEAK MEMORY CHIP ............................................. 65 5.1 EUT Memory Configuration .................................... -65 5.2 Inducing Weakness in a Memory Chip ............................. 68 5.3 Use of a Susceptibility Scan to Detect a Weak Chip ................... 70 5.3.1 Theory ................................................... 71 5.3.2 Measurement .............................................. 73 5.3.3 Comparison of theory with measurement ........................ 75 5.4 Use of Lowered Supply Voltage to Detect Weak Memory Chip ......... 77 5.5 Additional Failure Characteristics ................................. 78

................................................. 5.6 Conclusions -79

Chapter 6 EMI-INDUCED DELAY IN DIGITAL CIRCUITS ....................... 80 6.1 Introduction .................................................. 80 6.2 General Procedure to Find EMI-Induced Delay ...................... 81 6.2.1 Output slew nte dependence on input slew rate ................... 83 6.3 Induced Delay Example: Capacitive Coupling ....................... 84 6.3.1 Frequency domain derivation of node 4 voltage ................... 84 6.3.2 Time domain derivation of node 4 voltage ....................... 86 6.3.3 Induced delay at node 4 ...................................... 87 6.3.4 Induced delay at node 6 ...................................... 90 6.4 Induced Delay Example: Inductive Coupling ........................ 91 6.4.1 Static voltages ............................................. 93 6.4.2 Measured and predicted waveforms at node 4 ..................... 95 6.4.3 Measured and predicted waveforms at output ..................... 99 6.5 Induced Delay: HSPICE Comparison ............................. 101 6.6 Conclusions ................................................ 1 0 2

CONCLUSIONS ................................................... 103

APPENDIX A ..................................................... 105 APPENDIX B ..................................................... 107 APPENDIX C ..................................................... 108 REFERENCES .................................................... 112

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Lit of Acronyms

CMOS CPU DRAM DRC EMC EM1 EOS EPROM ESD EUT LANCE MOS PAL PC SPICE TEM TIZ UART

Page of fvst use

complementary MOS ................................................................................. 4 central processing unit .......................................................................... 27 dynamic random access memory .............................................................. 9 dynamic random access memory controller ............................................... 7 electromagnetic compatibility .................................................................. 1 electromagnetic interference ...................................................................... 1 electrical overstress ................................................................................... 68 erasable programmable read-only memory .............................................. 27

electrostatic discharge ................................................................................. 3 equipment under test ................................................................................... 2

local area network controller Ethernet ...................................................... 48 metal-oxide-semiconductor ......................................................................... 3 programmable array logic ......................................................................... 48 personal computer (hosting susceptibility scanner software) ................... 11 simulation program with integrated circuit emphasis ............................... 44

transverse electromagnetic .......................................................................... 2 transistor-transistor logic ............................................................................ 3 universal asynchronous receiver-transmitter ........................................ 13

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Chapter 1

INTRODUCTION

Electromagnetic compatibility (EMC) is "the ability of a device, equipment, or system to function satisfactorily in its electromagnetic environment without introducing intolerable electromagnetic disturbances to anything in that environment" [I]. In order for

a device or system to achieve EMC, it must be immune (i.e. not susceptible) to reasonable levels of electromagnetic interference (Em. Standard tests [2] exist to evaluate the sus-

ceptibility of a system*. It would be useful to know not only whether the entire system is susceptible, but also which part of it is most susceptible (i.e. it would be useful to have a susceptibility map showing the regions of the printed circuit board that are most suscepti- ble to EMI). This parallels the approach in electromagnetic emissions testing in which the entire system is tested, and in addition each printed circuit board in the system is scanned

using EMSCAN [3] to create an emissions map showing which parts of the board are con- tributing most to the emissions.

A printed circuit board susceptibility scanner can be used to map the susceptibility of the board to electromagnetic interference, as described by Zaky, Balmain, and Dubois

[4,5], Laurin [6], and Wallace [7]. The susceptibility map shows how the susceptibility of the printed circuit board varies with the position at which the EM1 couples to the board. In [8] a weak component" was found to cause board failures during a susceptibility scan. That is, it was found that an electronic system subjected to the stress of electromagnetic interference may fail to operate normally, just as it may fail under the traditional envimn-

mental stress of high temperature. The use of a susceptibility scanner as an environmental

stress tester is explored in this thesis. The objective of this work is to develop a tool for analyzing (i) the susceptibility of

a printed circuit board to localized electromagnetic interference, and (ii) the dependence

of the susceptibility map on board faults. This research includes a study of coupling

mechanisms and board failures. Since this is a new yea of focus, the body of literature related to it is quite small, as summarized in Sec. 1.1. The focus of the research is explained in Sec. 1.2, and the thesis structure is outlined in Sec. 1.3.

*In 6e remainder of this document 'susceptible" means susceptible to elemmagnetic interfererre. **A weak (marginal, walking-wounded) mmponent is one that is substandard in some way yet functions m d y in a strw-free envimnment.

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1.1 Literature Review

In this section, literature related to the mearch objective is summarized. Standard tests used to evaluate the level of susceptibility of a system are described in Sec. 1.1.1.

Research on the susceptibility of electronic components is summarized in Sec. 1.1.2. Lit- erature related to environmental stress testing in particular and reliability issues in general is outlined in Sec. 1.1.3. In Sec. 1.1.4 the small body of literature directly related to the combination of electromagnetic susceptibility testing and environmental stress testing is

reviewed. Finally, Sec. 1.1.5 presents the history of the susceptibility scanner at the Uni- versity of Toronto.

1.1.1 Susceptibility testing - present practices

In the past, the electromagnetic compatibility of equipment intended for civilian

use has been regulated in terms of emissions but not immunity (although some companies have in-house immunity guidelines)*. The European EMC d i i t i v e [2], however, does

include electromagnetic immunity requirements. The equipment under test (EUT) is placed in a shielded room or anechoic chamber and is subjected to radiated fields from a source antenna. Alternative methods of generating the required electromagnetic interfer- ence, including TEM cells and open antenna ranges, are permitted [2]. The interference consists of a 30 MHz to 1 GHz carrier which is 80% amplitude modulated at 1 kHz The carrier amplitude is 3 Vlm for a typical commercial environment and 10 Vlm for a typical industrial environment. The standard specifies four classes of test results:

1) normal performance, 2) self-recoverable degradation or failure, 3) degradation or failure requiring operator intervention to remedy, and 4) permanent degradation or failure.

These susceptibility tests do not address which part of the EUT is most susceptible or what

the failure mechanism is; thus they may not provide sufficient information for better design of the EUT or more stringent component quality requirements.

1.1.2 Susceptibility of individual components

The effect of EM1 on digital integrated circuits has been a subject of investigation

for several decades. In 1979 a special issue of the IEEE Transactions on Electromagnetic Compatibility was devoted to RF interference effects in semiconductor discrete devices and jntegrated circuits [lo]. The papers in the special issue dealt primarily with computer

*Military EMC starukrds do include suscqxibility requirementr [91.

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modeling of rectification effects in bipolar transistors. Larson and Roe modified a transis-

tor model to allow computer simulation of rectification effects [l I]. A companion paper by Whalen et aL used this model to predict EMI effects in lTL digital circuits 1121. In [13], Richardson developed a transistor model used to predict low-level, low-frequency rectification effects.

In [14], Alkalay and Weiner used computer simulations to study the EMI-induced change in propagation delay through a ITL digital circuit. They found that the induced delay is a strong function of the EMI frequency, amplitude, and phase. The authors do not interpret their fmdimgs, but do state that "future work will be d i i t e d at developing a rela- tively simple model to predict these effects." A similar study on differential line receivers by Dave and Weiner [IS] found that shifts in input threshold voltage, propagation delays,

acd transitions to incorrect states were caused by differential-mode interference, but the receiver was relatively immune to common-mode interference.

The aforementioned references focus on bipolar junction transistors. The effect of

EM1 on MOS (metal-oxide-semiconductor) devices was studied somewhat later. In 1981 Roach [I61 reported that the susceptibility of an NMOS memory is very dependent on the

memory operating conditions. Kenneally et aL studied the susceptibility of MOS ESD (electrostatic discharge) protection devices using both experiments and computer simula- tions, and found that susceptibility with the ESD protection circuitry may be different than

the susceptibility without protection [17]. In [18] Tront used computer simulations to observe the EM1 susceptibility of MOS digital integrated circuits as a function of interfer- ence frequency, amplitude, and phase. Tront observed dvee effects, at increasing levels of

interference: change in delay time of the circuit, multiple logic tmsitions when a single transition is expected, and failure to change logic states.

Two interesting papers regarding susceptibility of digital systems were published in the mid-1980's. In [19]. experimental investigations by Rhoades indicate that upsets can be caused by digital equipment that meets radiated emissions requirements but inter- feres with a susceptible system in close proximity to it. Everett and Everett [20] tested three microprocessors for radiated susceptibility to sinusoidal interference in the fre-

quency range 300 MHz - 1 GHz. The observed failures included inconect data and wild running displays.

In the early to mid 1990's. literature relating to EM1 susceptibility was primarily the work of two groups. At the University of Toronto investigations were canied out by Laurin [6]. Wallace [7], and Chappel [21] under the supervision of K. G. Balmain and

S. G. Zaky. Lul in explored a unique EMI-induced failure associated with crystal oscilla- tors in 1221. In [23] he combined results from a method-of-moments electromagnetic sim-

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ulator with a circuit simulator to study EM1 effects on digital circuits. Finally, in [24] and

[25] Laurin. Zaky, and Balmain studied the mechanism of EMI-induced delay in digital systems. Wallace introduced the concept of a susceptibility window - a region in time near a digital signal transition during which the system has increased susceptibility. He also explored the characteristics of static and dynamic susceptibilities of a D-type flipflop as functions of the logic implementation (LS, F, AC, etc.), the timing of the applied inter- fering signal. and other parameters 1261. The effects of low-level interference on digital circuits were also explored by Chappel [27]. Low-level EMI was found to cause failures

due to the violation of timing consaaints. The second group actively studying EMI effects on digital circuits in the 1990's is

based at the Radiopropagation and Electronics Lab in Lille, France. Baudet et aL injected

current and voltage pulses onto a track linking two NAND gates and observed the result-

ing upsets 1281. In [29] Klinger et al. concluded from their experiments on a simple digital circuit exposed to the fields of a TEM cell that coupling of EMI to circuit tracks is the pri- mary cause of failure. They also studied the frequency dependence of the upsets. Hedde-

baut et al. in [30] determined experimentally the EMI-induced delay in a CMOS logic circuit They state that the main factor influencing the device susceptibility is its dynamic output resistance. Scuka and Demoulin review the effects of transients on both digital and analog equipment in terms of interference sources and failure mechanisms 1311. Marechal et al. investigated susceptibility as a function of digital logic family in 1321. Baudet et aL proposed a general method to locate a malfunction within a large electronic system, con- sisting of fmt identifying the susceptibility of each component in the system and then con-

sidering the impact of a component malfunction on the operation of the system [33]. In [34] Coudoro. Baudef and Demoulin form a theoretical prediction of EMI-induced delay similar to that of Laurin [24]. Rifi et al. extend the Lille group's work on EM1 effects to

include track effects, such as resonances. This work does not, however, include digital (non-linear) sources and loads [35].

In addition to the work at Toronto and at Lille, several studies warrant mention. The extensive experimental results in Test Diagnostics of RFEfects in Integrated Circuits I361 imply that applied EM1 can cause timing problems in digital logic, although this con- clusion was not explicitly stated in the report. In [37] and [38], Yamanaka. Nishita , et al. studied the induced voltage due to EMI, assuming fmt linear loads and then non-linear loads. The authors observed EMI-induced delay in LS-Tl'L gates. Konefal and Marvin used numerical analysis to study the formation of intermodulation products in an EM^-exposed digital system 1391. In [401 Liu and Ho employed both simulation and mea- surement to characterize the frequency-dependence of EM1 susceptibility of TI'L gates.

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neglecting transmission line effects.

While the aforementioned references consider the effects of EM1 on digital com- ponents, they do not address the difference in the susceptibility of a marginal component and a robust one. Also, the transmission line effects associated with the coupling path from the interference source to the digital component are not covered. These effects are both important in EM1 stress testing.

1.1.3 Stress testing and reliability

Printed circuit boards are often s-d to evaluate their response to possible oper- ating conditions. There are two approaches: environmental stress testing, done during the

design phase, and environmental stress screening, performed on each manufactured board, as discussed in a tutorial paper by Chan et aL [41]. Environmental stress testing can help improve product quality by removing design flaws and marginal products before they result in field returns and loss of customer satisfaction [42]. The statistical methods asso- ciated with this type of testing have been explored in monographs such as Burn-in by Jensen and Petersen [43], but the choice of stresses is not clearly defmed. An elevated

ambient temperature is the traditional stress, and is refemd to as burn-in. The extension of bum-in to other stresses (thermal, vibration, voltage) and the importance of analyzing causes of failure are discussed by Parker and Harrison [44] and by Parker and Webb [45].

In [46] Rao distinguishes between environmental stresses (mnperature, humidity, vibration, etc.) and electrical stresses (voltage, current). These, together with time, make up the stress space; a product should be exercised over an adequate range of the stress space in order to assess its reliability and understand its failure mechanisms. The use of

environmental stress testing to turn latent failures - those failures caused by hidden defects or weaknesses - into observable failures is highlighted in [41] and [47]. The

stresses mentioned in [41] are shown in Table 1. The types of failures are also discussed in [411. Electromagnetic stress testing is mentioned but is not discussed in any detail. It is doubtful whether such a stress test has actually been evaluated by the authors.

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Table 1-1 Environmental S t r e s s (from [41])

I Stress I Notes I 1 Elevated temoerature 1 most common stress test (bum-in) I

I ~emperature cycling I d e n t temperahue conditions may reveal design problems I

I

I Voltage variations I often combined with tests at temperature limits I

Power cycling

I Clock variations I dimcult test to achieve I

repeatedly turning product odoff

I

Vibration &shock I used to reveal structural and solder ioint problems

I

Elevated humidity

ESD & power surge

1.1.4 Electromagnetic stress testing

- - done in conjunction with high temperature testing

not performed on products to be shipped to customers

EM1 susceptibility

In addition to the mention in [41] of EM1 susceptibility as a potential stress, the following references include the notion of electromagnetic stress testing. In the discussion

of susceptibility mapping in [4] and [5], it is noted that defective chips and bad contacts reduce the operational margins of the board and thus cause failures during susceptibility mapping. The authors mention the possibility of using such a stress test to reveal manu-

facturing problems, while pointing out the need for further work to characterize the phe- nomena by which these failures occur. The apparatus described in [4] and [S] serves as the starting point for the research presented in this thesis.

In a patent by Goulette et al. [48], a method and appmtus for measuring electro-

magnetic susceptibility is described. This consists of a modification of the EMSCAN

electromagnetic emissions scanner described in [3] and [49] to allow for susceptibility measurements. Another mode of susceptibility testing is described in which an interfering

signal is injected onto the EUT via a cable, and then the electromagnetic emissions are scanned and compared with a baseline (no interfering signal) emissions scan. Mention is also made of the use of the EMSCAN apparatus in the fault diagnosis of printed circuit boards, but it is not clear if this is referring to the emissions mode or the susceptibility mode of operation. While this patent describes an apparatus and method for electromag- netic stress testing, there are no published results of its being put into practice.

. A patent by Hankui and Harada [50] describes an apparatus similar to that used in this work, although the EM1 applicators are generally distributed on both sides of the EUT

rather than on one side as used here. The authors of this patent have not published, other

may be done in conjunction with temperature cycling

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than in the patent itself, a description of their susceptibility measurement technique. nor have they published results of susceptibility tests.

1.1.5 University of Toronto susceptibility scanner

Work on a susceptibility scanner at the University of Toronto began in 1984 under the direction of Prof. K. G. Balmain. The goal of this research project was an increase in the understanding of EM1 in digital systems: "... a way had to be found, not just to mea- sure the overall emission or susceptibity states of the board, but to identify the most sig- nificant contributory regions of the board, those conducting traces and semiconductor devices primarily responsible for the interference. Therefore it was decided to concentrate on emission and susceptibility mapping of a microcomputer board ..." [511.

The original susceptibility scanner was constructed by P. C. Kremer and

W. G. Langdon. It used a coaxial loop antenna as the EM1 applicator; the plane of the loop was oriented parallel to the printed circuit board and 10 mm above it. The scanner

apparatus moved the applicator in 10 mm steps. The board under test was a Motorola 6809 microprocessor-based single board computer, which had two signal layers and no

ground or power planes. Susceptibility scans using the original scanner had repeatability problems, which

were investigated by Godse in his undergraduate thesis 1521. He found that neither appli-

cator positioning errors nor fluctuations in the interference power were responsible for the large variation in susceptibility, and deduced that 1000 tests were required at each applica- tor position and interference frequency to achieve repeatable results. Dubois and Wallace

reduced this requirement to 50 tests by replacing a faulty Dynamic RAM Controller @RC) chip on the 6809 board and modifying the susceptibility scanner software to alert

the operator to board upsets 1533. In subsequent work by the same authors, variability was attributed to faulty components and bad connections between integrated circuits and their

sockets on the printed circuit board. Substitution of a new. presumably more robust, board resulted in a reduction of the required number of tests at a single applicator position and interference frequency to five.

Next the effect of frequency instability in the EM1 source was investigated, by

Dubois [54]. Susceptibility tests prior to this investigation had been performed using the output of a network analyzer as the EM1 source. Dubois determined that the frequency dependence of the 6809 board susceptibility is such that a small change in the interference frequency (e.g. from 66 MHz to 66.3 MHz) can cause a large variation in susceptibility.

~ e ~ i a c i n g the network analyzer with a programmable frequency synthesizer produced a decrease in the variability of the susceptibility scan results. such that a variation of only

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1 dB in the susceptibility was observed for a given applicator position and interference fre-

quency. The susceptibility scanner described in [54] was used in the experimental investi-

gations by Laurin [6] and Wallace [7]. Its characteristics were fust reported in the widely-available literature (as opposed to the internal reports previously cited) in 1992 [4]. Modifications to the susceptibiity scanner made during the course of the research repotted

in this thesis are described in Ch. 2.

13 Research Objectives

The literature review rev& that electromagnetic interference may be a viable stress test As previously stated, the goal of this research is to develop and study a tool for analyzing (i) the susceptibility of a printed circuit board to localized electromagnetic inter-

ference, and (u) the dependence of the susceptibility map on board faults. In order to

achieve this goal. the following questions should be addressed. Questions related to the generation of the susceptibiliry map:

a) What is the effect of the EM1 frequency on the susceptibility mapg?

b) How does modulating the EM1 affect the susceptibility map?

c) How does synchronizing the EM1 to the board clock affect the susceptibility map8?

d) How does the software running on the EUT affect the susceptibility map8?

e) How fine should the scan resolution be?

f ) Is the EM1 applicator optimally designed for coupling the interference to the board?

g) How repeatable is the susceptibility map?

h) Can the EM1 be coupled to ttacks on each side (solder and component) of the EUT? Questions related lo the transfonnafion from suscepfibili@ map to fault map:

i) What types of failures occur during a susceptibility scan?

j) How can a board failure be traced to a particular component fault?

The main focus of this research has been on the effects of interference frequency (a), cou-

pling routes (h), and fault location (j); answers to these questions are developed through-

out the thesis. The questions relating to software (d), resolution (e), and applicator design (0 are covered in Chapter 2, while the observed faults (i) are explained in Chapters 4.5. and 6. Finally. questions relating to modulation (b), synchronization (c), and repeat-

ability (g) are not covered in depth. We will return to each of these questions in the con- clusions, where we present the answers discovered in this research.

*These questions have been addressed to some extent in [41, [61. and [7].

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1.3 Thesis Structure

The first part of this thesis, Chapters 1-3, covers general notions related to EM1 stress testing. The second part, Chapters 4-6, deals with specific failures found during stress testing. The conclusions of this work are presented in Ch. 7. with reference to the research objectives of Sec. 1.2.

The fust three chapters of this thesis present the concept of electromagnetic stress testing. This fust chapter includes the literature review and research direction. Chapter 2 describes the scanner apparatus used to obtain the experimental results described in the

second part of the thesis. The scanner apparatus consists of the EM1 excitation system and applicator, the applicator positioning hardware, and the controlling software. The printed circuit board used as the EUT for many of the experiments in this work is also described, as are susceptibility maps of this EUT. Chapter 3 explains the derivation of expressions

used to predict the effects of the interference frequency and applicator position on the voltages at various points on the EUT. This theoretical work is used in subsequent chap- ters to predict experimental results.

The second part of this thesis gives experimental evidence and theoretical analysis of three failures that occur during stress testing. In Ch. 4 a signal handover failure is char- acterized. This failure is associated with the handover of a control line from one driver to

another. The signal handover failure, which is due to a design trade-off, was first identi- fied experimentally. Its characteristics were then predicted using the theory of Ch. 3. In Ch. 5 a weak memory chip failure is characterized. This failure occurs when interference on an address pin of a damaged, but functional. DRAM (dynamic random access memory)

chip causes errors at the DRAM data outputs. Again, the theory of Ch. 3 is validated by comparison with experimental results. In Ch. 6 a failure mode associated with induced delay is explained, and its predicted characteristics compared with measurement.

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Chapter 2

SCANNER APPARATUS

The chain of events culmimting in a failure of the EUT due to EM1 is:

a) The EM couples to an EUT track at the point of entry.

b) The track connects drivers (outputs) and receivers (inputs) on integrated circuits, forming the coupling mute.

c) The interference causes a driver or receiver to malfunction with a certain failure type.

d) The malfunctioning driver or receiver is exercised by a diagnostic mutine.

e) The diagnostic fails. The parameters that affect each of these events are shown in Fig. 2-1. The subject of this chapter is the susceptibility scanner apparatus, which includes elements related to the

point of entry, coupling mute, and diagnostic routine.

Point of Entry interference power interference frequency location of applicator (over which track, where along that track)

Coupling Route track layout impedance and propagation velocity locations and impedances of drivers locations and impedances of receivers

Diagnostic Routine * board coverage

failure classification effect on driver impedances (driving or high-impedance)

Failure Qpe direct at driver (e.g. signal handover failure, Ch. 4) feedthrough (e.g. weak memory chip failure. Ch. 5) direct at receiver (e.g. induced delay failure. Ch. 6)

Figure 2-1. Parameters affecting susceptibility scan.

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This chapter gives details of the susceptibility scanner apparatus. The hardware

required to perform a susceptibility scan is described in Sec. 2.1. In Sec. 2.2 the suscepti- bility scanner control software is described. Note the distinction between the control soft- ware, which runs on a PC and coordinates the scan, and the diagnostic software (Sec. 2.4.2). which runs on the EUT and detects failures. The PC communicates with the EUT over a serial link. In Sec. 2.3 the EM1 applicator, a key component of the scanner hard- ware, is described in detail. The EUT used in most of this thesis is shown in Sec. 2.4, fol- lowed in Sec. 2.5 by some susceptibility maps for this EUT. Finally, the main fmdings of

this chapter are summarized in the conclusions.

2.1 Susceptibility Scanner Hardware

The main components of the susceptibility scanner apparatus are an X-Y posi-

tioner driven by stepper motors, an EM1 applicator and the equipment to excite if and a host computer (PC), as shown in Fig. 2-2. The EUT is positioned on the plexiglass s u p port table, as shown in Fig. 2-3. The applicator is excited at a power level and frequency

specified by the PC, then the EUT diagnostic is run. If the diagnostic fails, the power is reduced and the diagnostic is re-run. If the diagnostic passes. the applicator is moved to the next test position, the power is reset, and the test continues. In this manner a map of the EUT susceptibility is obtained. The susceptibility is m e a s ~ e d in terms of the mini-

mum interfering signal that causes a failure; this is the failure threshold. Failure is detected by having the EUT report the result of the diagnostic to the PC.

The stepper motors and associated control card (mounted in the PC) were designed

at the University of Toronto Electromagnetics Group by P. Kremer. The motors have a minimum step size of 0.2 mm. The motors accurately position the applicator with respect

to a known reference (the comer of the scanner apparatus). The EN1 525LA power ampli-

fier has 50 dB gain (maximum available power 25 W) and operates in the frequency range from 1 to 500 MHz The signal generator, the HP8642B. is capable of producing sin- gle-frequency or modulated signals. in all the measurements considered here, single fre-

quency (unmodulated) interference is used.'

*~ri;f lesu with 100 kHz amplihlde moduhled interference indicated Lbat failure thresholds denend on ueak induced voltage; the moddaion does not affea susceptibility except in that it increases tbe pcak induced voltage (for example. a 100% modulated signal has twice tbe peak voltage as an unmodulaIPd signal).

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- GPlB cable

host computer (PC)

variable auenualor

Figure 2-2. Susceptibility scanner. f h

Printed circuit board Plexiglm suDpn rabl

J Figure 2-3. EUT positioned in susceptibility scanner.

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2.2 Susceptibility Scanner Control Software

The PC controls the susceptibility scan by higgerhg the actions described in Fig. 2-4. The control software d i i t s the diagnostic mutine (downloading it to the EUT. signalling the EUT to run it, and recording its result), the interference (turning it on and

Set up test parameters (frequency range, power range, diagnostic test) Initialize communications links Run diagnostic test (abort if failure) Move applicator to fust test position DO (loop through applicator positions)

DO (loop through frequencies) DO (loop through power levels, starting at maximum power)

DO (loop through tests at a single power level) Turn EM1 on IF there are no communications errors THEN

Run diagnostic test; record result ELSE

Reset E m , record communications error END IF If an error occcured, run diagnostic with EM1 off (reset if failure)

LOOP (until finished all required tests at this power level) Decrease power level

LOOP (until no failures are recorded at this power level) Increment frequency

LOOP (until finished all required frequencies) Move applicator to next position

LOOP (until finished all required applicator positions) . .

End

Figure 2-4. Susceptibility scanner control software pseudocode.

Several problems were encountered during the development of the susceptibility

scanner control software. Although these problems occurred with a particular EUT, they point to software and hardware changes that lead to a more robust test environment The

pseudocode of Fig. 2-4 includes these changes, except where otherwise noted below. Problem 1. The applied interference may upset the EUT sufficiently that when

the interference is turned off the EUT will not respond to commands from the PC. If this occurs, the PC regains control by sending a reset signal (over a separate cable not associ-

ated.with the serial link) to the EUT. Problem 2. The PC communicates with the EUT over a serial link. A problem

occurred when the interference caused the serial communications chip (UART) to trans-

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mit a square wave on the serial link. Since this square waved si@ed continual inter- rupts to the PC, the PC would crash when the serial port was opened This pmblem was solved by having the PC monitor the communications port on a polled, nther than inter- rupt, basis. In order to detect the abnormal presence of the square wave on the serial link, the PC inspects its modem status register before opening the communications port If the modem status register shows an error, the interference is hmed off, a reset signal is sent to the EUT, and the diagnostic result is recorded as a 'bad communications' failure.

Problem 3. When the applicator was positioned over a memory chip, occasionally

the interference corrupted the diagnostic program stored in the memory. Subsequent diag- nostic tests failed even without interference, since the corrupted diagnostic was no longer

able to tun. This problem was fixed by checking whether the diagnostic failed with no interference. and, if so, having the PC retransmit the diagnostic program to the EUT.

Problem 4. If the failure threshold is much lower than the maximum applied power, the "DO" loop through power levels (see Fig. 2-4) is repeated many times as the power is decremented to the failure threshold. Thus a long time is required to complete a test at a single frequency and applicator position. To increase the scan speed, the notion that similar frequencies will have similar failure thresholds was incorporated into the scan

procedure. Tests at successive frequencies s m at the lesser of the maximum power and 6 dB above the failure threshold at the previous frequency. If no failure occurs at this power level, the power loop is restarted at maximum power so that the true failure thresh-

old can be identified. For large frequency steps, this procedure may cause longer nther

than shorter scan times. A sample run at a single applicator position is shown in Fig. 2-5. Note that the algorithm associated with Problem 4 is not included in the pseudocode of Fig. 2-4.

' 100 MHz 110 MHz 120 MHz

Power Fails? m Power Fails? kl Figure 2-5. Example of method to increase scan speed. At 120 MHz and 130 MHz the scan stam at 6 dB higher than the previous failure threshold, rather than at the maximum power of 30 dBm.

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2.3 Applicator

A key component of an EMI streSC testing apparatus is the applicator. The appli- cator couples the EMI signal, produced by a signal generator and power amplifier. into the target track on the EUT. Methods for quantifying applicator performance are described below. Following that, three applicators that were used in this work are described; only the final applicator described here (the planar inductive applicator) was used extensively. Predictions and measurements of the chvacteristics of the planar inductive applicator are presented at the end of this section.

2.3.1 Applicator figures of merit

The applicators are characterized by evaluating their performance in coupling to a

calibration track This calibration track, shown in Fig. 2-6, was designed to be s i m i i to a typical EUT track in terms of dielectric material and thickness and metallization width and thickness. Unlike a typical track, the calibration track is saaight, isolated from other

tracks, and terminated in matched loads. The characteristic impedance of the calibration track is approximately 100 Q and h e propagation velocity v, = 1.7 x lo8 mls, corre- sponding to inductance and capacitance per unit length of b = 600 nWm and

Co = 57 pF/m. The calibration track is modeled as a :~!ped equivalent circuit in the

region where the applicator couples to i t The portions of the calibration tnck outside of the coupling region are replaced with resistors equal to the track chatacteristic impedance Z, The length of the coupling region, a, is assumed to be short with respect to the wave-

length so that the lumped equivalent circuit is valid. The lumped tee and pi equivalent cir- cuits of the calibration tnck are shown in Fig. 2-7, where L, = aLo and C, = aCo

An effective applicator has large coupling coefficient, high resolution, and wide bandwidth. The coupling coefficient CC is the ratio of the available power from the power

amplifier (i.e. the power delivered to a matched load for a given power input to the ampli- fier) to the power dissipated in the terminating resistors of the calibration track. A large coupling coefficient requires large a, but a should be kept reasonably small for adequate x-resolution. As the applicator is moved laterally (in they direction) away from the cali- bration track, the coupling coeff~ient decreases. The resolution R of the applicator, for a

given applicator height above the calibration track. is the reciprocal of the distance at which the coupling coefficient falls to 6 dB below its maximum value. High resolution is obtained by minimizing the applicator y-dimension.

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Figure 2-6. Calibration track

Figure 2-7. Equivalent circuits of calibration track: (a) tee equivalent, (b) pi equivalent

2.3.2 Capacitive applicator

A non-contacting capacitive applicator is shown in Fig. 2-8. This applicator is intended to have strong coupling between one plate of the applicator and the target aack,

and also strong coupling between the second plate of the applicator and the target ground plane. The desired equivalent circuit, using the tee equivalent circuit of the calibration track, is shown in Fig. 2-9a. Figure 2-9b shows the actual equivalent circuit complete with parasitic elements.

A capacitive applicator was studied to determine whether, for realistic dimensions. adequate coupling can be achieved. The applicator considered here is 3 cm long, with the metal plates 0.2 mm wide and separated by 0.1 mm; the applicator is located 1 mm above the calibration track. A commercial 3-D planar electromagnetic solver. Sonnet, was used

to fmd the equivalent circuit capacitances. For maximum coupling, C2, and Cjg should be large and al l other capacitances should be negligible. However, this is not the case here

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due to the relatively large clearance required between the applicator and the calibration

track (-1 mm minimum) and the small target track width. Also, the applicator plates are close together to maximize resolution, but this increases Cu so that most of the interfer- ence current flows through Cu rather than Czl and C3g as desired. The shunt capacitance Czt can be reduced by extending plates 2 and 3 in oppositex-directions, rather than paral- lel to each other; however, for a fixed applicator length (and hencex-resolution) each plate must be half as long as in the parallel case, thus reducing Cz,. For realistic dimensions the coupling coefficient is less than -50 dB, so this applicator was abandoned in favor of inductive couplers.

Figure 2-8. Planar capacitive applicator.

Figure 2-9. Equivalent circuit of planar capacitive applicator: (a) ideal; (b) with pamitics (capacitor values in fF are in parenthesis).

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23.3 Coevial inductive applicator

A simple inductive applicator is made by forming a semi-rigid coaxial cable into a square loop, as shown in Fig. 2-10. The y-dimension of this applicator is comparable to the cable diameter, and thus this applicator has relatively low resolution. Also, the coaxial

construction limits the bend radius and thus sets a lower limit on the loop dimensions. Finally, the effective feedpoint, with associated high electric fields, is adjacent to the tar- get track Thus the applicator may cause capacitive (electric field) coupling in addition to the desired inductive (magnetic field) coupling. This mixed coupling complicates the

analysis of the induced voltages and currents on the target track, and thus is undesirable. The coaxial inductive applicator has the advantage of inherent balance due to its symme- try; however, as explained in the next section, balance is not a key requirement here. The coaxial construction of the inductive applicator is ruled out in favor of planar printed cir-

cuit construction, as described in the next section.

C

Figure 2-10. Coaxial inductive applicator.

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23.4 Planar inductive applicator

A planar inductive applicator consisting of a small planar loop printed on a dielec- tric substrate is shown in Fig. 2-11. The equivalent circuit is also shown, with the pi equivalent circuit of the calibration track (parasitic capacitances are not shown here but are considered in Sec. 2.3.5). This applicator is very mall in the y-direction, and thus has high resolution. The printed design is more flexible than the coaxial design, in that con- ductor widths and bend radii can be chosen as desired. Fimally, the effective feedpoint is on the side of the applicator away from the calibration track, so that the field near the cali- bration tmck is predominately magnetic field rather than the relatively high electric field associated with the feedpoint Unlike the coaxial applicator, the planar design is unbal-

anced. However, the fields at the mget track due to the current flowing on the feed cable because of this imbalance will be small compared with the fields due to the applicator itself. Thus the planar inductive applicator is used in the rest of this thesis.

-

Figure 2-11. Planar inductive applicator and equivalent circuit

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23.5 Planar inductive applicator characteristics

The key characteristics of the applicator are the coupling coefficient, the resolu- tion, and the bandwidth. Each of these is discussed in this section, along with an explana- tion of how the failure threshold depends on the applicator characteristics.

The coupling coefficient depends suongly on the mutual inductive coupling between the applicator and the target track The mutual coupling per unit length can be

approximated by modeling the applicator as an infiitely long x-directed filament located at the bottom of the applicator metallization, and the calibmtion track as an infinitely long

x-directed filament located at the centre of the calibration track and over an infinite ground plane. The effect of the dielectric is neglected in this simplification, since exclusively magnetic field coupling is assumed. The per unit length coupling of this idealized geome-

try, derived in Appendix A, is then used to calculate M. The resulting mutual inductance, for a coupling length of a, is

where, with reference to Fig. 2-1 1, d is the lateral distance from the plane of the applicator to the target track, h is the height of the applicator over the target track, t is the dielectric thickness, and po = 4x x lo-' H/m is the permeability of free space. Note that this for- mulation neglects the effects of the conductor width w and the loop height b.

(VSlZ The coupling coefficient CC is the ratio of the available power Pa = to the 4 power dissipated in the terminating resistors of the calibration track, Pdk All voltages

are peak quantities, and sinusoidal time variation is assumed. We assume (and will later

prove) that the equivalent circuit of Fig. 2-11 can be reduced to that of Fig. 2-12, where

Vhd is the voltage induced in the target track and is given by (2-2). The induced voltage does not depend on the position of the applicator along the target track.

+ vid (B) Figure 212. Reduced equivalent circuit of planar induc- tive applicator over test target

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The coupling coefficient CC is then calculated from

where M is a function of a, d, h, and t. The maximum coupling occurs when the applicator is aligned with the target track (d = 0); we call this the aligned coupling coefficient,

CCId = 0.

As defined in Sec. 2.3.1, the resolution R of the applicator, for a given applicator height h, is the reciprocal of the distance d = dR at which the coupling coefficient falls to

one quarter (i.e. 6 dB below) the aligned coupling coefficient Since d affects the coupling

coefficient only through its effect on M, the reso!ution can be found by solving the follow- ing equation for dR in terms of h and c

and then calculating

1 1 R = - = - dR J- (2-4

The dependence of the resolution on the applicator height for several values of dielectric thickness is shown in Fig. 2-13.

3.5 1 1.5 2 2.5 Applicator height (mm)

Fiyre 2-13. Resolution as a function of applicator height and dielectric thickness, from eqn. (2-4).

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The coupling coefficient of the planar loop applicator falls off at low frequencies. By inspection of (2-2). the lower 3-dB limit on the bandwidth is

The high frequency limit of this applicator is not predicted by (2-2). We expect that two factors will inhence the operation of the applicator at high frequencies. The electric-field coupling between the applicator and the target track can be represented by parasitic capac- itances. The frequency oul at which these parasitic capacitances begin to affect VM can be found using circuit simulation on the equivalent circuit of Fig. 2-11. Also, the input

impedance of the applicator is inductive at low frequencies but acquires a large resistive component (the radiation resistance) as the perimeter of the loop exceeds approximately

0.4 wavelengths [55]. For satisfactory applicator operation 2a + 26 c 0.47L. and the corre- spondiig upper 3 dB frequency (where c i s the speed of light in vacuum) is given by

There are several trade-offs in designing the applicator. As the applicator length a increases. Vhd increases but the resolution in thex-dimension decreases. As the applicator height b decreases, the applicator self-inductance La decreases and thus VM increases, but

if b is too small then M, and thus Vhd, will decrease. This occurs when the field due to the current flowing in the upper conductor of the applicator begins to offset the desired field,

that due to the current flowing in the lower conductor (i.e. adjacent to the target tnck). Fially, as the width w of the applicator conductor is decreased, the current in the lower

conductor of the applicator is confmed to a region closer to the target track, so Va increases. However, small w implies increased series resistance in the applicator. and thus increased power loss and the potential for applicator heating. For the applicator used in thii work, we choose a = 3 cm, b = 1 cm, and w = 1 mm. This results in an applicator self-inductance La, calculated using Sonnet, of 64 nH.

The predicted aligned coupling coefficient CCld = from (2-3) and the predicted resolution from (2-4) for the planar loop applicator discussed above are compared with measurements in Fig. 2-14. The measurements were made using a calibrated network ana-

lyzer. and thus any imperfections in the source and detector are suppressed. The lower 3 dB ftequency for thii applicator is found from (2-5) to befi = 125 MHz For the upper frequency limits, using (2-6) we have fu = 1.5 GHz In order to f i d ful, we estimate the

parasitic capacibnces by using Sonnet to analyze the structure shown in Fig. 2-15a. The

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vertical strip represents the lower conductor of the applicator. In Sonnet, this vertical srrip is modeled as two 0.1 mm wide horizontal conductors, located at heights h and (h + W) above the target track These two conductors are connected along their lengths by vertical via. The resulting equivalent circuit is shown in Fig. 2-15b. Libra simulations of this cir- cuit indicate that the parasitic capacitances begin to effect Va above fuI = 1.5 GHz. Fig- ure 2-14 confirms that the planar inductive applicator is effective in the band studied here. i.e. 100 MHz to 500 MHz The dip in measured coupling coefficient above 450 MHz is not predicted here, but should not greatly affect our results.

Figure 214. Measured and predicted coupling coefficient and resolution for h = 1 mm, t = 0.5 mm.

Figure 2-15. Capacitance between planar loop applicator and target track: (a) physical structure, and (b) corresponding equivalent circuit

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We next justify eq. (2-2) by deriving the circumstances under which the induced

voltage does not depend on the target track load impedances, and thus can be represented as an independent voltage source Vind, as in Fig. 2-12. Figure 2-16 shows the equivalent circuit of the applicator over a target track terminated in arbitrary impedances Z1 and Z2 (with the C,$ elements of the target track equivalent circuit a b s o h d into ZI and &). Note that we have neglected the parasitic capacitances; we assume that we are operating in

the frequency band where the effects of these capacitances are negligible.

Wgure 2-16. Equivalent circuit of planar loop applicator over target track

The voltage across the termination loads, Vinb is

We now consider the cases for which this equation can be reduced to

Fit, we substitute Z, + Z2 = Z, = R, + jX,. Then, when the following two conditions are w e , (2-7) reduces to (2-2):

and

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In the extreme case of a target with purely reactive loads, i.e. R, = 0, the above requirements may not be met In this work we assume that sufficient loss exists in the target track so that (2-2) is valid. For example. resistance of R, = 3 R is s f l~c ien t to meet this condition at 200 MHz for typical applicator and target track characteristics.

The coupling coefficient shown in Fig. 2-14 was measured using a network ana- lyzer, so any imperfections in the source impedanceR, were suppressed by the calibration procedure. In susceptibiity scans, which use the apparatus shown in Fig. 2-2. the cou- pling coefficient is affected by mismatches at the power amplifier output The power amplifier output is fed to the applicator input through a 50 R feed cable. If the power amplifir output impedance R, is not matched to the feed cable, the coupling coefficient will be altered from the expected value. Figure 2-17 shows the measured and predicted coupling coefficients. The periodic variation in coupling coefficient is caused by the mis- match at the power amplifier output The decrease in average measured coupling coeffi- cient compared with theory is due to the attenuation through the variable attenuator shown

in Fig. 2-2 (which has loss even whai: set to 0 dB attenuation), cable loss, and variation in the signal generator output (specified to f 1 dB) and power amplifier gain (specified to 11.5 dB).

Freauencv (MHz)

Figure 2-17. Coupling coefficient with source mismatch.

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Failure fhreshold. During susceptibility scans, the minimum available power at

which failure fmt occurs is recorded. The failure threshold can be expressed as this avail- able power Pa, in dBm, or the corresponding induced voltage. Vim,+ in dBV. The former is directly recorded by the scanner software, and is referred to here as the power at failure. The latter is the result of calibration of the recorded data, and is referred to here as the fail- ure rhreshold. The calibration sequence consists of recording the induced voltage Vtrd for a given power setting Pa, and then calculating

where all quantities are expressed in dB. Note that the relation between Vind and Pa can be measured d i t l y by monitoring the voltage across one of the termination resistors of the

calibration track while exciting the applicator with available power Po, or deduced from the coupling coefficient measurement of Fig. 2-17.

Additional adjustment of (2-8) is required if the height of the probe during calibra- tion, ha,. is different from that during measurement h,, (where we assume that q u a - tion (2-2) holds and that d < h + 2t). The adjustment factor 201og(H), where H is given by (2-9). should be added to the right side of (2-8).

Failures observed in this wo d for available powers above approx. 20 dBm (100 mW). The maximum available power tested was 44 dBm, corresponding to the power amplifier maximum output of 25 W. Tc Aate these values to the equivalent field strengths, consider a failure at an available power of 30 dBm = 1 W. With negligible mismatch on the feed transmission line, this available power would correspond to a peak source voltage of 20 V. At 300 MHz this excites a peak current of 153 mA through the series load of 50 R source impedance and 64 nH applicator inductance. This current flows at a ditance (h + t) = (1 mm + 0.5 mm) above the ground plane. The H-field at a distance r = 1 mm from the applicator current, in the direction of the ground plane, is

1 0 153 1 + -- 1 = in (0.001 (2(0.0015)-0.W1))) = 37 Nm

If *is H-field were produced by a uniform plane wave, the corresponding E-field would

be 14 kV1m and the power density 259 kw/m2. This plane wave would. however, couple to the EUT in a different manner than the inductive coupling of the applicator.

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2.4 Typical EUT

24.1 Hardware

The EUT used in this work is the University of Toronto teaching board based on a Motorola 68000 central processing unit (CPU) and 2 MBytes of memory [56]. The board is 32 cm by 18 cm, and consists of 2 outer signal layers, a buried ground layer, and a bur- ied power (+5 V) layer. The two sides of the EUT are referred to as the component side, which has the chip packages, and the solder side, from which only the package pins can be

seen. The component placement is shown in Fig. 2-18 and the tracks as seen from the sol- der side are shown in Fig. 2-19. The EUT read-only memory chips (EPROMs) are loaded with a terminal program which allows the user to communicate with the EUT via a serial link to a terminal or a host PC. In this work the EUT was interfaced to a PC through this terminal program. In this way a diagnostic program could be downloaded from the PC to the EUT and then executed, and the results reported back to the PC.

I

I

0 PAL (programmable logic) Q Crys(al Corneaor

Cj Other chip Passive components pd GndfPwr planes ahrent

Figure 2-18. EUT layout (as seen from solder side).

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Figure 2-19. Scanned image of solder side of EUT.

Formulas for the characteristic impedance lo, propagation velocity v,,, and attenua- tion coefficient a for microstrip [57] are given in Appendix B. The tracks on the EUT are approximately 0.2 mm wide and 0.5 mm above the ground plane, and the relative permit-

tivity of the FR-4 substrate is 4.5. These dimensions give Zo= 100 R and

vp = 1.7 x lo8 mls. The attenuation coefficient a is found assuming 1 oz. copper mcks (corresponding to a conductor thickness of 36 prn and conducti-(ity of a = 5.8 x lo7 Slm) and a dielectric loss tangent of 0.024, and is shown in Fig. 2-20.

Measurements on the EUT indicate that the actual loss is greater than that predicted here; a

loss tangent of 0.25 is used when calculating the EUT attenuation coefficient The attenu- ation coefficient of Fig. 2-20 is used in the study of the test board described in Ch. 4.

Figure 2-20. Attenuation coefficient and its constituent parts (conductor and dielectric losses).

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2.4.2 Diagnostic routines

The diagnostic routine is an integral part of a susceptibiity s t x s test, as shown in Fig. 2-1. It controls the operation of the EUT and may affect the coupling route by turning a driver on and off, thus changing its impedance. In developing a diagnostic routine, the

key trade off is between functional coverage and test time. For a complex EUT, excessive test time would be required to test every possible EUT function.

As mentioned previously, the EUT contains a monitor program which is stored in the EPROMs and is running when the board is powered up. The monitor program sets various EUT defaults. It also allows communications with the PC via a serial link. All diagnostic tests used here are nm through the monitor program.

The diagnostic programs were written in assembly language on a Sun workstation and prepared for the 68000 microprocessor using the a68 cross-assembler. The diagnostic

routine is downloaded from the PC to the EUT memory in machine code (hexadecimal) form. If the diagnostic fails with applied interference. the interference is turned off and the diagnostic is re-run. If this fails, the diagnostic program is re-transmitted from the PC to the EUT memory since it may have been compted by the interference (see Sec. 2.2).

The standard diagnostic used in this work is called ParhialFill. The assembled code is shown in Fig. 2-21. This diagnostic tests three memory locations, comspondig

to four DRAM chips each. Zeros are written to each location, then read back to registers dl, d2, and d3. Next, ones are written to each location, then read back to registers d4, d5. and d6. After the test, if registers dl, d2, and d3 contain all zeros and d4, d5, and d6 con-

tain all ones then the EUT passes the diagnostic test; if not, it fails. The failure location

can be narrowed down by determining which register contains an incorrect value. The second diagnostic routine used here is called CompleteFill. This program f&

memory banks 1.2, and 3 with zeros. reads them back, and then fills these banks with ones and reads them back. CompleteFill takes considerably longer than ParrialFill to exe- cute (approximately 6 s compared with less than 1 s). Both CompleteFill and PartialFill are used to diagnose the weak chip failure described in Ch. 5.

The third diagnostic routine, Ethernetoff, modifies the default EUT set-up by di- abling the Ethernet controller. It is used in diagnosing the /AS handover failure of Ch. 4.

In each of these diagnostic routines, the result is communicated to the PC via the EUT registers. If the EUT fails to transfer correctly the register contents to the PC, the diagnostic is said to fail with a 'no response' result. This may indicate, for example, that the EUT has hung and needs to be reset. Also, if the PC detects invalid data on the com- munications link, the diagnostic is said to fail with a "bad communications" result. This may indicate a failure of the EUT serial communications chips.

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specify 3 addresses of interest

move all 0's to the 3 addresses

copy the contents of the 3 addresses to registers dl.d2, & d3

move all 1's to the 3 addresses

copy the contents of the 3 addresses to registers d4,d5, & d6

020036: 4e4f trap #I5 return to monitor prognm,

Figure 2-21. PartialFill diagnostic code.

2.5 Susceptibility Maps of the EUT

The scanner apparatus described in this chapter is used to generate susceptibility maps of the EUT described in Sec. 2.4. The results of a scan include the failure threshold

and diagnostic result for each applicator position and interference frequency. Here we try to pinpoint the tracks that are failing by showing only the presence of a failure as a func-

tion of position. We suppress the failure threshold and diagnostic results (the PartialFill diagnostic was used), and use a single interference frequency (200 MHz). The susceptibil- ity map shown in Fig. 2-22 consists of the track position information (Fig. 2-19) overlaid with the failure information (in red). This system has the advantage of quickly and clearly

showing failure regions, but loses much of the information gathered during the susceptibil- ity scan.

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Figure 2-22 indicate< threc Cailure regions. The top two are both associated wic.

the weak chip failure. and will be examined in Ch. 5. The longer bottom one, in the vicin-

ity of the dynamic RAM controller (DRC), is shown in more detail in Fig. 2-23a. The /AS

track is highlighted in Fig. 2-23b. This failure is thus associated with the /AS track; it is

explored further in Ch. 4.

....-............ -. ........... - . . . . . ..... -, ,:. , . . . , . , . . . .

Figure 2-22. Susceptibility map at 200 MHz over the cen- tral portion of the EUT; failures in red.

Figure 2-23. DRC vicinity of Fig. 2-22: (a) with failures in red, (b) with /AS track in blue.

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2.6 Conclusions

In this chapter the hardware and software required to perform a susceptibility scan

were discussed. Some key points in performing a successful EM1 stress test follow.

a) EM1 coupling to a target track over a ground plane (microstrip configuration) is more effective with an inductive applicator than with a capacitive applicator. This is due to the current diversion through the parasitic capacitance in the capacitive coupler.

b) A test track terminated in matched loads is used to calibrate the applicator system to account for variations with frequency of the injected signal. Variations are primarily due to the mismatch between the power amplifier and the applicator.

C) The spatial resolution of the applicator should be s i m i i to the track separation to allow a single track to be targeted.

d) The diagnostic routine running on the EUT can help in classifying a failure by indicat- ing which EUT function is being exercised when the failure occurs.

e) Communication between the EUT and the PC should be polled rather than inter- rupt-driven so that abnormal communications signals from the EUT will not crash the PC.

f ) An external reset is required to return the EUT to a known state in the event that the EM1 causes it to go into an otherwise unrecoverable state.

Susceptibility maps of the interference power causing failure of the EUT as a func-

tion of applicator position were shown. The maps pinpoint the tracks which, together with

their anached digital devices, are most susceptible to EML The remainder of this thesis deals with interpreting the frequency and applicator position effects on susceptibility and with characterizing particular failures.

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Chapter 3

FREQUENCY AND COUPLING POSITION EFlFECTS

A sinusoidal hterfering signal, when coupled to a track of a digital circuit, may cause upsets. The voltages developed at the circuit nodes determine the extent of the

upset In this chapter, the effect of the interfering signal as a function of frequency and coupling position will be studied. This work extends previous studies by including both transmission line effects and high-frequency effects, where the interfering signal period is

comparable to the digital signal risetime. The system under consideration is shown in Fig. 3-1. It consists of 2 driver on one

integrated circuit which drives a printed circuit board track (transmission line) that con- nects to a receiver on a second integrated circuit More complicated systems may include additional drivers, receivers, andlor passive components, modeled as stubs off the main

transmission line. The EM1 source is modeled as an ideal voltage source Vind connected in series with the transmission line, representing inductive coupling to the transmission line, as described in Sec. 2.3.4. Capacitive coupling, characterized by a shunt current source rather than a series voltage source, will also be considered. /

- --

Figure 3-1. Digital circuit with EMI.

First the effect of the interfering signal is derived for the case where the driver

impedance does not change with time (i.e. the static case). Considered next is the dynamic case. where the driver impedance abruptly switches from one value to another. In these derivations the driver and receiver are assumed to behave linearly, except for the abrupt impedance switching in the dynamic case. The interference waveforms are deter- mined using steady-state sinusoidal analysis, and then superposed on the interference-free signals. The final section of this chapter deals with determining the driver and receiver

impedances. The theoretical results of hiis chapter will be compared with measurements in subsequent chapters.

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3.1 Static Analysis

3.1.1 Inductive coupling

In this section the voltages at the nodes of the circuit of Fig. 3-1 are derived for the case when the driver impedance is static (not changing). The circuit is redrawn in Fig. 3-2; the transmission line linking the drivers has length L, characteristic impedance .?v, and propagation constant y = a + j p . The induced voltage is Rnd = Re{Xnd ejur}, and & is the phasor EM1 voltage at node x (where the subscript 0 indicates the static case).

-) vm- +- v,-

\ d

Figure 3-2. Equivalent transmission line problem to deter- mine sctic node voltages.

The voltage wave incident on node 1 is Vlo+. The superscript denotes the direction

of wave travel: + for away from the EM1 source and - for toward the EM1 source. The dependence of the node voltages on the excitation voltage Vind, the complex reflection coefficients r, and rl (corresponding to 2, and 21). and the line lengths Ll, &, and L is

shown in Fig. 3-3.

Figure 3-3. Flowchart for determining node voltages.

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Thus the node voltages are

where 4, = T,T,e-yzL. Consider for example a lossless m m i s s i o n line with & = 100 Q,

vp = 2 x 108 mls, and L = 25 cm. The loads used here are those developed in Sec. 3.3 for

a representative CMOS system. Figure 3-4 shows the voltages at the driver (VIo) and receiver (V@) corresponding to Va = 0.1 V for three applicator positions (LI = 0 at the driver end, LI = U2 at the middle, and LI = L at the receiver end of the line). The peak in

the frequency response corresponds approximately to a quarter-wavelength resonance (f = 2 = 200 MHz). The frequency dependence is most pronounced when the inter- ference is near the driver (i.e. LI = 0) because the impedance looking toward the receiver varies greatly with frequency. The voltage at the receiver, Va is greater than the voltage at the driver, V1& because the driver has a low output impedance and the receiver has a high input impedance.

Figure 3-4. Static node voltages (inductive coupling).

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3.1.2 Distributed source (inductive coupling)

If the interference couples not at a point but rather is distributed over the length a of the applicator, the equivalent circuit shown in Fig. 3-5 results. The effect of a can be

taken into account by writing (3-2) in terms of L, and then integrating over

L1 = L1 + Ll + a . The resulting expression is

If ya * 1, i.e. the applicator is short with respect to the wavelength, then we can use eWa = I f ya + i(ya)2 so that

2

Similar expressions can be derived for the voltage at node 1.

Fi y r e 35. Equivalent transmission line problem to deter- mine static node voltages: distributed interference source.

Figure 3-6 shows the node 4 voltage with the 3 cm applicator at the driver end (Ll = 0) and the middle (LI = U2) of the transmission line, ignoring the applicator length,

assuming a short applicator, and accounting fully for the applicator length (i.e. using equa- tions (3-2). (3-4). and (3-3) respectively). This figure shows that the applicator length has a negligible effect with LI = 0 and a small effect with Ll = U2, notably the decrease in the

voltage at the 200 MHz resonance and a shift in the frequency of the 400 MHz anti-reso-

nank. In al l cases considered here the short applicator approximation of (3-4) is suffi- cient, and often the zero-length approximation of (3-2) is adequate.

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0 5 L ' I 0 50 100 150 2Nl 250 300 350 400 450 500

FImuewv

- m applicator effect sbaa spplicatmeflsst full applicaIo~ effect

1, B

Figure 3-6. Effect of including applicator length on Vm: (a) L, = 0; (b) L, = U2.

3.1.3 Thevenin equivalent approach (inductive coupling)

In the previous sections we considered a point-to-point transmission line, that is one having a single driver and a single receiver as shown in Fig. 3-5. Sometimes the transmission line of interest has additional loads (drivers, receivers andlor passive compo- nents, possibly at the ends of transmission line stubs) as shown in Fig. 3-7. In this case the Thevenin equivalent approach results in a simpler analysis than that previously presented (although it hides the physical meaning apparent in the formulas of the previous section).

The Thevenin equivalent method consists of deriving an equivalent circuit looking from the node of interest into the transmission line. This is done by starting at a point far away from the node JE interest and moving toward i l transfoming along transmission lines and absorbing parallel loads according to the two cases illustrated in Fig. 3-8. The equations governing these transformations are given in (3-5>(3-8).

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Figure 3-7. Example circuit use of Thevenin-equivalent approach to fmd V,

Figure 3-8. Transformations to Thevenin equivalents.

For example, consider the equivalent circuit of Fig. 3-7. which corresponds to a simplified version of the EUT A4 track to be studied in Ch. 5. We want to fmd the voltage V, at node X due to the interference source located at the applicator position indicated. We start from the right of Fig. 3-7 and move toward the left, as follows:

a) Use YL = Yd, and L = La in (3-5) to determine Ya.

b ) Use YL = 1I(R, + lIYa) and L = Lb in (3-5) to determine Yb

C) Use YL = Yb, L = L, and Vfa = hd in (3-5) and (3-6) to determine Y, and V,.

d) Use Yu = Yld. YL2 = Y, and V* = Vc in (3-7) and (3-8) to determine Yd and Vd

e) Use YL = Yd. L = L,, and Vfa = Vd in (3-5) and (3-6) to determine Ye and V,. f) Use YL = Y p d L = .+in (3-5) to determine Yf

g) Finally, find V, by using Yu = Yf+ Yo, Yu = Ye, and V$ = Vein (3-6).

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3.1.4 Capacitive coupling

When the series induced voltage source VM of Fig. 3-2 is replaced by a shunt induced current source Ihd, equations similar to (3-1) and (3-2) can be derived. The

resulting node voltages are

Figure 3-9 shows the driver iVld and receiver (V . ) voltages corresponding to

Iind = 10 mA for three applicator positions (at the middle and each end of the line). As in the case of inductive coupling, the 200 MHz quaxter wavelength resonance is apparent, and the voltage at the receiver, V4@ is greater than that at the driver, V1@ due to the high receiver input impedance. However, with capacitive coupling the voltage is lowest with the interference close to the driver (Ll = 0). since the low impedance driver effectively shorts the adjacent shunt induced current source. This is in contrast to the inductive cou- pling case, where the voltage was lowest with the interference close to the receiver (L, = L).

Figure 3-9. Example of static node voltages (capacitive coupling).

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3.2 Dynamic Analysis

32.1 Inductive coupling

We tum next to dynamic analysis. in which the driver impedance switches from Z, to 26 at time t = 0 as shown in Fig. 3-10. A transmission line having propagation time tp = L/vp links the driver and the receiver. In actual operation, the impedance switches back to 2, after the logic transition. Dynamic analysis covers the case of failures during the logic transition.

In the previous section we had vind = Re{Ynd eJa'} . Since the transmission line impedances remained constant, we had no time reference so the phase of the interference was irrelevant In the dynamic case, however, the timing relationship between the digital signal and the interference is important We use as a time reference for the interfering sig- nal the time t, at which the interference-free digital signal at the applicator position crosses the switching threshold. That is, ?ind = Re{lxnd lei(m('-'f)+e)}.

Figure 3- 10. Equivalent transmission line circuit for deter- mining dynamic node voltages.

Before the impedance switches, the voltages are those described in the previous section (for the static case). When the switch closes at t = 0, and thus the reflection coeffi- cient at node 1 becomes Tb (corresponding to Zb), a wave is launched from node 1 and propagates down the transmission line in time tp. The resulting voltage at node 4 for

t 2 t p is

whek 6 = rJle-YzL and 6 , = r,r,e-yzL (see Appendix C for derivation). The voltage

at node 1 can be found in a similar manner. These voltages depend on n, the number of

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round-uip transmission line traversals that occur between t = t,, (when the effect of the switch closing is first apparent at node 4), and the time of interest 2:

Here the floor00 function rounds the argument X to the nearest integer toward minus infity. When n = 0 (i.e. t,, c: t c 3 t,,)

and when L + 0 (so that t,, -+ 0 and n + p.),

Equation (3-14) is identical to (3-2) for L + 0 and with Zb replaced by 2,. That is, for short lines the impedance change, neglecting transient effects, takes effect immediately (i.e. a new static situation is in effect).

Figure 3-11 shows the predicted 1% I from (3-2) and (3-11) for various interfer- ence frequencies. The transmission line has = 100 R, vp = 2 x lo8 d s , and L = 25 cm. and the interference Vhd = 0.1 V is adjacent to node 1. The loads used here are those developed in Sec. 3.3. This shows that the frequencies at which the node voltages are maximum change as time progresses (i.e. as n increases).

. "0 50 100 150 200 250 300 350 400 450 500 Fresuency (MHz)

Figure 511. Example of dynamic node voltages.

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The time domain waveform envelope for 300 hlHz interference (where, according to Fig. 3-1 1, the effect of n is pronounced) is shown in Fig. 3-12a. Here the impedance at node 1 switches from Z, to Zb at t = 0, so the static case exists at node 4 until t = tp = 1.25 ns. The time domain waveforms for four values of phase I$ (spaced by 90°) are shown in Fig. 3-12b, where the voltage corresponding to I$ = O0 is emphasized. The discontinuities in these voltages are not physical; the addition of the transient response provides more realistic waveforms, as shown in Fig. 3-12c. The transient response is based on a time constant of 0.2 ns. corresponding to 2 pF in parallel with 100 R

I - 2 - 1 0 1 2 3 4 5 6 7 8

Tune Ins)

Figure 3-12. Waveforms at 300 MHz: (a) envelope. (b) without tnnsient; (c) with transient

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32.2 Capacitive coupling

For the case of dynamic capacitive interference (see See. 3.1.4 for static analysis). the voltage at node 4, as derived in Appendix C, is

When n = 0 (i.e. 5 c t c 3 tp).

andwhenL +O (i.e.5 +O andn +m,sothatcn+O),

Equation (3-17) is identical to (3-10) for L + 0 and with Zb replaced by Z,,. That is, for short lines the impedance change takes effect immediately (as seen in the previous sec- tion).

Figure 3-13 shows the predicted lV, 1 from (3-10) and (3-15) for various frequen- . . cies. The transmission line has Zo = 100 R, v, = 2 x lo8 mls, and L = 25 cm, and the interference Ih, = 10 mA is adjacent to node 1. The loads used here are those developed in Sec. 3.3. This shows that the frequencies of maximum node voltages change as time progresses (i.e. n increases). This analysis does not consider the finite size of the applica- tor, nor does it include transient effects; these may be added as in Sec. 3.2.1.

0 50 100 150 200 250 300 350 400 450 500

Figure 3-13. Example of dynamic V4: capacitive applicator.

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3 3 Digital Component Equivalent Impedances

Figure 3-1 shows the target transmission line with the driver and receiver, which consist of non-linear m i s t o r circuits. In Fig. 3-2 and Fig. 3-10 the driver and receiver have been replaced by lumped equivalent circuits. In this section we show how the values of these lumped loads are determined. Here we consider the case of representative CMOS drivers (Northern Telecom's 0.8 pn process, available through the Canadian Microelec- tronics Corporation). The equivalent circuits are determined by running HSPICE simula- tions on the extracted netlists of the driver and receiver cells.

33.1 Receiver

The representative receiver consists of a CMOS inverter chain preceded by input protection circuitry, as shown in Fig. 3-14a. The impedance looking into node 4, Zl, is assumed not to change with the input signal, provided that the protection diodes are reverse biased (i.e. the input voltage is bounded by -Vd and Vdd+Vd. where Vd is the for- ward-biased diode drop and Vdd is the supply voltage). This impedance is represented by the equivalent circuit shown in Fig. 3-14b. The capacitances in the equivalent circuit are derived from small-signal swept-frequency input impedance simulations of the receiver with its input in steady state (either high or low). The resistance Rl is determined d i i t l y from the input driver netlist For the representative receiver, RI = 833 R. Cd = 40 fF, and Ci = 265 fF. The interference voltage at node 5 can be found from

Figure 3-14. Receiver (a) tnnsistor circuit and (b) equiva- lent circuil at input

33.2 Driver

The representative CMOS driver is shown in Fig. 3-15% and each transistor is labe'lled with its channel length. The equivalent circuit looking from the output into the driver is shown in Fig. 3-15b. The driver is divided into four stages. Stage 1 takes its

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input from the chip core logic. Stage 2 splits the output from stage 1 into two components, one for the pull-up circuitry (driving n9) and one for the pull-down circuiby (driving 1113).

Stage 3, the pre-driver stage, consists of mismatched pairs (i.e. one transistor in each inverter pair is much wider than the other); this ensures that, for a rising output. the nmos output transistors driven by n7 and n15 turn off before the pmos output transistors driven by no and n9 begin to conduct (and vice versa for a falling output). This prevents the direct current flow from the supply (Vdd) to ground which is associated with a typical inverter (e.g. Stage 1). Stage 4, the output stage, drives the off-chip load. The transistors in this stage drive large currents, so the prevention of direct path cumnt is imponant Fig- ure 3-16 shows the stage 4 input and output signals for a rising output These curves were obtained from HSPICE simulations of the representative output driver.

Stage 1 Stage2 i '

Output

\ d

Figure 3-15. Driver (a) transistor circuit with gate length (in pm) and (b) equivalent circuit at output

The output impedance of this driver is used to determine the interference voltage on the transmission l i e . When the driver is in the static state (i.e. not switching), one set

(nmos or pmos) of the output transistors is off and the other set operates in the triode

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region. The impedance Z, is thus the mode channel resistance in parallel with a capaci- tance tern. This output impedance can be determined using swept-frequency small signal analysis, as was done for the receiver, For the representative output driver, Ro = 41 Rand Co = 2.1 pF. As the input switches, the output transistors that were in triode turn off abruptly, while the output transistors that were off enter the samt ion and then the eiode region of operation. The impedance during switching. Zb thus consists of a capacitance (assumed to be the same as in the static case) in parallel with a much higher channel satu- ration resistance. This driver output resistance, consisting of the parallel combination of the channel resistances of the four output transistors, is shown in Fig. 3-17 for a rising edge at the output The driver output resistance changes with time as the voltages at the input and output of each output transistor. and thus the operating point on the transistor I-V curve, changes. The output driver reactance, corresponding to Co = 2.1 pF, is also

shown in fig. 3-17 for several frequencies. While the transistors are in saturation, the capacitive reactance is much less than the channel resistance, except at low frequencies. Thus during switching the output resistance Ro is modeled as infinite.

Figure 3-16. Driver voltages: rising edge at output

- - - Reeclaoceat 10hfHz . Reectaoce at 100 MHz '

1 0 05 1 1.5 2 25 3 35 4 4.5 5

Tme (ns)

Figure 3-17. Driver Ro compared with reactance (l/OC,).

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3.4 Conclusions

In this chapter we developed theoretical expressions for the voltage at a transmis- sion line node (any position on the line, but typically the terminals of a driver or a receiver) due to an interfering voltage or current source. The predicted resonant behavior of such a system is shown. including the frequency and applicator position dependence of the node voltages. Both static and dynamic cases are considered. This theory can be used to predict the frequencies and applicator positions most likely to cause failure of the devices associated with a particular target w k . Conversely, given the frequency and applicator positions associated with a failure, this theory can predict the node at which the induced voltage is maximum. The device at this node is expected to be that causing the

failure.

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Chapter 4

SIGNAL HANDOVER FAILURE

In many printed circuit boards, a single track is shared by several drivers. In such a multiplexed system, only one driver controls the track (i.e. is active) at any given time.

while the other drivers are disabled (tri-stated, in high-impedance states). During the han- dover of control of the track from one driver to another, the track is not driven. Rather, a resistor (e.g. 1 kR) connecting the track to the supply voltage ensures that the track is pulled up to a valid logic level.

When a track is in this state (pulled-up rather than driven), it is particularly suscep-

tible to EMI. This effect was discovered during susceptibility scans of the EUT, as

described in Sec. 4.1. It can be considered as a design issue since it only occurs with a large pull-up resisto;. The dependence of this failure on the interference frequency and

coupling position is predicted and measured in Sec. 4.2. A test board was consuucted and used to further investigate the effects of the interference frequency and coupling position on this failure. In Sec. 4.3 these experimental results are compared with the theory devel- oped in Chapter 3. Finally, the mechanism causing the failure (rectification of the inter-

ference signal at the disabled drivers) is described in Sec. 4.4.

4.1 Failure as Observed on EUT

The address strobe (/AS) track on the EUT is one case of the aforementioned mul-

tiplexed track. The layout of this track is shown in Fig. 4-1. The Ethernet controller (which includes the LANCE chip, the Ethernet PAL and the LED PAL), when enabled,

periodically rakes control of /AS. The interference causes a failure during this handover from the CPU to the Ethernet controller, while both drives are in the high-impedance state. The timing of a normal handover [58] is shown in Fig. 4-2i. The sequence is:

a) The Ethernet controller requests control of the /AS track, by asserting lBRETH (bus request - Ethernet).

b) The CPU signals its intention to release control of /AS by asserting lBGETH (bus grant - Ethernet).

c) The CPU negates /AS and then releases it (i.e. the driver goes into the high-imped- ance state). /AS is held in the high state by the pull-up resistor.

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d) The Ethernet controller detects the asserted IBGETH and negated /AS, and acknowl- edges its right to seize /AS by asserting IBGACK (bus grant acknowledge) and negat- ing IBRETH.

e) The Ethernet controller uses /AS, then negates IBGACK to end the cycle and return control to CPU.

In the presence of EMI, a failure occurs during this sequence. After the CPU releases /AS, and before the Ethernet controller seizes if both drivers are in the high-impedance state. Interference causes the /AS signal, which is normally pulled high

by the pull-up resistor. to fall to a logic low level. Thus the Ethernet controller cannot seize /AS, and the EUT fails. lhis sequence of events is shown in Fig. 4-2ii.

Figure 4-1. Routing of /AS track, with track lengths (mrn) and driver, receiver, and pull-up resistor positions indicated.

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Figure 4-2. Timiog of /AS handover from CPU to Ethernet controller: (i) normal operation, and (i) failure.

69 /As

'B-

4.2 Frequency a n d Applicator Position Effects o n EUT Failure Threshold

The failure threshold is related to the amount of interference required to cause fail-

ure, as explained in Sec. 2.3.5. The power at failure is the minimum available power (in dBm) at which failure first occurs; the failure threshold is the corresponding induced volt- age Vkd (in dBV). The failure threshold changes with frequency and applicator position. In this section we compare the predicted and measured failure thresholds of the signal han- dover failure. Two applicator positions were chosen for this comparison. The fust posi- tion (applicator position I) is near the DRC, at the centre of the 130 mm tnck running

horizontally across the board. Failures at this position can be seen in the susceptibility map of Fig. 2-22. The second position (applicator position 11) is near the CPU, at the cen- tre of the 36 mm horizontal track The interference power used to generate the susceptibii- ity map of Fig. 2-22 is insufficient to cause failures at this position; however, interference at slightly higher power does cause failures.

- - ...... - -.. .;1!

......................................................................... C) n

..........................................................................

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42.1 Theory

The frequency and applicator position dependence of the /AS handover failure is predicted here using the static analysis of Sec. 3.1.3. The quivalent circuit of the /AS track is shown in Fig. 4-3, which also indicates the two aforementioned applicator posi-

tions. All receivers are assumed to be capacitive with Ci = 10 pF. The pull-up resistorRp, is 5 kf2. The two driver impedances (G, and Zkd) are 10 pF (the driver resistance is neglected since the drivers are in the high-impedance state). We can solve for the voltage at any point on the track caused by the induced voltage source V~ (representing the appli-

cator). Since recfication at the tri-stated drivers is suspected as the failure mechanism here, we solve for the voltages at the CPU driver (Vqu) and at the LED PAL driver (Vied). A revised version of Fig. 4-3, with these voltages indicated and with the applicator in posi- tion I is shown in Fig. 4-4. Note that the strength of the induced voltage source depends on the available power and the applicator height, but does not depend on the applicator position, as discussed in Sec. 2.3.5.

appli? position I applicatqr position II '

Figure 4-3. Equivalent circuit of /AS track, with dimensions in mm; applicator positions are indicated.

nz, El ci BRP" I1zw

Figure 4-4. Equivalent circuit of /AS track with applicator at position I.

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Figures 4-5 and 4-6 show the ratios of the voltages at the drivers, Vq, and Vlu[. to the induced voltage VM as functions of frequency and applicator position Peaks occur

where, for a fued VM, we have large voltages at the nodes where failure is expected to occur (Le. at the drivers). Thus peaks correspond to regions of predicted high susceptibik ity and low failure threshold.

-201 I 0 50 100 150 200 '250 300 350 400 450 5W

Frequency (MHz)

Figure 4-5. Predicted voltage at CPU driver, both drivers in high-impedance state.

Figure 4-6. Predicted voltage at LED PAL driver, both drivers in high-impedance state.

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We would like to consolidate Figs. 4-5 and 4-6 into one graph of the predicted sus-

ceptibility independent of where the failure might be occurring (but dependent on fre- quency and applicator position). We take the voltage Vd,j as the larger of the two driver voltages (Vq, and Vied) at each frequency and applicator position. The result is shown in Fig. 4-7. We assume that the two drivers will react the same way to the same voltage, and so Vd,. is a measure of the susceptibility of the /AS track.

Figure 47. Predicted voltage at drivers (larger of Vcp, and VM).

The failure threshold is the minimum induced voltage V a (in dBV) at which fail-

ure frs t occurs. We would like to derive a predicted failure threshold from the predicted voltage at the drivers shown in Fig. 4-7. F i t we assume that the failure mechanism at the

drivers is frequency independent, and depends only on the voltage magnitude at the driv- ers, Vd+ Next, we assume that failures will occur when Vd,. exceeds a threshold, Vf,il The predicted failure threshold is then the value of V a (in dBV) required to cause Vd,. = V/oil. In Fig. 4-8 we show predicted failure threshold curves for several values of Vfail. We plot the predicted failure threshold with reversed vertical axis (i.e. smaller volt- ages at the top of the graph) so that peaks - where smaller Vind produces Vfail at a driver

-correspond to regions of highest susceptibility. The choice of Vfail is somewhat arbi-

trary but is constnined to a reasonable range. We would not expect, for example, Vfail = -40 dBV or Vfail = +40 dBV.

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Figure 4-8. Predicted failure threshold for several values of Vfoil (heavy lines for applicator position I, light lines for applicator position 11).

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4.2.2 Measurement

The measured power at failure is shown in Fig. 4-9 for the two aforementioned applicator positions. The corresponding failure threshold is shown in Fig. 4-10. Note that the vertical axes are reversed, so that the graph peaks correspond to regions of high sus- ceptibility (low failure threshold). These graphs clearly show that the failure threshold

varies greatly with frequency and applicator position The failures observed using the PartialFill diagnostic were of the "no response"

type explained in Sec. 2.4.2 since the EUT hangs and thus cannot respond to the PC. Sus-

ceptibility tests were also run using the Ethernetm diagnostic described in Sec. 2.4.2, such that the Ethernet controller did not request control of /AS. With this diagnostic, no failures occurred; thus the diagnostic routine aids in identifying the failure.

Figure 4-9. /AS handover: measured power at failure.

Figure 4-10. /AS handovec measured failure threshold.

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42.3 Comparison of theory with measurement

In Fig. 4-11 we compare the measured failure threshold of Fig. 4-10 with the pre- dicted failure threshold of Fig. 4-8. The resonant frequencies and relative strengths of the failures due to the applicator in the two positions are predicted correctly. The predicted failure threshold is based on Vr~, = 16 dBV; this value was chosen to make the predicted curves align with the measurements.

Figure 4-11. Measured and predicted failure thresholds.

We conclude from the above comparison that the theory predicts the frequency and applicator position dependence of the failure threshold correctly. However, the failure threshold levels are not predicted; rather, they are inferred from the value of Vroil required to align the prediction with the measurement A possible explanation for the discrepancy between measurement and prediction at higher frequencies (above 250 MHz) is given in the discussion of the failure mechanism. Sec. 4.4.

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4.3 Test Board

A test board, shown in Fig. 4-12, was constructed to study the /AS handover fail- ure in more detail. The test circuit consists of a single driver (A) with high impedance control, and a single receiver (B). The output of A is connected through a 0.25 m, 75 R track to the input of B. The applicator is positioned above the target track. Both Tn and CMOS logic is tested, in turn, by using 74LS367 and 74HC367 hi-state buffers. The /EN signal is held high so that the driver is in the high-impedance state, and the target track is

pulled to logic high through the 5000 R pull-up resistor Rp,. Interference is coupled to the target track with the applicator of Sec. 2.3.4 located 1 mm above the test track, and the voltages on the test board are measured at nodes 1 and 5.

Figure 4-12. /AS handover failure test board.

The frequency and applicator position effects on the voltage at the driver are fust investigated. The predicted voltage at node 1 is calculated from the static theory devel- oped in Ch. 3:

with L = 25 cm and y = a + jabp, where vp = 2 x lo8 m/s and a is as shown in Fig. 2-20. The driver output impedance consists of a capacitance of 10 pF for the LS buffer (13 pF

for the HC buffer) in parallel with the pull-up resistor, the receiver input impedance con- sists of a capacitance of 5 pF for the LS buffer (5 pF in series with a 10 R resistance for the HC buffer). The predicted and measured voltages at node 1, using the LS buffers, are compared in Fig. 4-13 for three applicator positions. The measurements were made from

the underside of the test board, using a high-impedance probe connected between the ground plane and a very short wire passing from node 1, through an adjacent hole, to the probe tip. The signal from the probe is measured using a vector network analyzer.

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20

10 3 - b. 0 . b- - -10

-20 0 50 100 150 200 250 300 350 400 450 500

Frequency (MHz)

-20 1 I 0 50 100 150 200 250 300 350 400 450 500

Frequency (MHz)

-20 1 I 0 50 100 150 200 250 300 350 400 450 500

Frequency (MHz)

Figure 4-13. Measured and predicted peak interference voltage at LS buffer A output for applicator centre (a) 3.5 cm; (b) 12.5 cm; and (c) 21.5 cm from the driver.

Page 64: Electromagnetic Interference Stress Testing · 2020. 4. 7. · Electromagnetic Interference Stress Testing PhD. Thesis, 1998 Leesa Marie MacLeod Department of Electrical and Computer

The saongly resonant behavior and the effect of the applicator position are appar- ent in Fig. 4-13. We now consider how the failure threshold (as opposed to the node 1 voltage) changes with frequency. Recall that we are monitoring the voltages at nodes 1

and 5 (here we use an oscilloscope, rather than a network analyzer. to measure the node voltages). We must specify what ~0nStitUteS a failure in terns of these voltages. Here we consider two failures.

Failure I occurs when the minimum voltage at node 1 falls below 4 V. Since the interference-free voltage at node 1 is 5 V, failure I corresponds to an interference voltage

of 1 V at node 1, that is Vl = 1 V. This is a very strict failure criterion, since a logic level of 4 V is interpreted correctly as a high level by the receiver. Figure 4-14 shows the mea- sured power at failure I as a function of frequency with the applicator 3.5 cm from node l; the corresponding measured failure threshold is shown in Fig. 4-15.

20

- $23 9 D 3 30 - t * 35 a0

40 0 50 100 150 200 250 300 350 400 450 500

Frequency W)

Figure 4-14. Measured power at failure I with applicator 3.5 cm from TPl.

Figure 4-15. Measured failure threshold for failure I with applicator 3.5 cm fmm TPI.

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Equation (4-1) is used to predict the failure threshold, i.e. the Vw required to cause VI = 1 V = 0 dBV. That is, we use Vail = 1 V. The level-shifting used in plotting the predicted failure threshold of the EUT /AS handover failure in Sec. 4.2.3 is not required here, since by d e f ~ t i o n failure I occurs when VI = 1 V.

Figure 4-16. Measured and predicted failure threshold with applicator 3.5 cm from the driver, for failure L

Failure II occurs when the time-average voltage at the receiver output (node 5). which has an interference-free value of 4 V for LS buffers and 5 V for HC buffers, falls below 3 V. This is a more realistic failure criterion than failure I, since it requires a change at the output of the test board. Figure 4-17 shows the measured power at failure I1 as a function of frequency with the applicator 3.5 cm from node 1; the corresponding mea- sured failure threshold is shown in Fig. 4-18.

Figure 4-17. Measured power at failure I1 with applicator 3.5 cm from the driver.

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Figure 4-18. Measured failure threshold for failure II with applicator 3.5 cm from the driver.

As for failure I, equation (4-1) is used to predict the failure threshold. Here, we use Vfiil = 10 dBV. The measured and predicted failure thresholds are compared in Fig. 4-19.

Figure 4-19. Measured and predicted failure threshold with applicator 3.5 cm from the driver, for failure 11.

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4.4 Failure Mechanism

The theory developed in Ch. 3 predicts the EMI voltage at the output of the driver. Here we describe how this voltage affects the operation of the driver. The circuit of the LS driver, from [59], is shown in Fig. 4-20, where the Schottky diodes associated with Q1, 42, and Q5 are not shown explicitly. This figure also shows the external pull-up resistor Rp, and the equivalent circuit looking into the target track (represented by Veq and Zeq). Note that V, and Ze4 change with interference frequency and applicator position.

Figure 4-20. LS-lTL driver circuit

When the Output Enable signal is low, under normal operating conditions transis- tors 43 and Q4 are off and the output is pulled high by Rp,. In the presence of EMI, the interference appearing at the driver output couples to the base of the pull-down transistor 43 through the collector-base junction capacitance and through the capacitance CD3 of Schottky diode D3. If the coupled interference is sufficiently large (i.e. the peaks of Vk3 exceed approximately 0.7 V) then transistor 43 will turn on for a portion of the interfer- ence cycle, thus acting as a rectifier. The DC portion of the 43 collector current is sup- plied through the pull-up resistor Rp, (we assume Q4 remains off and Zeq is reactive). The corresponding voltage drop across Rp, may be sufficient to force the output node to a logic low level, and thus cause a logic error.

Transient simulation was performed using the Libra circuit simulator on the circuit of Fig. 4-20 in order to confum the failure mechanism. The transistor and diode parame-

Page 68: Electromagnetic Interference Stress Testing · 2020. 4. 7. · Electromagnetic Interference Stress Testing PhD. Thesis, 1998 Leesa Marie MacLeod Department of Electrical and Computer

ten were taken from Hodges and Jackson 1591, the load impedance Zq corresponds to a capacitance of 10 pF, and the interference voltage source Vcq is 2 V at 200 MHz Sirnula- tions were run for three cases: (a) R, = 5 ki2 and CD3 = 2 pF, (b) R,. = 1 kR and CD3 = 2 pF. and (c) R, = 5 kR and CD3 = 0 pF. Results are S~OWII in fig. 4-21.

-21 , I 0 m loo0 1m

The (ns)

Figure 4-21. Simulation results: (a) R, = 5 kR and CD3 = 2 pF, (b)R,.= 1 ki2andCD3=2pF,and(c)R,=SMandCD3=OpF.

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Figure 4-21 illustrates two key points. Fit, by decreasing the value of R, from

5 kR to 1 kR we can eliminate the failure. Also, by reducing the parasitic capacitance from the collector of 4 3 to its base we can eliminate the failure.

Since the failure mechanism relies on feedback from the collector to the base of Q3 - through the parasitic collector-base capacitance - the portion of Veq appearing at the base of Q3 increases with frequency. Thus the interference level at the driver output required to cause failure decreases with frequency, so the susceptibility increases with fre- quency. This effect is seen in the measured results of Fig. 4-11.

4 5 Conclusions

In this chapter we identify and characterize an EUT failure encountered during sus-

ceptibility scans. This failure occurs due to rectification at a tri-stated driver on the /AS track, and only occurs when both drivers are in the high-impedance state. The resistor used to pull the tri-stated line to a valid logic state is critical: a larger resistor makes the circuit more susceptible to interference. The frequency and applicator position depen-

dence of the failure were correctly predicted by the theory developed in Ch. 3. A test board with characteristics similar to the /AS tnck was designed. Experiments confirm the failure characteristics. Since the interference affects the operation of the driver. we refer to this failure as being "direct at driver".

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Chapter 5

WEAK MEMORY CHIP

The EUr susceptibility map of Fig. 2-22 shows three areas of susceptibility. The area associated with the /AS bandover failure was described in Ch. 4; the other two areas

are due to a weak dynamic random access memory @RAM) chip. Recall that a weak component is one that is substandard in some way yet functions correctly in a stress-free environment This chapter describes the failure associated with this weak chip. The memory configuration of the EUT is fust presented, followed by a description of the weak chip. Two methods of detecting the weak chip are explained; the fust is based on intetfer- ence susceptibility, the focus of this thesis, and the second uses reduced supply voltage.

5.1 EUT Memory Configuration

Figure 5-1 shows the A4 ttack as seen from the solder side of the EUT. This track canies an address signal from the DRAM controller @RC) to the DRAM chips. The 16 256k-by4bit DRAM chips are labelled 0-F. The memory is organized into 4 banks. as described in Table 5-1. Figure 5-2 shows the DRAM chip pinout, Fig. 5-3 shows the functional model of the chip, and Fig. 5-4 is a sketch of a typical DRAM cell [60].

Figure 5-1. Routing of A4 track, with track lengths (in mm), and driver, receiver, and resistor positions indicated.

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Table 5-1 EUT Memory Organization

U02 - U04 WE YO3 Rx-3 -

C AS NC OE A0 A8 A1 A7 A2 A6 A3 A5 Vdd A4

L -

AO-8: RAS: CAS: WE: OE: Y O 1 4 Vdd: vss: NC:

Address inputs Row address strobe Column address strobe Write enable Output enable Data input output +5 v supply 0 v supply No connection

Figure 92. Memory chip for EUT.

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Figure 5-3. Functional model of DRAM chip [60].

Enhancement mode FET

Capacitor

Figure 5-4. Memory cell structure.

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5 2 Inducing Weakness in a Memory Chip

A weak component is one that is substandard in some way yet functions cornfly in a no-stress situation, as explained in Ch. 1. During susceptibity scans of the EUT, a weak memory chip was discovered. The events causing the weakness in this chip, and the way in which its weakness is exhibited, are explained here. Since the use of EM1 stress testing to locate weak components is of great interesf we tried to create additional weak chips by various means. These trials were unsuccessful except for a repetition of the orig- inal weakening event

The original weak chip was created during a susceptibility scan mishap. A capaci- tive applicator, intended to sit above the EUT, accidentally contacted the EUTin the vicin-

ity of the memory. After this mishap two of the memory chips, in locations C and D (see Fig. 5-1). no longer functioned and had to be replaced. After these chips were replaced, the diagnostic passed under normal operating conditions. However, when interference

was applied near the memory chips, errors occurred in the chip in position B (ie. bits 12-15 of the data stored in addresses 1OOOOO to 17FFFF). This chip was exchanged with the chip in position A; subsequefit application of interference caused errors in data loca- tions stored in position A (bits 8-22 of the data stored in addresses 1OOOOO to 17FFFF). The errors were thus found to be associated with the chip itself (hereafter referred to as Weakl) rather than with the circuit board.

Since tests to fmd the weak chip are an important part of this thesis, we want to ensure that we can replace the Weakl chip with aqother weak chip should Weakl some-

how be destroyed. In order to induce weakness deliberately, the circumstances of the orig- inal weakening incident were reproduced as closely as possible. The capacitive applicator, excited at 125 MHz and 40 dBm, was dragged across the solder side of the EUT. The chip in position 8 was destroyed and that in location C was weakened. Thus the weakening of Weakl was not an isolated event; rather, it is repeatable.

As described above, a memory chip can be weakened through direct contact with the applicator. A study was conducted to determine if other phenomena, in particular elec-

trostatic discharge (ESD), can also weaken a chip. Several DRAM chips were tested, and each was given an identif~er (e.g. Al). Results of ESD, mechanical, and electrical over-

stress (EOS) tests on these chips are shown in Table 5-2. Although several chips were destroyed, no weak chips were produced by these stresses.

More refined tests using a physical ESD simulator were performed to try to induce weakness in a memory chip. Multiple (-20) discharges were applied to each pin of a memory chip, which was then tested to see if it had been destroyed or put into a weak state. The chip operated normally after discharges at 2.5 kV and below. A 3 kV discharge

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either left the chip unharmed or destroyed i t Tests at 3 kV also revealed an appmnt EMI-related precipitation of failure: a chip that had been subjected to ESD discharges operated properly under normal operating conditions but then began to diplay errors in the presence of interference. These errors continued after the interference was removed and normal operating conditions resumed; that is, the chip had been destroyed. This phe- nomenon was observed twice during the course of the experiments, but since it destroys rather than weakens the chip (a weak chip exhibits errors under EM1 stress but the inter- ference does not induce permanent failure), further studies were not pursued.

It was determined that an electrostatic discharge at 3 kV causes the memory chip

either tc be destroyed or to remain properly functional, but not to become weak. This is in agreement with 1611, which concludes that latent failures (i.e. weak chips) caused by ESD

ate unlikely to be a major reliability hazard since they occur only for a very narrow range of discharge voltages.

Table 5-2 Attempts at Weakening DRAM Chips (in Chronological Order)

IESD 11.23.4 k~ discharge to gnd through pins l ~ l , A 2 , A 3 , ~ 4 1 - 1 - 1

E O S ~

Mech

EOS

Type

ESDa

~EOS )+9 V across each pin to gnd I A ~ , A ~ , N ~ I - I - I

Chips Tested

Al,A2,A3,A4

Description

rub cotton against synthetic; pick up chip

+6 V across pwrlgnd pins

drop 1 m onto concrete floor

+8 V across owrknd oins

EOS

EOS

EOS

EOS

Weakened

- Al,A2,A3,A4

Al,A2,A3,A4

Al.A2,A3,A4

+8 V across each pin to gnd

+ 8.5 V across each pin to gnd

+9 V across each pin to gnd

+9.5 V across each pin to gnd

EOS

EOS

Destroyed

- - -

M A 4

A1#

M A 4

a Elecfmslatic discharge. b. Electrical overstress.

-9 V across pwrlgnd pins

-8.5 V across pwrlgnd pins

A2

A3

N1

A1

N1

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53 Use of a Susceptibility Scan to Detect a Weak Chip

The EUT susceptibility map of Fig. 2-22 shows failures with the applicator in sev- eral positions. The two positions associated with the weak chip are investigated here. With reference to Fig. 5-1, these are applicator position III. above the 42 am horizontal segment near the board edge, and applicator position IV, above the 31 mm horizontal seg- ment Susceptibility tests were run with the planar inductive applicator (see Sec. 2.3.4) in these two positions. The goal of these measurements is to determine if the theory of Ch. 3 conectly predicts (i) the frequency and applicator position dependence of the susceptibii- ity. and (u) how this dependence changes as the weak chip is moved. If this validation is

successful, the theory can be used to determine which chip attached to a particular tnck might be responsible for failures.

First we confm that the failure threshold does change with the location of the weak chip. With the applicator in position III, the power at failure was measured with the Weakl chip in various locations. The results for an interference frequency of 200 MHz are shown in Fig. 5-5, where the inset shows the memory chip locations. The power at

failure, and thus the failure threshold, changes over a large range (8 dB) as the Weakl chip is relocated. In the next sections we use the two Weakl chip locations that cause the extremes in Fig. 5-5, i.e. positions 8 and F.

Weakl lomion

Figure 5-5. Power at failure as a function of weak chip location, with applicator at Position IfI and 200 MHz inter- ference. Inset shows weak chip locations.

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5.3.1 Theory

Figure 5-6 shows the A4 track equivalent circuif which is used to predict the fail- ure threshold. The distance between successive DRAM chips is 11 mm. The series resis- tance R, is 39 Q and the DRC impedance Zd, corresponds to an output capacitance of 10 pF (typical value from datasheet) in parallel with the "on" resistance (estimated to be 30 R). The DRAM datasheet gives a maximum receiver input capacitance Ci of 6 pF; here we try, in turn, Ci = 6 pF and Ci = 3 pF. The predicted failure threshold based on Ci = 3 pF matches the measurement more closely, as will be shown in the following sec-

tions.

Figure 5-6. Equivalent circuit of A4 track, with each DRAM impedance labelled with the chip position. Track lengths are labelled in mm.

Figure 5-7. Equivalent circuit of A4 track, with applicator at position III.

As mentioned in the previous section, we will consider two applicator positions

@I and N) and two Weak1 chip locations (8 and F). In Fig. 5-7 the voltages at the two

chip locations are indicated on the equivalent circuit with the applicator at position III. In Fig. 5-8 the predicted voltage at chip location 8, V8, for the two aforementioned applicator positions is plotted,.for the two values of Ci. Similarly, the predicted voltage at chip loca- tion F, VF, is shown in Fig. 5-9. Note that these voltages are not plotted d i i t l y , but as ratios with respect to Vhd. As in Ch. 4, the predicted failure threshold is found by deter- mining the minimum VM required to cause that node voltages, Vg or VF, to reach a failure threshold Gil . This final step will be taken in Sec. 5.3.3.

. Figures 5-8 and 5-9 show that the predicted node voltages (and thus the expected failure threshold) change markedly with applicator position. Also, the frequency and applicator position dependencies of V8 are very different from those of VF.

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- A p p l h p o d t i ~ m - 5 - Appliutor position N

- -10 -

0 50 100 150 200 250 300 350 400 450 500 Fresuency (MHz)

Figure 5-8. Predicted voltage at location 8: Ci = (a) 6 pF, (b) 3 pF.

Applicalor position N

- 0

. -5 >k - -10

-15 0 50 100 150 200 250 300 350 400 450 500

Frequency (MHz)

Figure 19. Predicted voltage at location F: Ci = (a) 6 pF, (b) 3 pF.

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53.2 Measurement

The measured power at failure with the Weakl chip in location 8 is shown in Fig. 5-10. with the corresponding failure threshold in Fig. 5-11. The power at failure and the failure threshold with the Weakl chip in location Fare shown in Figs. 5-12 and 5-13.

Figure 5-10. Measured power at failure vs. frequency and applicator position, with the Weakl chip in location 8.

I - ApplicatorpositionDI M Applicator position N

*

Figure 5-11. Measured failure threshold vs. frequency and applicator position, with the Weakl chip in location 8.

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Figure 5-12. Measured power at failure vs. frequency and applicator position, with the Weakl chip in location F.

-15 , 1 Applicator position III M Applicator position N

-10 - m S

-5-

0

Figure 5-13. Measured failure threshold vs. frequency and applicator position, with the Weakl chip in location F.

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53.3 Comparison of theory with measurement

When the location of the weak chip is unknown, it can be deduced by comparing the measured failure threshold with the predicted voltages at each of the possible weak chip locations. For example, the two failure curves of Fig. 5-11 (one for each of the two applicator positions) are much more similar in shape to the curves of Fig. 5-8 (ie. V8) than they are to the curves of Fig. 5-9 (i.e. VF). Indeed, the Weakl chip was in location 8 for the measurement shown in Fig. 5-11. Also, we can deduce the location of the Weakl chip corresponding to the measured failure threshold of Fig. 5-13 by comparing the measured failure thresholds with the predicted Vs and VF, and noting the similarity to VF.

In order to compare with the measured failure thresholds, we must convert the pre-

dicted voltages of Sec. 5.3.1 to predicted failure thresholds. We use the Ci = 3 pF curves

as these correspond more closely to the measured results. As in Ch. 4, we assume that the

chip will fail when the voltage at its terminal reaches VIail. We choose Fail so that the pre- dicted failure threshold is close to the measured failure threshold (changing Vfail shifts the predicted curves with respect to the measured curves but does not change thcir shapes). Here we use Gil = -5 dBV.

The measured and predicted failure thresholds with the Weakl chip in location 8

are compared in Fig. 5-14. Although the correspondence is not perfect, the essential fea- tures are predicted correctly. In particular, the susceptibility is higher when the applicator

is near the board edge (applicator position III) than when it is near DRAM1 (applicator position IV). The comparison of measurement with prediction with Weakl in location F is shown in Fig. 5-15. Again, the essential features of thz frequency and coupling position

effects are correctly predicted by the theory.

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-15

s-10 m S

i -5

$ 0 D 3 & 5

10 0 50 100 150 200 250 30D 350 400 450 500

Frequency (MHz)

Figure 5-14. Measured and predicted failure thresholds with the Weakl chip in location 8.

- ApplicaInr position ID (Rcd.) Applisalor position N (Meas.) Applisalcn position N (Rcd.)

Frequency (MHz)

Figure 5-15. Measured and predicted failure thresholds with the Weakl chip in location F.

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5.4 Use of Lowered Supply Voltage to Detect Weak Memory Chip

In this section we demonstrate that EM1 is not the only stress that will cause the Weakl chip to fail. We show that this chip also fails with reduced supply voltage. We also show that the diagnostic program can be used to detect the position of the Weakl chip. With lowered supply voltage, we must rely on the diagnostic to locate the failing chip; with interference susceptibility testing, we have additional information such as the

applicator position and frequency dependence of the failure. Board failures associated with the capacitive applicator (Sec. 2.3.2) were found to

depend strongly on the ground return through the power supply. It was thus hypothesized that changing the supply voltage might cause the Weakl chip to fail. This hypothesis is

supported by Hao and McClusky [62], who found that by using very low voltage testing, weak CMOS chips wiU malfunction while good chips will continue to function correctly.

The weakness observed in 1621 was traced to resistive shorts (for which pattern-dependent faults were displayed) and hot camer damage.

The diagnostic CompleteFill was run repeatedly as the EUT supply voltage was varied. 'Ihe number of memory addresses at which failures occurred was recorded as a

percentage of the number of memory addresses tested. The experimental results in Table 5-3 show that the Weakl chip failure does indeed depend on the supply voltage.

Table 5-3 Effect of Supply Voltage on W

3.87

3.83 1.94

21.89

akl Failures

As the diagnostic results were analyzed, it was discovered that only those data bits corresponding to the position of the Weakl chip were in error. Additionally, while the ermr is associated with the receiver (the Weakl chip), it is not due to a simple misinterpre-

tation of the desired address. If this were so, co error would be registered if the chip con- tainbd all the same data (e.g. all zeros). Here invference at the A4 input pin causes a change at the data output of the chip; we call this a feedthrough failure.

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5.5 Additional Failure Characteristics

During the course of susceptibility scans involving the Weakl chip, a lack of repeatability was noticed. This was found to be due to heating effects; that is, susceptibii- ity tests run when the chip is cool, as it is when the EUT is fmt turned on, show a higher failure threshold (i.e. less susceptibility) than when the chip is warm, after the EUT has

been powered up for some time. This temperature dependence is shown in Fig. 5-16. Test A was started just after the EUT, which had been off for 12 hours, was turned on. The tri- als are spaced 1 minute apart Test B was started 30 minutes after the end of Test A; that is, there is a 30 minute gap between tests 33 and 34. After Test B completed. all of the excitation and measurement equipment was powered down; only the EUT remained pow- ered. One hour later all the equipment was powered up and Test C was initiated. From these results, it is evident that the failure threshold s t a b i i s after about 30 minutes. All

results shown in this chapter (other than those in Fig. 5-16) were preceded by a minimum 30 minute warm-up period.

-0 10 20 30 40 50 60 70 80 90 100 Trial #

Figure 516. Temperature dependence of Weakl failure threshold.

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5.6 Conclusions

A weak chip was found to fail under the stress of electromagnetic interference. The diagnostic program fails due to a weak DRAM chip returning incorrect data when interference is coupled to one of the momory address tracks. A4. This failure occurs in the address and data range compondiig to the physical location of the weak chip, moving with it as it is used in different locations. The failure is dependent on the interference fre- quency, the applicator position along A4, and the location of the weak chip. Figures 5-14 and 5-15 show that this measured dependency is correctly predicted by the theory devel- oped in Ch. 3. The failure also depends on the weak chip temperature. The failure involves interaction within the weak chip; the A4 pin is the enuy point for the interference but does not appear to be otherwise involved in the failure, in that the failure is not depen- dent on the particular state of A4. This failure is thus classified as a feedthrough failure.

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Chapter 6

EMI-INDUCED DELAY IN DIGITAL CIRCUITS

6.1 Introduction

In Ch. 3 we found the voltages developed at the ends of a transmission line due to an interference source. In this chapter we study how this interference can cause a delay in the logic hansition at the output of a digital circuit A representative circuit is shown in Fig. 6-1, where the hack (transmission line) has a driver at node 1, a receiver at node 4, and interference inductively coupled at nodes 2-3. The circuit output is at node 6.

The following notation is used in this chapter. the interference voitage is

Find = Re{Vindeja} = IVindlcos(co(t- tJ +$I), V, and V , are the phasor interfer- ence voltages at node x before and after switching at t = 0. % is the time-domain voltage at node x without interference. and a = & + Re{V, eJm'} is the time-domain voltage

at node x with interference. Section 6.2 outlines the general procedure used to find the interference-induced

delay. Thii includes the dependence of the output slew rate of a receiver on its input slew rate, illustrated using measurements performed by Laurin [6]. In Sec. 6.3 results derived

from the theory of Sec. 6.2 are compared with Laurin's measured induced delays for capacitive coupling to a negligibly short transmission line. Observations are made regard- ing the effect of interference frequency and amplitude on the induced delay. In Sec. 6.4 measurements of induced delay due to inductive coupling to a transmission line are com-

pared with theoretical predictions. Section 6.5 shows the comparison between simulations using HSPICE and predictions using the theory of this chapter.

Figure 6-1. Equivalent circuit for induced delay due to inductively coupled interference.

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6.2 General Procedure to Find EMI-Induced Delay

Waveforms illusmaring the induced delay concept are shown in Fig. 6-2. There are two mechanisms that lead to EMI-induced delay. First, the interference voltage super- posed with the interference-free vohge at node 5, % = %, + Re{% ejw') , will cross the switching threshold yw at time t5 rather than t5,. Thus the receiver starts switching - after a delay (with respect to the interference-free case) of At5 = t5 - t5, . Ako, 6 has a different slope than 6,. so the propagation delay through the input driver, tp5,. is modi- fied from the interference-free value t,,,,,. These two effects combine to give the total induced delay at node 6, At,. Note that a negative delay indicates that the pemirbed

hAk lime

waveform crosses the switching threshold before the interference-free waveform.

m - wilhout interference

-\ - wilh interference

Figure 6-2. Timing definitions.

The procedure to find the EMI-induced delay is as follows:

a) Find 4 using frequency-domain analysis, as described in Ch. 3.

b) Find the time domain voltage at node 5, = %, + Re{% eJwr} . C) Solve (6-1) for ts. the time at which % crosses the switching threshold V,

d) Find the EM1 induced delay at node 5, At5 = t5 - t5,.

e) +Find the EM1 induced propagation delay Atps6 = tp5, - tpS6,.

f) Find the EM1 induced delay at node 6, At, = At5 + AtpS6.

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Equation (6-1) can be solved for t5 using a mot-fmding algorithm; however. if only the maximum delay is required for a given interference amplitude, irrespective of the interference phase, then a simplification may be invoked. The interfering signal, when a l l

possible phases are considered, has a constant envelope o f f 16 I . If the interference-free - signal K n has slope sSn = - Kw , then the minimum induced delay is

f5n - to

v s w The propagation delay tpS6 depends on the slope at node 5, s5 = according to

where s6, is the output slope for an infinite input slope, and a is the empirical input slew-rate dependence factor. This empirical formula has the same form as that used by Hodges and Jackson [59]. The propagation delay derived from thii formula is

where tpS6, is the propagation delay for an infinite input slope. Hodges and Jackson [59] express the propagation delay dependence on risetime as

Since the 102-9096 risetime t, = 2(t5 - t0)(0.8), thii corresponds to the previous expres- sion for $56 with a = 0.8. The interference-free propagation delay is

so with interference the propagation delay can be expressed as

from which Atp56 = tp56 - tpSfin and !hen At6 = AtS + !itp56 can be found.

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63.1 Output slew rate dependence on input slew rate

The output slew rate depends on the input slew rate ss and the load capacitance CL according to the relation

where Cg, is the output capacitance and I6 is the current drive of stage 6 (see Kg. 6-1). As

s5 + -, we r i d that S6 + S6 , and the propagation time tpli6 = tPs6- = v 5, where sw l6

C6 = Cg, + CL. The parameters Cg,. 16. and a for the case studied by Laurin in [6] were

found by fitting (6-4) to his measurements (Fig. 3-6 of [6]). The result, shown in Fig. 6-3. corresponds to Cg, = 34 pF. J6 = 3.5 m.4, and a = 0.42.

In [6] the following output slew rate dependence on the input slew rate is used:

In this case. a changes with CL. The diiference between (6-4) and (6-5) is not due to fre- quency effects but rather is due to a diiference in accounting for the slew rate dependence.

Figure 6-3. Node 6 slew rate dependence on slew rate at node 5 and capacitive loading at node 6; measured results from Laurin [6] and predicted results from (6-4).

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6 3 Induced Delay Example: Capacitive Coupling

In this section we consider capacitive coupling to a transmission line of negligible length. This case was considered experimentally by Laurin in [q. Here we use the theory developed in Sec. 6.2 to derive the expected EMI-induced delay, and qualitatively com- pare these predictions with Laurin's experimental results.

Interference that is capacitively coupled to the track between the driver and the

receiver can be represented as a shunt induced current source Id, as shown in Fig. 6-4. In this figure the driver is represented by a current source in parallel with a capacitance, rep

resenting the driver during switching. Comparing this figure with Fig. 6-1 indicates that

here Zb is capacitive (Clo). The receiver is made up of a capacitive input impedance

Z, = l/(jwC,,), a drive current 16, and an output capacitance Ca The receiver is loaded with a capacitance CL.

Figure 6-4. Circuit with capacitively coupled interference.

63.1 Frequency domain derivation of node 4 voltage

In this section we find the induced delay at node 4, the input to the receiver, using the procedure outlined in Sec. 6.2. Since the receiver of Fig. 6-4 has no node 5, we con- sider node 4 instead. First, we determine - using (3-10) and (3-17) - the frequency

domain voltage at node 4 before and after t = 0:

where Z, is the driver output impedance before t = 0. Zb is the driver output impedance after t = 0, and Z1 is the receiver input impedance. If we assume that before switching, the driver impedance is much smaller than the receiver impedance, i.e. Z, a Z,, then

so the interference voltage before switching is neglected.

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After t r 0 the interference component of the receiver voltage is

where C4 = Clo + C4i. Next, we calculate the timedomain voltage at the receiver input by superimposing

the interference on the interference-free waveform. Recall that we take the phase refer- ence at t = t, where t, is the time at which the interference-free voltage at the position of interference coupling (here node 1 and node 4, which are collocated) crosses the switching

threshold. Thus iind = Re{Iindejmf} = IIg4cos(o(r - r,) +I)). and

- - 14.4 V4 = Kn + Re( V4ejmf) = en + - sin(o(t - t,) + $)

oc4

However, for continuity we require that V, = Vm at t = 0. We model the transient

response as (e401,= o- f41,=o)et'T. and we assume that the time constant 'E. is much larger than the time scale of interest here. Referring to Rg. 6-4, this is rwonable in light

of the lack of resistance in the equivalent circui So

- - IIinA V4 = Kn + -(sin(o(r- t,) + I)) - sin(- or, +I)))

oc4 (6-6)

This is the voltage at the receiver input in the presence of interference. The fmt term il I this expression is the node 4 voltage without interference. en = 4. We can re-write G

(6-6) in terms of the relative interference strength K = and the unperturbed signal risetime t4,, = :

I ,

11

V4 - = - :::( t + M(sin(o(t- 01 t,) + I)) - sin(- or, + I))))

In a later section we will use this expression for the time-domain voltage at the receiver input in the presence of interference to derive the interference-induced delay.

At low frequencies, we consider just the extremes of (6-7). which reduces to

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6.3.2 Time domain derivation of node 4 voltage

In the previous section we derived an expression for the voltage at node 4. the input to the receiver. in the presence of capacitively coupled interference. We fmt calcu- lated the interference voltage in the frequency domain, then converted to the time domain and superposed with the interference-free signal. This followed the procedure outlined at the beginning of this chapter. For this simple case of capacitive coupling to a negligibly short transmission line with capacitive loading, the node 4 voltage can also be derived

directly in the time domain. With reference to Fig. 6-4 we have:

which is the same result as (6-6). This expression can be transformed into (6-7) in the

same manner as was used in the previous section. Note that although the above procedure is straightfonvard in this case, for more complicated coupling situations the procedure of the preceding section is more suitable.

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63.3 Induced delay at node 4

In the previous two sections we found the voltage at the receiver input (node 4 of Fig. 6-4) in the presence of capacitively coupled interference using two methods. In this section we use this result to determine the EMI-induced delay at node 4. m a t is, we solve (6-7) for the time t4 at which the node 4 voltage crosses the switching threshold, V,

This leads to the following implicit function describing t in terms of the unperturbed sig-

nal risetime t4n and the interference amplitude factor K, radian frequency a , and phase

@ -

In the low frequency case, this reduces to t4n - t4 - ~ K ~ ~ ~ c o s ( - at , + @) = 0, which has extremes at t4n - t4 * 14 t4 = 0. Thus for low frequencies

The voltage waveforms described by (6-9) and (6-1 1) are shown in Figs. 6-5 and

6-6, for 0.5 MHz and 5 MHz interference with t4, = 100 ns and r = 0.5. In these plots all

phases (in 20' increments) are shown for the complete expression of (6-9). but only the extremes are shown for the DC approximation of (6-11). These plots show that the DC approximation accurately predicts the maximum positive and negative delays at 0.5 MHz but fails to do so at 5 MHz.

Having calculated the voltage waveforms at the receiver input, we now proceed to

determine when these waveforms cross the switching threshold. The EMI-induced delay at node 4, At4. is found by solving (6-10) for t and then calculating At4 = t4 - t4n.

Next, we consider how the induced delay depends on frequency and interference magni- tude.

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Figure 6-5. Effect of 0.5 MHz intederence (various phases) on voltage at input to receiver, with K = 0.5. Inter- ference-free and DC approximation are also shown.

Figure 6-6. Effect of 5 MHz interference (various phases) on voltage at input to receiver, with K = 0.5. Interfer- ence-free and DC approximation are also shown.

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Figure 6-7 shows the maximum positive and negative induced delays at the receiver input as a function of interference frequency. as calculated using (6-10). In

Fig. 6-8, the effect of the interference magnitude K on the induced delay is shown at hvo frequencies, along with the DC approximation for delay given by (6-11). These theoreti- cal predictions of induced delay are consistent with the experimental observations made by Laurin in [a, namely that the positive delays are generally larger in magnitude than the negative delays, the positive delays are more frequency sensitive than the negative delay+ and the interference magnitude range over which the delay is proportional to the interfer- ence amplitude (i.e. K) increases with frequency.

- - - - Maximum p i l i v c delay Maximum negative delay

- - - _ ---1 0 2 4 6 8 10 12 14 16 18 20

Frequency W)

Figure 6-7. Effect of frequency on induced delay at the receiver input (At4). with t4, = 100 ns and K = 0.5.

-."" 0 0.1 0.2 0.3 0.4 05 0.6 0.7 0.8

hlI level (K)

Figure 6-8. Effect of interference amplitude K on induced delay at the receiver input (At4). with t4, = 100 ns.

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6.3.4 Induced delay at node 6

The delay induced at the receiver input, At4 = t4-t4,,. will not affect system operation unless the delay propagates to the output of the receiver (i.e. to node 6). The EMI-induced delay at node 6 depends on both the &lay at node 4, as found in Sec. 6.3.3. and the change in the propagation delay from node 4 to node 6, Atp46 = tp46 - tp46n. The extra propagation delay is caused by the EMI-induced change in the slew rate at node 4, as described in Sec. 6.2. For the experimental case considered by Laurin, we found in Sec. 6.2.1 that Cs, = 34 pF, I6 = 3.5 mA, and a =0.42. Additionally, we have (th- to) = 100 ns. and CL = 0 pF. Thus

and

Results for the EMI-induced delays at nodes 4 and 6 as a function of frequency for K = 0.5 are shown in Fig. 6-9. The delays at node 6 are larger than those at node 4; again,

this is consistent with the experimental results of Lawin.

Maximum N6 positive delay Maximum N6 negative delay Maximum N4 positive delay Maximum N4 negative delay - 100

e

Fi y r e 6-9. Predicted effect of frequency on induced delays at receiver input (At4) and receiver output (At6).

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6.4 Induced Delay Example: Inductive Coupling

In this section measurements of the induced delay due to inductive coupling to a simple CMOS circuit are compared with predictions. The measurement setup is shown in Fig. 6-10; the test equipment is identified in Table 6-1. The applicator is actually posi- tioned over the target track; in Fig. 6-10 it is shifted so as not to obscure the target track. The test board described in Ch. 4 and re-displayed in Fig. 6-11, originally used to diag- nose the /AS handover failure, is used again here with the 74HC367 buffers. The 75 i2

target track is 0.25 m long, which at vp = 2 x lo8 m/s corresponds to a propagation time of tp = 1.25 ns. The /EN signal is held low; that is. the driver is always enabled. Voltages are monitored at the receiver input, node 4, and the receiver output, node 6.

The key in performing these measurements is to display clearly the high-frequency

interference signal from the signal generator overlaid on the relatively low-frequency dig- ital signal from the function generator. Thus the signal generator and the function genera- tor must have a common timing reference. This is provided by the 10 MHz reference

output of the signal generator, which is used as the reference oscillator for the function generator. The function generator provides a 1 MHz synchronizing output which is used to trigger the o.xilloscope. Since the signal generator output is derived from the same ref- erence as the trigger, the interfering signal is clearly displayed on the oscilloscope pro- vided that its frequency is an integer multiple of 1 MHz Consequently we can see the

interference "move across" the logic transition as we change the phase of the interference (which is defined with respect to the time at which the logic transition crosses the switch- ing threshold at the position of the interference applicator).

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Figure 6-10. Measurement setup.

Table 6 1 Measurement EPuioment

Designation

HP54120B

Description

Digitizing oscilloscope mainframe

HP54124A

HPll2OA

HP33120A

Figure 611 . uduced delay test board.

- -

Four channel test set

500 MHz probe (+ power supply + 10:l divider)

Function Eenerator

HP8642B

EN1 525LA

Signal generator

50 dB, 25 W power amplifier, 1-500 MHz

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6-41 Static voltages

Before p r o c d i g with the induced delay measurement and prediction, we con- sider the static voltages at node 4 (the input to the receiver). That is, we measure and com- pare with theory the interference voltage at node 4 when the circuit is not switching. As was shown in Ch. 3, the static voltage affects the dynamic voltage for low values of n; thus it is important that we predict correctly the static voltages if we are to predict correctly the dynamic voltages and thus the induced delay. Figure 6-12 shows the ratio of the node 4 static voltage to the interfering voltage Vind for the driven logic states (high and low),

with the applicator 3.5 cm from the driver. The receiver is modeled as Ci = 5 pF in series with Rl = 10 R. and the driver as Ro = 30 R in parallel with Co = 13 pF and the 5 kR pull-up resistor (refer to Figs. 3-14 and 3-15 for the receiver and driver equivalent cir- cuits). The agreement between measurement and theory is within f 2 dB at most frequen- cies. Figure 6-13 shows the measured and predicted node 4 voltage with the driver in the high-impedance state (i.e. Ro + -); again, reasonable agreement is obtained. The static high impedance state is of interest here because the driver impedance during switching is very high; thus Fig. 6-13 shows the voltage that would be developed at node 4 if the driver switched very slowly.

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Figure 6-12. Measured and predicted static voltages at node 4: driver in logic high and low states.

Figure 6-13. Measured and predicted static voltage at node 4: driver in high impedance state.

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6.4.2 Measured and predicted waveforms at node 4

Having verified the static models, we now turn to dynamic analysis. The theory of Ch. 3 predicts interference to be superimposed on the interference-free logic transition. This interference is a function of frequency and applicator position along the target track Here we consider 50 MHz interference coupled using the inductive applicator 3.5 cm from the driver. The applicator is excited with 40 dBm available power. F ~ s t we predict the interference voltage waveforms and superimpose them on the measured interference-free logic transition. Then we present measurements of the transition with interference, and compare meuurement with prediction.

In order to predict the interference that will appear at node 4 (the receiver input),

we must first characterize the interference-free logic transition. ?he oscilloscope was used to capture this waveform, which shown in Fig. 6-14. Only the rising edge of the dig- ital signal is considered here. As indicated in this figure, switching effectively begins at to = 29.5 ns. and the switching threshold is reached at t . = 30.3 ns.

5 - 4 -

28.5 29 29.5 30 305 31 315 32 32.5 33 33.5 T i e (us)

Figure 6-14. Receiver input (node 4) waveform without interference.

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First we use the theory of Sec. 3.2 to predict the interfe~nce voltage at the receiver input (node 4). The interference at node 4 is calculated with induced voltage VM in 20' increments. The resulting time domain waveform (Re{& ejm'}) is shown in Fig. 6-15, where t c 29.5 ns corresponds to the static case. 29.5 ns c t c 32 ns to n = 0, and t > 32 ns ton = 1. We then superpose this predicted interference signal with the interference-free transition of Fig. 6-14. The result, shown in Fig. 6-16, is the predicted time-domain wave- form at node 4 in the time surrounding the logic transition.

-0.5 1 I 28.5 29 29.5 30 305 31 31.5 32 325 33 33.5

T i e (IS)

Figure 6-15. Predicted interference voltage at receiver input, for various phases of interference at 50 MHz, -10 dBm.

I 285 29 295 30 30.5 31 31.5 32 325 33 33.5

Tie (ns)

Figure 6-16 Predicted voltage at receiver (interference superimposed on unperturbed voltage).

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The measured waveforms at the receiver input, for 20' incremer.ts in phase of the interference signal, are shown in Fig. 6-17. In Fig. 6-18 the interference-free signal of Fig. 6-14 is subtracted from the measured waveforms with interference. This measure- ment compares well with the prediction of Fig. 6-15; in particular, the change in wave- forms at r = to = 29.5 ns, when the effect of switching fmt reaches node 4, is apparent in both. In Fig. 6-18 the dashed lines indicate to and t4,,, while the solid vertical line of Fig. 6-18 corresponds to one round-trip propagation delay after t,,.

Figure 6-17. Measured voltages at receiver input, includ- ing interference at various phases.

Figure 6-18. Measured interference-only voltages at receiver input.

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By comparing the shapes of the measured and predicted voltage waveforms shown on the previous two pages we can state that the two sets of curves are similar. Here we quantify the comparison by considering the induced delay. Recall that the EMI-induced delay is the time between the interference-free threshold crossing, t4,. and the with-inter- ference threshold crossing, t+ Here we take the threshold to be V, = 2.5 V. The mea- sured and predicted EMI-induced delays at node 4 are shown in Fig. 6-19. The maximum positive and negative delays and the phase dependence of the delay are thus shown to be predicted well by the theory.

Figure 6-19. Measured and predicted delay at the receiver input, At4. VS. the phase of the 50 MHz interference.

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6.4.3 M e w e d and predicted waveforms at output

In the previous section we compared measured and predicted voltage waveforms and induced delays at node 4, the receiver input Next, we move to the receiver output, node 6 of Fig. 6-11. Recall that the induced delay at the circuit output (node 6) is of more importance than that at node 4, since we are unconcerned about delays internal to the cir- cuit (node 4) as long as they do not affect the timing at the output of the circuit (node 6).

Before we predict the interference waveforms at node 6, we must determine sev- eral properties of the circuit The interference-free waveform at the receiver output is shown in Fig. 6-20. Comparing Figs. 6-14 and 6-20 we find that the interference-free propagation delay from node 4 to node 6 is 4.5 ns. The output line (from the output of the

receiver to the voltage probe) is about 10 cm long, contributing 0.5 ns to the delay. This leaves a 4.0 ns delay through the non-inverting buffer, which is constructed from two inverters. The fust inverter, which is the one we are concerned with here, drives a rela- tively small load (just the second inverter), while the second inverter drives the off-chip

load. The fust inverter will thus contribute a smaller fraction of the 4 ns buffer delay than the second, given equal drive strengths. We assign one quarter of the buffer delay to the input inverter.; thus tm = 1 ns. Also, from Fig. 6-14 we have t - to = 0.8 ns. Finally. we use the slew-rate dependence factor derived from [59], a = 0.8 (see Sec. 6.2). Know- ing these parameters, we now proceed to calculate the expected induced delay at node 6.

T i (ns)

Figure 6-20. Interference-free voltage at receiver output

* ~ b d predicted output waveforms are relatively invariant to the choice oft, For example. if we split the lMal propagation delay equally between the t& invaers, ie. t+ = 2 ns. &;-resulting maximum delay at node 6 would be 0.13 ns raIher than the 0.15 ns corresponding tot+ = 1 ns.

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The change in propagation delay from node 4 to node 6 due to the interference is

tp46 = ,/(tp46n)2 + a2(2(t4, - t0)At4 + ( ~ t ~ ) ~ )

Using At4 from Fig. 6-19, the total interference-induced delay at node 6.

At, = At4 + (tP4,, - t,,,) . can be predicted. The measured waveforms at node 6 are shown in Fig. 6-21. In Fig. 6-22. the corre-

sponding measured delay is compared with the predicted delay. As expected, the delay at node 6 is slightly greater than that at node 5, due to the slew-rate iilduced change in pmpa- gation delay. Again, the theory correctly predicts the maximum and minimum induced delays and the dependence of delay on the phase of the interference.

6

Figure 6-21. Measured receiver output waveforms with 50 MHz interference at various phases.

- (deg.)

figure 6-22. Measured and predicted delay at receiver out- put vs. phase of 50 MHz interference.

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6.5 Induced Delay: HSPICE Comparison

HSPICE is a widely-used circuit simulator. Here the predicted delays using the theory of Sec. 6.2 are compared with HSPICE simulation results. The circuit corhists of a 0.25 m, 2x lo8 m/s transmission line linking the driver and receiver discussed in Sec. 3.3. The interference is modeled as an ideal voltage source located next to the driver.

The delay at each frequency was calculated and simulated for interference with 20' phase increments; the maximum absolute delay at each interference frequency is shown in Fig. 6-23. The discrepancy between the theory and HSPICE at 620 MHz may be due to a shift in the resonant frequency andlor higher losses due to changing driver and receiver impedances. Note that the theory correctly predicts the larger gap between node

4 and node 5 delays due to the filtering effect at the input of the receiver. This comparison confirms that the simple theory developed in this chapter is use-

ful for predicting interference-induced delays. The theory developed here runs approxi-

mately 100 times faster than the HSPICE simulations.

500 1 . . . . . . . . . . . . . . . . Pred 8 4 . - Pred 85 '., x x Meas 8 4 -

0 I I t I t I I 8

0 100 200 300 400 500 600 700 800 900 1000 Freauencv (MHz)

Figure 6-23. Maximum induced delay: prediction com- pared with measurement (HSPICE simulation).

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6.6 Conclusions

Previous work by Laurin [6] showed that interference coupled to a transmission line of a digital circuit can delay (or advance) the digital signal In this chapter (and Ch. 3) this theory has been extended to include the frequency dependence of the induced-delay phenomenon. Also, the effect of the transmission line itself is considered (previous work neglected possible resonance effects, assuming that the transmission line was short with respect to the interference wavelength). The theory developed here has been validated through comparison with previously published measurements (Sec. 6.3). with measure- ments performed as part of this work (Sec. 6.4). and with a common circuit simulator (Sec. 6.5).

In addition to the validation of the theory, the following observations were made. For the case of capacitive coupling to a short track, the low-frequency approximation overestimates the EMI-induced delay when the interference period approaches the digital signal risetime (Fig. 6-8). Track resonances can cause the EMI-induced delay to double the low-frequency delay at some frequencies and to reduce to no delay at other frequencies (Fig. 6-23).

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Chapter 7

CONCLUSIONS

This work extends the notion of electromagnetic interference stress testing beyond that previously reported. In this chapter the key contributions of this research are summa- rized. First, results relating to the objectives outlined in Sec. 1.2 are presented. This is followed by a discussion of the novel findings that make up the contribution of this thesis.

Results based on research objectives. The research objectives stated in Sec. 1.2 were addressed primarily in Ch. 2, which discusses the EM1 stress testing apparatus, but also throughout the rest of the thesis. The following results were found:

a ) What is the effect of the EMIfiequency on the susceptibility map? One of the main contributions of this work is the analysis of the frequency dependence of

the susceptibiility map. It has been postulated, and then proven experimentally, that the chief mechanism affecting the frequency dependence is track resonance.

b) How does modulating the EMI affect the susceptibility map? A brief test of the effect of amplitude modulation yielded no effect beyond that expected

due to changes in peak signal level (Sec. 2.1).

c) How does synchronizing the EM to the board clock affect the susceptibility mop? The induced delay studied in Ch. 6 depends strongly on the phase of the interference with respect to the digital signal transition.

d) How does the software running on the EUT affect the susceptibility map? The diagnostic test used to monitor EUT failures is an integral part of a susceptibility scan

(Sec. 2.4.2). The EUT may or may not fail depending on the particular diagnostic.

e) How fine should the scan resolution be? The scan resolution must be fine enough so that a single track can be targeted (Sec. 2.3.1).

f) Is the EMI applicator optimlly designedfor coupling the interference to the board? Three applicators were designed, and the best of these was adopted (Sec. 2.3).

g) How repeatable is the susceptibility mop? The failure threshold at any point on a susceptibility map can be found to - f 1 dB.

h) Can the EMI be coupled to tracks on each side (solder ond component) of the EUT? Coupling to the solder side of the EUT is easier to achieve since the packages on the com- ponent side have vaiying heights and thus would require vertical positioning of the appli- cator.

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i) What types of failures occur &ring a susceptibiliq scan? TWO types of failures were observed in susceptibility scans on the EUT, one due to a high-inpdance line with a pull-up resistor and the other due to a weak component A thirC failure type, induced delay, was also studied.

j) HOW can a boardfailure be traced to a particular component? The component causing a board failure is found by first noting which track is the target when the failure occurs. AU components attached to this track are suspect By consider- ing the diagnostic test results, the frequency, and the applicator position at failure, suspects may be ruled out and a "culprit" identified.

Contributions. In this work a new understanding has been developed of the parameters that affect the susceptibiity of a printed circuit board. It has been established that the frequency dependence of EM1 susceptibility is dominated by transmission line

resonances, and that these resonances depend on track lengths and load impedances. The theory predicting the frequency and applicator position effects on susceptibility, devel-

oped in Ch. 3, has been successfully validated by comparison with measurements. This theory has been used to predict where a failing component is located (Sec. 5.3.3).

During EM1 stress testing experiments, a new phenomenon was discovered, in which a tri-state driver in the high-impedance state fails due to EM1 rectification (Ch. 4). This failure is highly dependent on the resistor used to pull the high-impedance line up to a valid logic level (a larger resistor results in a more susceptible circuit). Rectification has long been recognized as a cause of failure [lo], but this work is new in that it demonstrates the heightened susceptibility of a tri-stated driver with a large pull-up resistor.

A weak chip was discovered that functions correctly under normal operating con- ditions but fails under EM1 saess (Ch. 5). This is a key revelation because it shows that EM1 stress testing works, a point that had previously only been hypothesized 141. The sus- ceptibility of the weak chip has been observed to be temperature-dependent The temper- ature rise due to power dissipation in the weak chip and sumunding components.

primarily occurring in the minutes following initial power-up of the EUT, leads to increased susceptibility of the weak chip.

Finally, the theory of EMI-induced delay in digital circuits has been expanded to include both high-frequency effects and transmission line effects (Ch. 6). Thii theory has

been validated experimentally. The low-frequency approximation of Laurin over-esti- mates the induced delay at higher frequencies (where the interference period is of the same order as the digital signal risetime). On the other hand, transmission line resonances can significantly increase the EMI-induced delay over that expected with no transmission line.

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Appendix A

MUTUAL COUPLING BETWEEN TWO INFINITELY LONG, INFINITESIMAL FILAMENTS OVER A GROUND PLANE

The per-unit-length coupling between two infinitely long, infinitesimal filaments (representing the applicator and the target track) over a gmund plane is derived as follows. The geometry of the problem is shown below, where (a) shows the physical arrangement and (b) shows the equivalent problem with the ground plane removed and replaced by

The mutual coupling can be found by fxst calculating the magnetic field due to the applicator and its image, then integrating this field over the loop fonned by the target tnck

and the ground plane to find the induced voltage. Here, we simplify the algebra by

exploiting the symmetry of the problem. We note that:

1) The induced voltage in the loop formed by the target hack and its image is twice the induced voltage in the loop formed by the target track and the ground plane.

2) The magnetic fields due i t h e applicator don; (in free space) &e half those due to the applicator and its image, in regions symmetrical about the image plane.

Thus we calculate the induced voltage by integrating the magnetic field due to the applica-

tor alone (in free space) over the loop formed by the target track and its image. Fist, we find the magnetic field due to an infinitesimal, infinitely long x-directed

cumnt element in free space. The applicator current is assumed to flow in the negative x

d i i t i o n (i.e. into the page), while the applicator image current flows out of the page. The

origin of our co-ordinate system is at the applicator.

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Nexc we find the induced voltage due to this magnetic field; that is, we fmd the magnetic

field that links the loop formed by the target hack and its image. Note that this loop lies in the x-z plane; we use a length of a in the x-direction. and integrate the y-directed H-field in the z-direction.

Recognizing that y = d in the plane of the target track loop, we obtain the following

expression for Va, the voltage induced in the target track due to the applicator current

The mutual inductance per unit length is found by noting that from circuit theory,

Vind = - j aMI

so that the mutual inductance is

Finally, the mutual inductance per unit length is

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Appendix B

MICROSTRIP TRANSMISSION LINE PROPERTIES

The formulas used in this thesis to determine the characteristic impedance Zo, propagation velocity vp, and attenuation coefficient a of a microstrip transmission line were taken from Pozar 1571, and are reproduced here. The microstrip diekctic has thick- ness d, relative permittivity E, and loss tangent tan@); the conductor has width W and conductivity a. The properties of free space are approximately c = 3 x lo8 mk,

10-9 E~ = 3 6 ~ Flm, and po = 4 r X lo-' Wm. Note that the attenuation constants depend on the rad~an frequency a.

60 8d W -In(-+ ) W ,& W 4d for - $1 d

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Appendix C

DERIVATION OF DYNAMIC VOLTAGES

C-1. INDUCTIVE COUPLING The equivalent aansmission line problem is shown below, where the impedance at

node 1 switches at t = 0. Here we focus on the node 4 voltage; the same procedure can be used to fmd the voltages at the other nodes.

Before t = 0, all voltages are static; i.e. V, = Vlo and I$ = Va. and

When the switch closes at t = 0, a wave is launched from node 1 and propagates down the

transmission h e in time tp. Following the flowchwt of Fig. 3-3, and noting the time for the impedance change at node 1 a progress down the transmission line, we find that

where n is the number of round-trip propagation delays from the time at which the switch

108

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closing effect is fmt felt at node 4, so that n = floor -9 .

Thus the voltage at node 4 for t 2 tp is

which is the result given in (3-1 1).

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C-2. CAPACITIVE COUPLING Next we derive the dynamic node 4 voltage for the case of capacitive coupling,

using the equivalent circuit shown below.

f \

The corresponding flowchart with IindZo = V i , is:

Before t = 0,211 voltages ate static; i.e. V 1 = V l 0 and & = V&, , and

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so that the resulting voltage at node 4 for t 2 t,, is

which is the result given in (3-15).

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