Electrical Power and Energy Systems 63 (2014) 446–454

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Electrical Power and Energy Systems

journal homepage: www.elsevier .com/locate / i jepes

A novel low-ripple interleaved buck–boost converter with highefficiency and low oscillation for fuel-cell applications

http://dx.doi.org/10.1016/j.ijepes.2014.06.0200142-0615/� 2014 Elsevier Ltd. All rights reserved.

⇑ Corresponding author. Tel.: +98 21 88462408; fax: +98 21 88462066.E-mail addresses: vahidsamavatian@ee.kntu.ac.ir, vahidsamavatian_90@yahoo.

com (V. Samavatian), radan@kntu.ac.ir (A. Radan).

Vahid Samavatian ⇑, Ahmad RadanElectrical and Computer Engineering Faculty, K.N. Toosi University of Technology, Seyedkhandan Bridge, 1431714191 Tehran, Iran

a r t i c l e i n f o

Article history:Received 21 January 2014Received in revised form 31 May 2014Accepted 3 June 2014

Keywords:Low-ripple I/O currentsInterleaved techniqueNon-inverting buck–boost converterHigh efficiencyFuel cell

a b s t r a c t

Efficiency and dynamics of DC–DC converters play a major role in proficiency of renewable energy exploi-tation. This paper presents a novel DC–DC interleaved buck–boost converter for fuel-cell applications.While keeping the same step-up/step-down voltage transfer ratio, the proposed converter exhibitsnon-pulsating I/O currents using interleave technique. A damping network is also added to improvethe inner dynamics of converter. Besides the steady state operation based on state space averaging(SSA) method, design considerations of converter are thoroughly elaborated. MATLAB/SIMULINK environ-ment is used for simulating the steady state operation of proposed converter, and the experimentalresults are presented, to verify the theoretical expected merits of the converter including high efficiency,non-pulsating I/O currents and low voltage oscillation. Prototype setup of 360 W and 36 V output voltagefor a fuel cell with a brand of ‘‘FCgen 1020ACS’’ Ballard Power Systems, Inc was implemented. Experimen-tal results including efficiency and time domain responses in the steady state show impressive benefits ofthe proposed converter.

� 2014 Elsevier Ltd. All rights reserved.

Introduction

With ever-increasing use of DC–DC power converters in manyapplications such as battery charging, fuel cell systems, power fac-tor correction (PFC), hybrid electric vehicles, communicationpower supply, maximum power point tracking (MPPT) of photovoltaic system (PVs) and for other renewable sources’ maximumenergy extraction, a considerable number of studies have beenconducted over these kinds of converters. On the whole DC–DCconverters fall into three categories; buck, boost and buck–boost.A buck–boost converter is required when the output voltage iswithin the input voltage range [1–12].

Although there are many single-active-switch step-up/step-down DC–DC converters such as Sepic, Cuk, and conventionalinverting buck–boost and flyback converters, the non-invertingbuck–boost one constructed by combining a boost and a buck circuitin cascade with two independently controllable switches is a popu-lar choice for such applications requiring bidirectional conversioncapability, high efficiency and low component stresses [2–4].

In addition to the above-mentioned step-up/step-down DC–DCconverters topologies, it is possible to combine a buck converter

with a boost one in cascade leading to a single inductor high per-formance buck–boost converter for low voltage applications [5–7].

Although other topologies, capable of working through highvoltage applications, are reported in [8,9], their controlling systemsare completely involved. Another topology is KY buck–boost con-verter with improving controlling system via eliminating right-half-plane (RHP) zero in continuous conduction mode (CCM)[10],but it poses a major problem in four power switches whichresults in increasing the cost of the device. In order to mitigate thisproblem, new topology with two reduced active switches andaforementioned advantage is reported in [11].

Most of the DC–DC converters mentioned earlier have thedrawback of pulsating input/output (I/O) currents resulting in ahigh noise level and complicated controlling system as well as cur-rent limitations. In many applications, especially in hybrid electricvehicles, power factor correction and fuel cell, low-ripple current ispreferred [13–15]. For subsiding this problem the two-switch tri-state buck–boost is proposed [16] and with regard to capabilityof using large inductance in pseudo-continuous conduction mode(PCCM) [17,18], lower-ripple I/O currents can be achieved. Anotherpossible solution for this problem is to use the interleaved tech-nique. Using this technique further benefits like harmonic cancel-lation, better efficiency, component stresses reduction, betterthermal performance, and high power density can be easilyobtained [13,15,19–22]. The concept of interleaving is not new

Nomenclature

C1, C2, Cd input, interface and output capacitorD12 steady state duty cycle of boost stageD34 steady state duty cycle of buck staged12(t) duty cycle of boost staged34(t) duty cycle of buck stageiL1–iL4 inductor 1 through inductor 4 currentM(u) converter voltage transfer ratioM(D12, D34) converter voltage transfer ratioPRd power dissipation in damping network resistor

S1–S4 Q1–Q4 Signal activationsTs switching periodu unified controlling variablevC1, iC1 capacitor 1 voltage and currentvC2, iC2 capacitor 2 voltage and currentvCd, iCd damping network capacitor voltage and currentvg, ig input voltage and currentvL1–vL4 inductor 1 through inductor 4 voltagevout, iout output voltage and current

V. Samavatian, A. Radan / Electrical Power and Energy Systems 63 (2014) 446–454 447

and covers a wide area of applications [22]. In [13], the 16-phaseinterleaved bidirectional boost converter for hybrid energy storagesystem (HESS) has solved I/O currents high ripple but this topologycan just operate in the boost mode and it is not generalized in both

Fig. 1. Schematic circuit diagra

Fig. 2. Operating modes of proposed conv

buck and boost operating modes [15]. Proposes an interleaved noninverting buck–boost converter with a low-output current ripple,but in this topology counteracting the input voltage variation inwide range is not completely achieved. In [20], the double-switch

m of proposed converter.

erter: (a) boost mode; (b) buck mode.

448 V. Samavatian, A. Radan / Electrical Power and Energy Systems 63 (2014) 446–454

buck–boost converter is proposed which can reduce the induc-tance, raise the conversion efficiency and have simple controlstrategy, but component stresses have been remained highthrough this topology. Another solution reported in the study ofthis paper is to utilize a non-inverting interleaved buck–boost con-verter with a damping network, placed between a two-phase inter-leaved boost part and a two-phase interleaved buck part. In thisway the drawbacks of high I/O currents ripple, low converter effi-ciency and voltage oscillation have been improved by using inter-leaved technique, reducing component stresses as result ofcombining boost stage and buck stage in cascade connection,which has also less component stresses as a result, and employingdamping network respectively. Through increasing the number ofinterleaved phase in boost and buck stages, the proposed convertercan be easily used as a modular converter which is suitable fortransferring high power density in applications such as HESS andother individual storage systems requiring the capability ofincreasing power density.

The purpose of this paper is to analyze a cascaded combinationof interleaved boost and buck converters connected through adamping network. After discussing the steady state operationand state equations of the proposed converter in the following sec-tion based on the depicted key waveforms, circuit design and itsimplementation as an application of fuel cell voltage regulationhave been presented in Section 3. Section 4 focuses on the experi-mental results and the last section presents a conclusion for thisstudy.

Fig. 3. Key waveforms of proposed converter shown in Fig. 1 for Vout = 36 V, (a) currentsbuck mode with Vg = 43 V (D12 = 0).

Steady state operation and analysis of the proposed converter

The proposed converter is shown in Fig. 1. This converter canoperate both in boost and buck modes as shown in Fig. 2(a andb). The boost mode is achieved when the switches 3 and 4 (Q3

and Q4) turn on permanently and switches 1 and 2 (Q1 and Q1)operate in PWM. Similarly, in buck mode Q1 and Q2 turn off perma-nently and Q3 and Q4 operate in PWM. The steady state operationwaveforms of this converter for both modes of boost and buck areillustrated in Fig. 3(a) and (b) respectively. The last traces in thesetwo figures, namely S1 to S4, are allocated to logic activation signalsof Q3 to Q4. The PWM activation signals of Q1 and Q2 are similar toeach other with a delay of T3/2 for catering the interleaved patternand their duty cycles are considered as d12(t). The same is true forQ3 and Q4 activation signals with considering d34(t) as their dutycycles. The duty cycle of switches is adjusted in such a way thatoutput voltage is regulated around a desired value (here is 36 V)in both operational modes. Including a capacitor and resistor con-necting in series, damping network plays the role of decaying inputvoltage oscillation in buck mode where Q1 and Q2 are permanentlyoff.

The two main methods used for obtaining the differential equa-tions describing the dynamic behavior of interleaved convertersare state space averaging (SSA) methods [3] and signal flow graph(SFG) [23]. In this paper state space averaging method is preferreddue to simplicity.

and voltages in boost mode with Vg = 26 V (D24 = 1), and (b) currents and voltages in

V. Samavatian, A. Radan / Electrical Power and Energy Systems 63 (2014) 446–454 449

Assuming the operation of continuous conduction mode (CCM)and a switching frequency much higher than the converter naturalfrequencies, state space averaging method [3] can be applied toexplore the converter model considering the small-ripple approxi-mation and the principles of inductor volt-second balance andcapacitor charge balance.

For obtaining the modeling equations for both modes of opera-tion simultaneously, the switching pattern of Fig. 4 is considered.Based on this figure, each period introduces 6 time intervals and6 corresponding circuit diagrams illustrated in Fig. 5. Time intervalnumbering and portioning are listed in Table 1. As the intervals 2and 5 have the same time portions and the same switching state,with regard to Figs. 4 and 5, the converter can be analyzed onlyin 5 states as follows:

Interval 1: [t0 � t1], Fig. 5(a). In this time interval Q1, Q3 and Q4

are in conducting mode causing inductor 1to start savingenergy and concurrently inductor 2 to transfer its stored energyto output load and both output inductors via D2. ConsideringFig. 5(a), the differential equations describing the capacitors’voltages and inductors’ currents can be given as follows:

mL1ðtÞ ¼ L1diL1dt ¼ mgðtÞ

mL2ðtÞ ¼ L2diL2dt ¼ mgðtÞ � mc1ðtÞ

mL3ðtÞ ¼ L3diL3dt ¼ mL4ðtÞ ¼ L4

diL4dt ¼ mc1ðtÞ � moutðtÞ

ic1ðtÞ ¼ C1dmC1

dt ¼ iL2ðtÞ � ðiL3ðtÞ þ iL4ðtÞÞ � mC1ðtÞ�mCdðtÞRd

ic2ðtÞ ¼ C2dmC2

dt ¼ iL3ðtÞ þ iL4ðtÞ � moutðtÞR

icdðtÞ ¼ Cddmcd

dt ¼mC1ðtÞ�mcdðtÞ

Rd

8>>>>>>>>>>><>>>>>>>>>>>:

ð1Þ

Interval 2 and 5: [t1 � t2 and t4 � t5], Fig. 5(b). In this time inter-val Q3 and Q4 are in conducting mode while Q1 and Q2 turn off.Therefore the energy stored in inductors 1 and 2 starts transfer-ring to inductors 3 and 4 via D1 and D2. Similar to time interval1 a set of differential equations can be found for describing ofthe capacitors’ voltages and inductors’ currents in this timeinterval based on Fig. 5(b). One can find these equations inAppendix 1.Interval 3: [t2 � t3], Fig. 5(c). In this time interval Q3 is in con-ducting mode while Q1, Q2 and Q4 are off. Energy transfer in thisinterval is completely similar to previous interval except thatthe energy stored in both input inductor is transferred to theinductor 3 only.Interval 4: [t3 � t4], Fig. 5(d). In this time interval Q2, Q3 and Q4

are in conducting mode while Q1 is off. Energy transfer in thisinterval is as also similar to that of interval 1 except that thefunctions of inductor 1 and 2 replace each other.

Fig. 4. Switching pattern of converters’ MOSFETs.

Fig. 5. Operating states. (a) Circuit diagram in interval 1, (b) circuit diagram ininterval 2, 5, (c) circuit diagram in interval 3, (d) circuit diagram in interval 4, and(e) circuit diagram in interval 6.

Fig. 6. Voltage conversion ratio of the proposed buck–boost converter.

Table 2Required expressions for evaluating parameters’ values.

Parameter Expressions

L1, L2 Vg ðVout�Vg ÞDiL1or2Vout

Ts

L3, L4 Vout ðVout�Vg ÞDiL3or4Vg

Ts

C1 ðVout�Vg ÞDmC1R Ts

C2 Vout ðVout�Vg ÞDmC2 RVg

Ts

Table 1Required expressions for evaluating parameters’ values.

Interval number Time interval Time portion

1 t0 � t1 d12(t)TS

2 t1 � t2 (d34(t) � d12(t) � 0.5)Ts

3 t2 � t3 (1 � d34(t))Ts

4 t3 � t4 d12(t)Ts

5 t4 � t5 (d34 � d12(t) � 0.5)Ts

6 t5 � t6 (1 � d34(t))Ts

450 V. Samavatian, A. Radan / Electrical Power and Energy Systems 63 (2014) 446–454

Interval 6: [t5 � t6], Fig. 5(e). In this time interval Q4 is in con-ducting mode while Q1, Q2 and Q3 are off. Therefore the energystored in inductor 1 and 2 is transferred to the output capacitorand inductor 4.

Using the differential equations in all time intervals and apply-ing averaging technique [3] on these equations over one switchingperiod, the following set of differential equations are given:

L1diL1ðtÞ

dt

D ETs

¼ L2diL2ðtÞ

dt

D ETs

¼ VgðtÞ � VC1ðtÞð1� d12ðtÞÞ

L3diL3ðtÞ

dt

D ETs

¼ L4diL4ðtÞ

dt

D ETs

¼ �VoutðtÞ þ VC1ðtÞd34ðtÞ

C1dVC1ðtÞÞ

dt

D ETs

¼ � VC1ðtÞ�VcdðtÞRd

þ ðiL1ðtÞ þ iL2ðtÞÞð1� d12ðtÞÞ

�ðiL3ðtÞ þ iL4ðtÞÞd34ðtÞC2

dVoutðtÞdt

D ETs

¼ ðiL3ðtÞ þ iL4ðtÞÞ � VoutR

CddVcdðtÞ

dt

D ETS

¼ VC1ðtÞ�VcdðtÞRd

8>>>>>>>>>>>>>>><>>>>>>>>>>>>>>>:

ð2Þ

where d12 and d34 are the duty ratio of the switches Q1, Q2 andrespectively. For obtaining the steady state inductor currents andcapacitor voltages, the steady state operating value of duty ratios,D12 and D34, and input voltage, Vg, will be used. By applying theprinciples of inductor volt-second and capacitor charge balance,another set of expressions describing the steady state operationcan be derived as follows:

Ig ¼ IL1 þ IL2 ¼ D341�D12

VoutR

Iout ¼ IL3 þ IL4 ¼ VoutR

VC1 ¼ Vg

1�D12¼ Vout

D34

VCd ¼ 0Vout ¼ D34VCI ¼ D34

1�D12Vg

8>>>>>>><>>>>>>>:

ð3Þ

The last expression of Eq. (3) yields the voltage transfer ratio of con-verter M (D1, D2) as follows:

MðD12;D34Þ ¼Vout

Vg¼ D34

1� D12ð4Þ

The converter operation in boost and buck modes is determined byfollowing conditions.

Boost mode : fD34 ¼ 1 and 0 < D12 < 1gBuck mode : fD12 ¼ 0 and 0 < D34 < 1g

ð5Þ

For making the transition between two modes smooth, the voltagetransfer ratio M (D12, D34) should be written in terms of only onecontrol variable [4,7]. For establishing a meaningful relationbetween D12 and D34, the variable u is defined:

Assuming

u ¼ D12 þ D34 ð6Þ

Boost mode : 1 < u < 2Buck mode : 0 < u < 1

ð7Þ

The new voltage conversion ratio can be written as follows.

MðuÞ ¼ minð1;uÞ1�maxð0;u� 1Þ ð8Þ

Using above equation as voltage conversion ratio a smooth transi-tion can be easily established. This conversion ratio is depicted inFig. 6.

It is noted that small signal modeling and dynamic analysishave been completely studied in [24]. Therefore readers wouldbe referred to [24] for more details in such analyses.

Circuit design

In this section, some design considerations related to the selec-tion of proposed converter’s components are addressed. As it men-tioned earlier, need of low ripple I/O currents is key issue of thisstudy and accordingly inductors are selected so that this require-ment has been met. The inductors values can be selected such thata desired current ripple (DiL) is obtained. Similarly, desired voltageripple (DmC) can be achieved through selecting the capacitors val-ues properly.

The appropriate capacitors and inductors values are obtainedusing the equations describing behavior of inductors voltagesand capacitors currents in time intervals. Since the slope of theinductor current and capacitor voltage during one of each timeinterval is specified as well as the length of that time interval,the ripple magnitude of both current and voltage can be evaluated.Therefore expressions required for calculating the values of capac-itors and inductors are given for both modes of operation are listedin Table 2.

Converter system with higher orders (more than two) canencounter some internal oscillations which have to be decayedusing some methods described in details in [25], but here a damp-ing network has been employed to mitigate this behavior. Thisdamping network consists of a capacitor and a resistor connectingin series for subsiding input voltage large variations.

Although the design procedure of damping network parametersis thoroughly elaborated in [24], but here a brief explanation hasbeen presented. Regarding control-to-output transfer function ofthis proposed converter in buck mode operation (9), the constraintof damping network parameters calculation has been identified[24]. One can find numerator coefficients in Appendix 2.

V. Samavatian, A. Radan / Electrical Power and Energy Systems 63 (2014) 446–454 451

Gmod34ðsÞ ¼m̂outðsÞd̂34ðsÞ

¼ ad343 s3 þ ad34

2 s2 þ ad341 sþ ad34

0

b5s5 þ b4s4 þ b3s3 þ b2s2 þ b1sþ b0ð9Þ

For improving internal dynamic, all the zeros in control-to-outputtransfer function should be Left-Half-Plane (LHP) zeros. Accord-ingly, applying Routh-Hurwitz stability criterion to the transferfunction numerator, following set of equation would be derived.

ad340 ¼ RVout

D34ð1� D12Þ2 � 0

ad341 ¼ Vout

D34ðCdRRdD2

12 � 2CdRRdD12 � L12D234 þ CdRRdÞ � 0

ad342 ¼ L12Vout

D34ðCdRþ C1R� D2

34CdRdÞ � 0

ad343 ¼ R2RdCdC1L12Vout

D34� 0

ad342 ad34

1 � ad340 ad34

3 � 0

8>>>>>>>>><>>>>>>>>>:

ð10Þ

Regarding aforementioned conditions and using nonlinear optimi-zation (Nelder–Mead method), following damping network param-eters constraints can be expressed.

Rd > 0:65ffiffiffiffiffiL12C1

qCd > 8C1

(ð11Þ

The damping resistor dissipation power is evaluated by the follow-ing expression assuming that mcd has some ripples in form of trian-gular waveforms [4].

PRd ¼Dm2

C1

12Rð12Þ

Fig. 7. Proposed converter prototype, (a) power stage, (b) controller stage, and (c)two isolated voltage sources for driving buck MOSFETs.

Experimental results

The proposed converter is designed as a voltage regulation sys-tem so that its output voltage is adjusted around 36 V when itsinput voltage range varies from 26 to 43 V. The maximum outputpower is limited to 360 W corresponding to a load resistance equalto 3.6 Ohm. Using (4) and above data, it can be easily seen that theduty cycles are limited within the ranges: 0 < D12 < 0.2777 and0.837 < D34 < 1. The switching frequency is around 50 kHz andthe inductors’ current ripple and capacitors’ voltage ripple are lim-ited to 1 A and 0.1 V respectively.

The proposed converter has been designed as a fuel cell voltageregulation. The application requirements have been met so thatoutput voltage of fuel cell, with brand of ‘‘FCgen 1020ACS’’BallardPower Systems, Inc, is fixed around 36 for charging a battery bank.Fuel cell input voltage range varies from 26 to 43 V. Using (4), theexpressions listed in Table 2 and the ripples specified earlier, thelist of components and their value are given in Table 3. It is worthnothing here that for inductors the cores of Xinlli CORE Corpora-tion and the calculation method of [3] have been selected.

Fig. 7 shows the top view of prototype in three stages; (a) thepower stage including MOSFETs, IRF840b, and SHOTTKY diodes,MBR20100 and other main components denoted on figure, (b)the controller stage with a micro controller ATMEGA16L, MOSFET

Table 3Components for proposed converter.

Components Descriptions Types/values

Q1, Q2,Q3, Q4 Power MOSFET IRF840bD1, D2,D3, D4 SCHOTTKY diodes MBR20100L1, L2 Inductor 80 lH, 5 AL3, L4 Inductor 100 lH, 5 AC1 Capacitor 47 lF, 100 VC2 Capacitor 68 lF, 100 VCd Capacitor 470 lF, 100 VRd Resistor 1 ohm, 1 W

Fig. 8. Activation signals, (a) boost mode, and (b) buck mode.

Table 4Current ripple comparison.

Buck–boost converter Maximum input currentripple percentages (%)

Proposed converter 5.2Proposed converter in [4] 20Proposed converter in [11] 13Proposed converter in [14] 30Proposed converter in [16] 30

Fig. 10. Output current and output inductors’ current ripple in buck mode (a)Vg = 43 V, and (b) Vg = 40 V.

Fig. 9. Input current and input inductors’ current ripple in boost mode, (a)Vg = 26 V, and (b) Vg = 30 V.

Fig. 11. Capacitors voltage ripples in boost mode, (a) Vg = 26 V, and (b) Vg = 30 V.

452 V. Samavatian, A. Radan / Electrical Power and Energy Systems 63 (2014) 446–454

driver ICs, ICL7667 and two fast optocouplers, 6N137 and (c) theisolated voltage supplies. This section is organized in such a way

to present the experimental waveform of steady state operationin both modes by applying input voltage equal to 26 V and 30 Vin boost mode and 40 V and 43 V in buck mode under the full loadconditions.

The activation signals are depicted in Fig. 8(a) for boost modewhere D34 = 1 and D12 are operating in PWM and in Fig. 8(b) forbuck mode where D12 = 0 and D34 are operating in PWM.As it canbe seen from this figure, having a delay of Ts/2 guarantees the ben-efits of interleaving technique.

As it mentioned earlier, steady state experimental results havebeen illustrated in four various input voltages to verify the steadystate operation of proposed converter in the wide range of inputvoltage. Figs. 9 and 10 illustrate the overall input current andinductor currents ripples in boost and buck operation moderespectively. As depicted from these figures, the maximum rippleof inductor currents is limited to 1.05 A and it is about 0.52 A(%5.2) for input currents. These figures show that the ripples ofboth inductors are minimally different because all the inductorsare handmade. These values are not only satisfactorily met therequirements but also, in comparison with recent studies[4,11,14,16] which their input current ripple percentages are listedin Table 4, proves a better steady state performance for the pro-posed converter.

Fig. 13. Energy conversion efficiency for Vo = 36 V as: (a) function of the outputcurrent for different input voltage levels; (b) function of the input voltage fordifferent output current levels.

Fig. 12. Capacitors voltage ripples in buck mode, (a) Vg = 43 V, and (b) Vg = 40 V.

V. Samavatian, A. Radan / Electrical Power and Energy Systems 63 (2014) 446–454 453

The ripples of input, interface link and output voltages in bothoperation modes are depicted in Figs. 11 and 12. Maximum rippleof input and capacitor voltages are restricted to 1 V, 0.2 V, 0.05 V(%0.14) respectively.

The energy conversion efficiency is the matter of any conver-sion system. Efficiency traces are shown as a function of the outputcurrent iR for different input voltage levels in Fig. 13(a) and as afunction of the input voltage with different output current levelsin Fig. 13(b). With regard to Fig. 13, the maximum efficiency canbe obtained in both boost and buck modes and is not in the bound-ary of operating mode change because of mode transition. Maxi-mum efficiency as function of the input voltage with differentoutput current levels occurs in all current levels when input volt-age in near to 36 V, because buck switches are permanently on inthis situation and there is only conduction power loss.

Conclusions

A new non-inverting buck–boost DC–DC converter is obtainedthrough a cascade connection of an interleaved boost and an inter-leaved buck stage and assisted by a damping network at the inter-mediate capacitor to decay voltage oscillations and to improveconverter inner dynamic. Simulation and experimental results ofa prototype converter validate the predicted low-ripple I/O cur-rents due to application of interleaved technique. Efficiency studiesshow that maximum efficiency can be achieved for buck mode,where the switches boost stage are always OFF, and for boostmode, where the buck stage switches are continuously ON.

The capability of low-ripple I/O currents creates possibilities formany applications like battery, super-capacitor, PV panel, or fuelcell energy exploitation. There are still two remaining small prob-lems associated with the proposed converter, namely appearance

of several discontinuous conduction modes at light loads andRHP zero which are being worked to be solved and reported in nearfuture.

Appendix A

This appendix is provided to derive differential equationsdescribing the capacitors’ voltages and inductors’ currents in timeintervals based on Fig. 5. These equations corresponding to firstinterval have been explored in Section 2. However the other differ-ential equations are expressed here.

Interval 2 and 5: [t1 � t2 and t4 � t5], Fig. 5(b),

mL1 ðtÞ ¼ L1diL1dt ¼ mL2 ðtÞ ¼ L2

diL2dt ¼ mgðtÞ � mC1 ðtÞ

mL3 ðtÞ ¼ L3diL3dt ¼ mL4 ðtÞ ¼ L4

diL4dt ¼ mC1 ðtÞ ¼ moutðtÞ

iC1 ðtÞ ¼ C1dmC1

dt ¼ ðiL1ðtÞ þ iL2ðtÞÞ � ðiL3ðtÞ þ iL4ðtÞÞ � mC1ðtÞ�mcdðtÞRd

iC2ðtÞ ¼ C2dmC2

dt ¼ iL3ðtÞ þ iL4ðtÞ � moutðtÞR

icdðtÞ ¼ cddmcd

dt ¼mC1ðtÞ�mCdðtÞ

Rd

8>>>>>>>>><>>>>>>>>>:

ðA1ÞInterval 3: [t2 � t3 ], Fig. 5(c),

mL1 ðtÞ ¼ L1diL1dt ¼ mL2 ðtÞ ¼ L2

diL2dt ¼ mgðtÞ � mC1 ðtÞ

mL3 ðtÞ ¼ L3diL3dt ¼ mC1ðtÞ � moutðtÞ

mL4 ðtÞ ¼ L4diL4dt ¼ moutðtÞ

iC1 ðtÞ ¼ C1dmC1

dt ¼ ðiL1ðtÞ þ iL2ðtÞÞ � ðiL3ðtÞ � mC1ðtÞ�mcdðtÞRd

iC2ðtÞ ¼ C2dmC2

dt ¼ iL3ðtÞ þ iL4ðtÞ � moutðtÞR

icdðtÞ ¼ cddmcd

dt ¼mC1ðtÞ�mCdðtÞ

Rd

8>>>>>>>>>>>><>>>>>>>>>>>>:

ðA2Þ

454 V. Samavatian, A. Radan / Electrical Power and Energy Systems 63 (2014) 446–454

Interval 4: [t3 � t4], Fig. 5(d),

mL1 ðtÞ ¼ L1diL1dt ¼ mgðtÞ � mc1ðtÞ

mL2 ðtÞ ¼ L2diL2dt ¼ mgðtÞ

mL3 ðtÞ ¼ L3diL3dt ¼ mL4

diL4dt ¼ mC1ðtÞ � moutðtÞ

iC1 ðtÞ ¼ C1dmC1

dt ¼ iL1ðtÞ � ðiL3ðtÞ þ iL4ðtÞÞ � mC1ðtÞ�mcdðtÞRd

iC2ðtÞ ¼ C2dmC2

dt ¼ iL3ðtÞ þ iL4ðtÞ � moutðtÞR

icdðtÞ ¼ cddmcd

dt ¼mC1ðtÞ�mCdðtÞ

Rd

8>>>>>>>>>>>><>>>>>>>>>>>>:

ðA3Þ

Interval 6 [t5 � t6], Fig. 5(e),

mL1 ðtÞ ¼ L1diL1dt ¼ mL2ðtÞ ¼ L2

diL2dt ¼ mgðtÞ � mC1ðtÞ

mL3 ðtÞ ¼ L3diL3dt ¼ moutðtÞ

mL4 ðtÞ ¼ L4diL4dt ¼ mC1ðtÞ � moutðtÞ

iC1 ðtÞ ¼ C1dmC1

dt ¼ ðiL1ðtÞ þ ðiL2ðtÞ � ðiL4ðtÞÞ � mC1ðtÞ�mcdðtÞRd

iC2ðtÞ ¼ C2dmC2

dt ¼ iL3ðtÞ þ iL4ðtÞ � moutðtÞR

icdðtÞ ¼ cddmcd

dt ¼mC1ðtÞ�mCdðtÞ

Rd

8>>>>>>>>>>>><>>>>>>>>>>>>:

ðA4Þ

Appendix B

This appendix is provided to show numerator and denominatorcoefficients of control-to-output transfer function in buck mode.

b0 ¼ RðD12 � 1Þ2

b1 ¼ ðL34 þ L12D234 þ L34D2

12 � 2D12L34 þ CdRRd � 2CdRRdD12 þ CdRRdD212Þ

b2 ¼ ðC1L12Rþ C2L34Rþ CdRL12 � 2C2L34RD12 þ CdRdL34 � 2CdRdL34D212

þC2L12D234Rþ C2L34RD2

12 þ CdRdL12D234 þ CdRdL34D2

12

b3 ¼ ðCdC2L34RRdD212 � 2CdC2L34RRdD12 þ CdC2L12RRdD2

34 þ C1CdL12RRd

þCdC2L34RRdÞb4 ¼ L12L34ðC1C2Rþ CdC2Rþ C1CdRþ C1CdRdÞb5 ¼ C1C2CdL12L34RRd

8>>>>>>>>>>>>>>><>>>>>>>>>>>>>>>:

ðA5Þ

ad340 ¼ RVout

D34ð1� D12Þ2

ad341 ¼ Vout

D34ðCdRRdD2

12 � 2CdRRdD12 � L12D234 þ CdRRdÞ

ad342 ¼ L12Vout

D34ðCdRþ C1R� D2

34CdRdÞ

ad343 ¼ R2RdCdC1L12Vout

D34

8>>>>>><>>>>>>:

ðA6Þ

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