Electrical characterization of La-silicate gate dielectrics for SiC … · 2015-02-23 ·...

1

February, 2015 Abstract of Master Thesis

Electrical characterization of La-silicate gate dielectrics for

SiC power devices

Supervisor: Prof. Hiroshi Iwai

Tokyo Institute of Technology

Department of Electronics and Applied Physics

13M36360 Shu Munekiyo

Silicon carbide (SiC) has attracted attention as a power device material of

next generation because it has excellent physical properties such as high

breakdown field and high thermal conductivity. In addition, SiC also has an

ability that can be formed SiO2 by thermal oxidation. However, the

characteristics of 4H-SiC MOSFET using thermal oxidation SiO2 as the gate

dielectric exhibits a low inversion layer channel mobility due to large

interface state density. The possible origins of the poor MOS interface

characteristics would be the carbon related defects in near-interface region

of oxides and those on SiC surface caused by the biproducts of thermal

oxidation. Recent study on La-silicate interface layers for SiC substrates has

shown improvements in interface states and reduction in electron trapping.

Besides these improvements, the basic physical reasons have not been

clarified yet. Therefore, a systematic study to elucidate the effect of La atoms

need to be clarified. For this purpose, we conducted La2O3 capped oxidation

and SiO2 capped oxidation to form La-silicate interface layers and compared

2

the electrical characteristics of MOS capacitors.

In the case of using La2O3 capped oxidation, electrical characteristics of

SiC-MOS capacitor with La2O3 interface layer investigated. It is revealed

that La2O3 insertion between SiO2/4H-nSiC have shown improved interface

properties. In addition, further Dit and hysteresis reduction by post-oxidation-

anneal was obtained.

In the case of using SiO2 capped oxidation, electrical characteristics of SiC-

MOS capacitor investigated. First, increasing insertion La2O3 layer at oxide

/semiconductor interface is effective improved electrical characteristics. In

addition, uniform La-silicate layer is formed by carrying out SiO2 capped

anneal, and La atom is presented at oxide /semiconductor interface. These

La atom at the interface is effective relaxed the SiO4 network, it obtained

more reduced Dit and hysteresis.

With the SiN layer at the interface, it is considered La atom is not arrived

oxide/semiconductor interface by inserting SiN layer. In addition, nitrogen

was not present at oxide/semiconductor interface from EELS result.

Therefore, effect of interface nitridation was not expected by inserting SiN

layer. These results, it is necessary to choice La2O3 as inserting interfacial

layer.

In conclusion, this study gives us the instruction of understandings

electrical characteristics of improvements in lanthanum silicate gate

dielectrics on silicon carbide substrate.

3

Contents

Chapter 1. Introduction

1.1 Introduction of Silicon carbide material as power devices.................7

1.2 Gate dielectrics of SiC and MOS interface technology…………….9

1.3 Purpose of this study.......................................................................11

References.............................................................................................. 13

Chapter 2. Fabrication and Characterization

2.1 Fabrication procedure.....................................................................15

2.2 Experimental principle

2.2.1 SPM cleaning and HF treatment................................................17

2.2.2 RE-oxides deposition by MBE...................................................17

2.2.3 PDA in 5%O2 / 95%N2 ambient...................................................18

2.2.4 RF magnetron sputtering............................................................19

2.2.5 Patterning of resist by photo lithography……………………20

2.2.6 Dry etching by RIE.....................................................................20

2.2.7 PMA in F.G. ambient..................................................................22

2.2.8 Deposition of Al by vacuum evaporation ...................................22

References……………………………………………………………..23

4

Chapter 3. Process dependent interface properties of

SiC-MOS capacitor with insertion La2O3

3.1 Introduction……………………………………………………..25

3.2 Impact of annealing temperature to capacitance-voltage

characteristics…………………………………………………………27

3.3 Thickness dependence of insertion La2O3 layer on capacitance-

voltage characteristics……......…....…………...………………………..29

3.4 Impact of Post Oxidation Anneal on capacitance-voltage

characteristics………………………………………………….……..33

3.5 TEM image of La2O3 capped oxidation…………………………..36

3.6 Conclusion………………………………………………………..37

References……………………………………………………………..37

Chapter 4. Improvement interface properties of SiO2

capped oxidation

4.1 Introduction……………………………………………………..39


voltage characteris tics…………………..……………………40

4.3 TEM image of La2O3 capped oxidation………….………..…43

4.4 Conclusion………………………………………………………..45

References……………………………………………………………..45

5

Chapter 5. Effect of SiN interfacial layer on electrical

characteristics

5.1 Introduction………………………………………………………47

5.2 Thickness dependence of insertion SiN layer on capacitance-voltage

characteristics………………………………………….………………48


characteristics using SiO2 capped anneal…………………………….50

5.4 TEM image and analysis of nitrogen in interface by EELS………..52

5.4 Conclusion………………………………………………………..53

References……………………………………………………………..53

Chapter 6. Conclusions............................................................54

Acknowledgements......................................................... ..... ..........57

6

Chapter 1

Introduction

1.1 Introduction of Silicon carbide material as power devices

1.2 Reports of La-silicate as gate dielectrics

1.3 Purpose of this study

References

7

1.1 Introduction of Silicon carbide material as power devices

When using electrical energy, between consumption and power generation,

such as AC-DC converter, for converting the voltage or frequency, and in the

terminal, electrical and electronic equipment, consumer electronics, a

number of semiconductor in utilization side of the railway power devices are

being used. If low loss and high performance of these semiconductor power

devices is achieved, energy loss during using power can be significant

savings, such as contributing to the reduction of environmental load, is

extremely large the pervasive effect. Now, semiconductor power devices is

fabricated almost Silicon semiconductors, these performance has been

achieved by making full use of microfabrication technology. However, since

approaching the performance limits due to physical properties of Si, it is

considered future breakthroughs are not expected, expectations for a next-

generation power semiconductor Silicon carbide (SiC) is large.

SiC is a IV-IV compound semiconductor having a Si:50% and C:50%

science stoichiometric ratio, is a covalent bond crystal having 11% ionic. Fig.

1.1 shows comparison of physical properties of 4H-SiC and other materials.

Si-C atomic distance in the SiC crystal is short at 0.189nm, binding energy

is strong about 4.5eV. Strong binding energy of SiC add high phonon energy,

it giving a high thermal conductivity. On the other hand, when viewed as a

semiconductor, strong binding energy has given wide bandgap and high

breakdown field. In addition, SiC has high optical phonon energy, saturated

drift velocity of carrier is high. Wide bandgap and superior thermal stability

8

show SiC is suitable for the fabrication of high-temperature operation device.

Table. 1.1 Comparison of physical properties of 4H-SiC and other materials

More than 200 of the SiC polytype has been confirmed, high occurrence

probability, semiconductor applications important thing are 3C-, 4H-, 6H-

and 15R-SiC. Among these polytypes, 4H-SiC are thought to be suitable for

the most device applications. The reason for mobility, band gap and

dielectric breakdown electric field is large, anisotropy of electrical

conductivity is small, donor or acceptor level are relatively shallow, good

quality single crystal wafer is available, on the such that it can form a high-

quality epitaxial growth layer. Notable characteristic in 4H-SiC, the

breakdown field is about 10 times as high as the Si or GaAs, saturated drift

velocity of electron is about 2 times, thermal conductivity is about 10 times

as high as the Si.

In any case, currently, Si power device performance are approaching the

theoretical limit determined by the material properties, breakthrough in the

GaN ４H-SiC GaAs Si

Band gap(eV) 3.45 3.2 1.43 1.1

Mobility(electron/hole) (cm2/Vs) 1250/850 1000/50 8500/400 1500/600

Dielectric breakdown (MV/cm) 3.3 2.5 0.4 0.3

Thermal conductivity (W/cm・K) 1.3 4.9 0.45 1.5

Saturation velocity (cm/s) 2.7 107 2.2 107 1.0 107 1.0 107

Dielectric constant 9.0 9.7 12.9 11.8

BM (vs Si) 910 290 28 1

9

field of power devices has been strongly demanded. In that regard, the impact

of SiC power devices such as described above has attracted attention enough

to various institutions estimate the energy-saving effect.

1.2 Gate dielectrics of SiC and MOS interface technology

In SiC, it is possible to prepare a MOS (Metal-Oxide-Semiconductor) device

of SiO2 which is formed on the substrate as a gate insulating film. SiC is a

unique feature that can be formed of SiO2 is a good insulating film by thermal

oxidation like Si. However, carbon in the SiC remains in the oxide film and

the oxide/SiC interface, various institutions have also been research of

deposited film in order to avoid the problem. The case of thermal oxidation,

the SiC after washing is placed in a thermal oxidation furnace to oxidize the

SiC surface by flowing oxygen and water vapor in the high temperature. N2O

gas is also flowed to improvement of interface property. SiC is known to be

significantly different oxidation rate depending on the plane direction [1.1].

(0001) Si-face is the slowest oxidation rate, (112̅0) a-face is faster than 3-5

times. (0001̅) C-face is the most oxidation rate which is about 10 times faster

than (0001) Si-face. Although oxidation rate is often used more than 1100

degree C, the temperature dependence of the interfacial properties are

different depending on the plane direction. Often used is LPCVD (Low-

pressure Chemical Vapor Deposition) method and PECVD (Prasma-enhaned

Chemical Vapor Deposition) method for the formation of the deposited film.

Because it is formed at a relatively low temperature compared to thermal

10

oxidation, in order to improve the insulating properties, interface nitridation

Fig 1.2 dielectric constant and bandgap of RE-oxides [1.4].

by NO or N2O gas is often performed after the oxide film

formation.[1.2][1.3]

Thermal oxynitridation treatment under NO or N2O ambient are effective

reduce interface state density and improving the channel mobility. The

oxynitride film formed in this way, removal of terminated or carbon

compounds and the dangling bonds is facilitated by the nitrogen introduced

into MOS interface, MOS interface characteristics are improved such as

reduce the interface state and negative charge than the dry oxidation film.

Moreover, as the cause of improving the channel mobility, the effect of N

doping of the channel has also been suggested.

As SiC MOS device gate insulating film, has excellent electrical properties

0 10 20 30 40 50 60

2

3

4

5

6

7

8

9

10B

an

d G

ap

[e

V]

dielectric constant,

0 10 20 30 40 50 60

2

3

4

5

6

7

8

9

10B

an

d G

ap

[e

V]

dielectric constant,

La2O3

J. Robertson, Solid-State Electronics 49 (2005) 283–293

11

high-k dielectrics have been attempted to be deposited on the SiC substrate.

By depositing high-k dielectrics on the SiC substrate by using the CVD

method or a sputtering method, it is considered to be possible to reduce the

characteristic deterioration of the MOS interface induced carbon impurity.

As the gate dielectric, a material having a wide band gap and high dielectric

constant is desirable. However, the dielectric constant and the band gap has

a trade-off relationship, such a TiO2 with dielectric constant about 80 can not

be obtained the band offset in SiC. In the SiC device, it has a feature which

contact formation and activation annealing temperature after ion

implantation is high. Thus, although it depends on the manufacturing process

of the SiC devices, high-k is required excellent durability.

Future, searching and of the high-k materials suitable for SiC semiconductor,

direct deposition method that does not induce surface defects and

developments of improving technology of interface electrical properties is

expected.

1.3 Purpose of this study

As described above, oxide/semiconductor interface properties is improved

by interface nitridation and using high-k dielectrics. Among them, I have

noted that using La2O3 dielectric one of the high-k material as

oxide/semiconductor interface layer. La2O3 reacts with Si substrates to form

LaSixOy (La-silicates), it shows good interface property and electrical

characteristics. Recently, it is reported La-silicate interface layer has shown

to reduce the Dit and high mobility over 130 has been presented [1.4].

12

However, example of a report SiC devices with La-silicate is little, process

conditions such as interfacial La2O3 thickness and anneal condition are

unoptimized. On the basis of these, in this study, we explored the process the

deposition conditions of La2O3 and obtained further electrical characteristics

improvement.

This thesis contain 6 chapters. Fig. 1.4 shows chapter structure in this thesis.

In chapter 1, base on SiC semiconductor such as physical property is

introduced.

In chapter 2, fabrication procedure and experimental principle is described.

In chapter 3, process dependence of electrical characteristics on SiC-MOS

capacitor with La2O3 interface layer was investigated. Sample in this chapter

is fabricated by La2O3 capped anneal.

In Chapter 4, process dependence of electrical characteristics on SiC-MOS

capacitor with inserted La2O3 was investigated. Sample in this chapter is

fabricated by SiO2 capped anneal. In addition, the compositional analysis of

the gate dielectrics and formed interface layer is performed using EELS, we

investigate the relationship between the electrical characteristics and

physical analysis results.

In chapter 5, evaluation of SiC-MOS capacitor with inserted SiN was

conducted. Moreover, we make a comparison of measurement results

between SiN interface and La2O3 interface (Chapter 3 and Chapter 4), better

material as interfacial layer is decided.

Finally, in chapter 6, conclusions and prospects for future work are described.

13

References

[1.1] K.Ueno. phys. Stat. sol. (a) 162, 299 (1997).

[1.2] G.Y.Chung, C.C.Tin, J.R.Williams, K.McDonald, R.K.Chanana,

R.A.Weller, S.T.Pantelides, L.C. Feldman, O.W. Holland, M.K.Das and

J.W.Palmour, IEEE Electron Device Lett. 22, 176 (2001)

[1.3] M.Noborio, J.Suda, and T.Kimoto, IEEE Trans. Electron Devices

55,2054 (2008)

[1.4] X. Yang et al., ICSCRM Th-2B-5 (2013).

14

Chapter 2

Fabrication and Characterization

2.1 Fabrication procedure


2.2.1 SPM cleaning and HF treatment

2.2.2 RE-oxides deposition by MBE

2.2.3 RF magnetron sputtering

2.2.4 Dry etching by RIE

2.2.5 PMA in F.G. ambient

2.2.6 Wet etching with HCl and BHF

2.2.7 Vacuum evaporation for Al deposition

References

15

2.1 Experimental procedure

Fig. 2.1 shows the fabrication flow of La2O3 capped anneal samples. MOS

capacitor were fabricated on n-type 4o off-axis 4H-SiC (0001) substrates.

The substrates with ~1×1016cm-3 doped n-type epitaxial layer were subjected

to a solvent and diluted hydrofluoric acid surface cleaning. Next, 4nm and

10nm-thick La2O3 films, which act as capping layers for oxidation, were e-

beam deposited (EBD) on substrates, followed by oxidation in 5%-O2

ambient at 1000oC. Another SiO2 layer is placed by plasma-enhanced

chemical vapor deposition (PECVD) on top of the samples and annealed

again at 1000oC. Tungsten (W) gate electrodes were deposited by RF

sputtering, thereby producing a MOS capacitor. Finally, samples were

subjected to annealing in forming gas (3%-H2) at 420oC. Note that no

annealing in NO or N2O ambient was conducted in all the samples. A sample

without La2O3 layer and with POA were also fabricated as a reference. The

measurement was performed Capacitance-Voltage characteristics of devices,

it was studied the electrical characteristics due to the insertion of La2O3 layer.

Fig. 2.2 shows the fabrication flow of SiO2 capped anneal samples. SiO2

capped anneal is carrying out anneal after TEOS-SiO2 by PECVD, anneal

after La2O3 is not performed.

16

Fig.2.1 Fabrication procedure the case of using La2O3 capped anneal

Fig.2.2 Fabrication procedure the case of using SiO2 capped anneal

W/SiO2/La2O3/4H-nSiC

EB-La2O3 (0nm, 4nm, 10nm) deposition

Gate metal(W) deposition (Sputtering)

SPM and HF(20%, 5min) cleaning

Oxidation in 5%O2, 1000oC, 30min

Reactive ion etching(RIE)(Cl2+O2) of gate metal

Backside Al contact

Measurement：CV

Nd-Na=1016 cm-3

SiC substrate

W

La2O3(0, 4, 10nm)

Al

SiO2

SiC epilayer (12mm)TEOS-SiO2 deposition (40nm)

Oxidation in 5%O2, 1000oC, 30min

FGA (H2 : N2 = 3% : 97%), 420oC, 30min

W/SiO2/La2O3/4H-nSiC

EB-La2O3(2, 4, 6, 10nm) deposition

Gate metal(W) deposition (Sputtering)

SPM and HF(20%, 5min) cleaning

Reactive ion etching(Cl2+O2) of gate metal

Backside Al contact

Measurement：CV

Nd-Na=1.2 1015 cm-3

TEOS-SiO2 deposition (2min→35nm)

Oxidation in O2, 30min (1050oC)

FGA (H2 : N2 = 3% : 97%), 420oC, 30min

Backside SiO2 etching by BHF

SiC substrate

W

La2O3(2,4,6,10nm)

Al

SiO2

SiC epilayer (30mm)

17


2.2.1 SPM cleaning and HF treatment

First of all, it is important to clean the surface of Si-substrate because

particles and metal ions in fabrication processes affect the performance,

reliability, and yield of the devices [2.1]. Treatment in mixed solution of

sulfuric acid and hydrogen peroxide (H2O2:H2SO4 = 2:1) (SPM) and

treatment in hydrofluoric acid (HF) give the effective cleaning procedures.

SPM cleaning remove particles and metal ions thereby cleaning the surface

of SiC-substrate. Particles and metal ions are taken in chemical oxide formed

during SPM cleaning. Thus, 20% HF is used to etch the chemical oxide. By

this cleaning procedure the surface of Si substrate is cleaned and not affected

by contamination.

2.2.2 RE-oxides deposition by MBE

Molecular beam epitaxy is one of the vacuum evaporation methods. Figure

2.3 shows schematic illustration of MBE [2.2]. Since ultra high vacuum

(~10-6 Pa) is created inside of the chamber, the source molecule is not

scattered by residual molecules. E-beam emitted from hot-filament is

accelerated, and bended by magnetic field and then it hits on the source

material. As a result source material is heated to result in the evaporation of

the source material onto the SiC substrate.

18

Fig. 2.3 Schematic illustration of MBE.

2.2.3 PDA in 5%O2 / 95%N2 ambient

Post deposition annealing is a thermal treatment used for formation of La-

silicate. After deposition of La-silicate by electron beam. Sample will send

into Rapid Thermal Annealing (RTA) chamber for annealing. To ensure the

oxidation begins at specified temperature. A rapid heating rates was obtained

by high density lamps. In this study, annealing temperature from 800oC to

1000oC are used for the post deposition annealing.

Substrate

Molecular

beam

Source

ultra high vacuum (~10-6 Pa) Substrate heater

Shutter

19

2.2.4 RF magnetron sputtering

Gate electrode in this study is deposited by radio frequency (RF) magnetron

sputtering. Fig. 2.4 shows schematic illustration of RF magnetron sputtering.

The high voltage is applied between a substrate and a target. A magnet is set

under the target to prevent plasma damage. Then, Ar gas is flown into the

chamber and high voltage makes high electric fields. Therefore, Ar becomes

the state of plasma, and ionized. Ar ions hit the targets and atoms of the target

are emitted and the film is deposit on the substrate. The advantage of this

method is that better adhesion between substrate and target can be obtained

by this method.

Fig. 2.4 Schematic illustration of RF magnetron sputtering.

Substrate

Ar+

Target

material

Plasma

Atom of

target material

Substrate

Ar+

Target

material

Plasma

Atom of

target material

20

2.2.5 Patterning of resist by photo lithography

Resist patterning is the method to eliminate only parts of gate metal which is

needless. It is not needed in FTIR method because the absorption of interface

and inside of substrate can be measured. If the metal part is cut off, La is laid

bare, and the part of total reflection is changed, and the IR spectrum also is

changed. First, resist is applied with on the gate electrode. In this study,

positive resist which developer melts places exposed to light is used. In order

to make resist thickness uniform, SiC-substrates covered with resist are

revolved by spinner.

After that, the substrates are heated to fixate the resist (“Pre-bake”), the

substrates are adjusted to photo mask to do resist patterning. Then, they are

soaked into the developer, and the place covered with the mask is remained.

Finally, they are heated to fixate the resist (“Post-bake”).

2.2.5 Dry etching by RIE

RIE (Reactive Ion Etching) is one of the methods to etch pattern. Fig.2.5

shows schematic illustration. Etching gas which is etching W as a metal

electrode in this study is SF6. O2 is used to eliminate resist. SF6 flows and

Plasma is occurred like RF magnetron sputtering. W uncovered with resist

reacts with F- , and becomes WF6, which is gas in room temperature. After

that, O2 flows and the resist is eliminated. The process is called ashing. RIE

uses both physical and chemical reaction. Physical reaction is due to cations

collide with the substrate for electrical field. Chemical reaction occurs when

21

radicals are absorbed on the substrate, and the compounds are separated from

the substrate due to its volatility. Anisotropic etching occurs because cations

are incident vertically, which is advantage point.

Fig. 2.5 Schematic illustration of RIE.

Prasma(Cl2 +O2)

SiC substrate

22

2.2.6 PMA in F.G. ambient

Post metallization annealing (PMA) is important to improve high

performance of devices. When it is formed a vacuum, forming gas (F.G.)

(N2:H2 = 97:3) is flown and begin annealing. One of the main purposes of

PMA is dangling bonds at the interface between SiC and La2O3 dielectrics.

Si structure has periodicity and properties at the interface between Si and

La2O3 dielectrics. Therefore, many dangling bonds are generated and cause

interface state, there. By PMA, dangling bonds can be terminated. Interface

has influence on device properties qualities it causes trap, which would be

electrons recombination.

2.2.7 Deposition of Al by vacuum evaporation

Finally, on the backside of substrate, Al electrode whose melting point is

about 660oC is deposited. In this study, vacuum evaporation method is used

to deposit Al, as shown in the Fig. 2.6. First, Al is set on the W board and

then current is flown in the circuit which is connected to W board. Large

current is flown and Al is evaporated by Joule heat. Because evaporation

point of Al is lower than the melting point of W. Al is vaporized and

deposited on the substrate.

23

Fig. 2.6 Schematic illustration of vacuum evaporation method.

References

[2.1] T. Ohmi: “Advanced electronics I-15 Ultraclean ULSI gizyutu”,

pp.157-158,

[2.2] T. Watanabe: “Denshisen jochaku・ teikou kanetu jochaku sochi”,

http://www.msl.titech.ac.jp/~hosono/facilities/EBeamEvaporator.htm

Back side

of substrate

W boat

Heated

Aluminium

24

Chapter 3

Process dependent interface

properties of SiC-MOS capacitor

with insertion La2O3

3.1 Introduction

3.2 Impact of anneal temperature on capacitance-voltage characteristics


voltage characteristics

3.4 Impact of Post Oxidation Anneal (POA) on capacitance-voltage

characteristics

3.5 TEM image of La2O3 capped oxidation

3.6 Conclusion

References

25

3.1 Introduction

Recent investigations have demonstrated interface property is improved by

using La-silicate as gate dielectric in Si substrate. It is considered there are

two merits of La-silicate dielectrics.

First, La-silicate can relax strain of oxide/semiconductor interface (Fig. 3.1).

La-silicates were reported to have three dimensional silicon tetrahedron

(SiO4) networks modified with La atoms [3.1] and consisted mostly of the

covalent bonds. In addition, as La-silicates are in amorphous state under

conventional semiconductor processes, it can be speculated that bond lengths

as well as bond angles in La-silicates strongly affect electrical characteristics

as in the case of silicon dioxide. It is reported that there is a strong correlation

between strain and defect in SiO2. As a result, La-silicate is expected to

reduce Dit with decreasing interface defect.

Fig. 3.1 IR absorbance spectra with annealing temperature as a parameter.[3.1]

70080090010001100120013001400

Wavenumber (cm-1)

200

800

300

450400

500550600650700750

Absorb

ance (

a.u

.)

70080090010001100120013001400

Wavenumber (cm-1)

200

800

300

450400

500550600650700750

Absorb

ance (

a.u

.)

Si-O-Si La-O-SiGe/La2O3/n-Si

ATR-FTIR 60o

Temperature (oC)

30min

26

Fig. 3.2 Generation radical oxygen in La2O3 layer.

Secondly, La2O3 generate of radical oxygen. It is reported that La2O3 can

change external oxygen (O2) to radical oxygen (O*) (Fig.3.2)[3.2]. Radical

oxygen easy to react than external oxygen, it is expected to reduce defects

such as oxygen vacancy in SiO2. However, it is necessary to change all of

insertion La2O3 at oxide /semiconductor interface to La-silicate. Because

electrical characteristics is degraded by presence of interface state between

remained La2O3 and La-silicate (Fig.3.3).

In this thesis, we fabricated SiC-MOS capacitor with La-silicate interfacial

layer, effect on the electrical characteristics by insertion La-silicate layer is

examined. Anneal to react La2O3 carried out after La2O3 deposition by EB

because it is necessary to change all of insertion La2O3 at oxide

/semiconductor interface to La-silicate. And then, process dependent

interface properties of La-silicate structure is investigated by using above

techniques and electrical measurement.

27

Fig. 3.3 Band diagram of La2O3/La-silicate/n-SiC structure.


Capacitance-voltage (CV) characteristics measured at 100 kHz after

annealing capacitors at 800, 900, and 1000oC are shown in Fig. 3.4. Electron

trap is effectively decreased by high temperature anneal more than 900

degree C. Fourier transform infrared spectra, with attenuated-total-reaction

configuration (ATR-FTIR), of SiC substrates oxidized at 1000oC in 5%-O2

ambient with 2-nm thick La2O3 capping layer is shown in Fig. 3.5. The large

absorption peak at around 1065cm-1 is attributed to the LO modes of the

asymmetric stretching vibration of La-O-Si bond. This peaks appeared at

900°C and increase significantly with the temperature raises. This result

suggested that La-silicate formed by high temperature anneal more than 900

degree C.

La2O3

silicate (tsilicate)

Vg

Ef

n-Si

CLa2O3

n-SiC

28

Fig. 3.4 Annealing temperature dependence of capacitance-voltage characteristics of

SiC-MOS capacitor with inserted La2O3.

Fig. 3.5 Infrared absorption spectra of 2nm-thick La2O3/SiC substrate.

W/SiO2/La2O3(4nm)/SiC

Frequency : 1MHz

L/W = 100/100μm

: 1000oC

: 900oC

: 800oC

Gate voltage (V)9630-3-6-9 12 15 18

80

70

50

40

30

20

0

60C

apac

itan

ce (

nF/

cm2)

10

Ab

sorb

ance

(a.

u.)

La2O3 (2nm)/SiC, 5%O2 anneal

12501300 1200 11001150 1050 1000Wavenumbers (cm-1)

Si-O-Si

Li-O-Si

1000oC

950oC

900oC

29



Fig. 3.6 shows capacitance-voltage (CV) characteristics of samples (a)

without La2O3, (b) 4-nm-thick La2O3 and (c) 10-nm-thick La2O3 insertion.

Humps in CV curves is decreased by increasing insertion La2O3 thickness.

Fig. 3.7 shows hysteresis voltage range of all samples. Clockwise Hysteresis

reduction by one-third was obtained with La2O3 insertion. And there is little

difference with the amount of lanthanum oxide insertion. Hump and

Hysteresis affect the electron trap in gate dielectrics and interface defect.

Hence, it was considered that those trap has been reduced by insertion thicker

La2O3 layer.

Fig. 3.8 shows flatband voltage of all samples. Negative shift of flatband

voltage is carried out by increasing insertion La2O3 thickness. Such result

means negative charge in oxide is eliminated by La2O3 insertion.

Extraction of interface state density (Dit) with Terman method showed Fig

3.9. Dit reduction by two third with La2O3 insertion, and little difference with

the amount of insertion La2O3.

30

Fig. 3.6 Insertion La2O3 thickness dependence of capacitance-voltage characteristics

of SiC-MOS capacitor.

(b) La2O3 = 4nmL/W=100/100μm

: 1MHz

: 500kHz

: 100kHz

: 50kHz

Gate voltage (V)40-4-8-12 8 12 16 20

100

40

20

0

60

Cap

acit

ance

(n

F/cm

2)

80

(c) La2O3 = 10nmL/W=100/100μm

: 1MHz

: 500kHz

: 100kHz

: 50kHz

40

20

0

60

Cap

acit

ance

(n

F/cm

2 )

80

Gate voltage (V)40-4-8-12 8 12 16 20

100

40

20

0

60C

apac

itan

ce (

nF/

cm2)

80

Gate voltage (V)40-4-8-12 8 12 16 20

(a) w/o La2O3

L/W=100/100μm

: 1MHz

: 500kHz

: 100kHz

: 50kHz

31

Fig. 3.7 Decreasing hysteresis voltage range in CV curves by insertion La2O3.

Fig. 3.8 Negative shift of flatband voltage by increasing La2O3 thickness.

Hys

tere

sis

volt

age

ran

ge (

V)

1.2

0.8

0

1.6

La2O3 thickness10nm4nmno La2O3

0.4

W/SiO2/La2O3/SiC

N2(5%O2) anneal:1000oC

100kHz

8.0

4.0

2.0

0

6.0

Fla

tba

nd

volt

age

(V

)

La2O3 thickness10nm4nmno La2O3

32

: TEOS only: TEOS-SiO2 + La2O3(4nm): TEOS-SiO2 + La2O3(10nm)In

terf

ace

sta

te d

ensi

ty,

Dit

(eV

-1cm

-2)

1010

1011

1012

Surface potential (V)0.050 0.3 0.350.1 0.15 0.2 0.25

Tarman methodFrequency : 500kHz

Fig. 3.9 Interface state density of capacitance-voltage characteristics

of SiC-MOS capacitor with insertion La2O3.

.

33

3.4 Impact of Post Oxidation Anneal on capacitance-voltage

characteristics

Fig. 3.10 shows CV characteristics (100kHz) of samples that with and

without Post-Oxidation-Anneal (POA) which carried out in 5%-O2 ambient

at 800oC. A sample without La2O3 layer is also fabricated as a reference. In

the case of a sample without La2O3, improvement of electrical properties is

not confirmed. However, as for La2O3 inserted sample, we see improvements

in both stretch-out and hysteresis by POA. Stretch-out affect the interface

state density (Dit) of the interface between oxide and SiC substrate. Therefore,

this result suggest that Dit is reduced by the POA process in La2O3 inserted

sample. For this reason, it was anticipated that the strain of the interface

between oxide and SiC substrate was mitigated by La atom in La-silicate

move as network modifier during POA. In addition, hysteresis was also

reduced by carrying out the POA, smallest hysteresis was obtained in that

case (Fig. ). In these result, POA process is expected to improve the electrical

characteristics in La2O3 inserted SiC-MOS capacitor.

34

Fig. 3.10 Effect of post oxidation anneal on CV curves (a) w/o, (b) with 10nm-thick La2O3.

w/o La2O3 layerL/W=100/100μm100kHz

POA at 800oC

w/o POA

100

40

20

0

60

Cap

acit

ance

(n

F/cm

2)

80

Gate voltage (V)40-4-8-12 8 12 16 20

100

40

20

0

60

Cap

acit

ance

(n

F/cm

2 )

80

Gate voltage (V)40-4-8-12 8 12 16 20

La2O3 = 10nmL/W=100/100μm100kHz

POA at 800oC

w/o POA

20

(a)

(b)

35

Fig. 3.11 Decreasing hysteresis voltage range in CV curves by POA.

Fig. 3.12 Interface state density of capacitance-voltage characteristics

of SiC-MOS capacitor with insertion La2O3.

2.0

1.2

0.8

0

1.6

La2O3 thickness10nm4nmno La2O3 10nm(POA)

0.4

Hys

tere

sis

volt

age

ran

ge (

V)

W/SiO2/La2O3/SiC

N2(5%O2) anneal:1000oC

100kHz

: TEOS only: TEOS-SiO2 + La2O3(4nm): TEOS-SiO2 + La2O3(10nm): TEOS-SiO2 + La2O3(10nm) + POAIn

terf

ace

sta

te d

en

sity

, D

it(e

V-1

cm-2

)

1010

1011

1012

0.050 0.3 0.350.1 0.15 0.2 0.25

Terman methodFrequency : 500kHz

Surface potential (V)

36


Cross sectional transmission electron microscope (TEM) image showed

formation of La-silicate grains, with composition of La2SiO5, agglomerated

at step bunches at the surface of SiC substrates (Fig. 3.13). From the

observed change in the interface and obtained electrical characteristics, one

can anticipated that La-silicate grains are likely to passivate the charge

trapping at step bunches and effectively suppresses the Dit. However, non-

uniform oxide are concerned degradation of dielectric breakdown by topical

electric field concentration. Hence, it is considered necessary to form a more

uniform La-silicate layer.

Fig. 3.13 TEM image of La2O3 capped oxidation indicate formation of La-silicate grains

at step bunches.

SiC(0001) 50nm La2SiO5

JCPDS: 40-0234

http://ejje.weblio.jp/content/are+concerned

37

3.6 Conclusion

In this chapter, electrical characteristics of SiC-MOS capacitor with La2O3

interface layer investigated by measuring capacitance-voltage characteristics.

First, La-silicate formed by high temperature anneal more than 900 degree

C on SiC substrate. Secondly, increasing insertion La2O3 layer at oxide

/semiconductor interface is effective improved interface property (hysteresis,

Dit) and reduced trap in oxide (hump, negative charge). In addition, further

Dit and hysteresis reduction by post-oxidation-anneal was obtained. These

improvement is obtained by relaxing the SiO4 network by La atoms at the

interface, and presumable the generation of radical oxygen by La-atoms to

effectively eliminate the C at and near the interface. However, non-uniform

oxide are concerned degradation of dielectric breakdown by topical

electric field concentration. Hence, it is considered necessary to

form a more uniform La-silicate layer.

Reference

[3.1] S. D. Kosowsky, et al., APL, 73, p.3119 (1997).

[3.2] K. Kakushima, et al., Solid-State Electronic, vol. 54, pp. 720-723, 2010.


38

Chapter 4

Improvement interface properties

of SiO2 capped oxidation

4.1 Introduction




4.4 TEM image of SiO2 capped oxidation

4.5 Conclusion

References

39

4.1 Introduction

La-silicate grains with composition of La2SiO5, agglomerated at step

bunches at the surface of SiC substrates from 3.5 in Chapter 3. Moreover,

La-silicate grain formed at a position away from SiC surface. Ideally, La

atoms is uniformly distributed at around SiC to improve electrical

characteristics by relaxing interface strain. We therefore employed anneal

carried out after cap-SiO2 deposition by PECVD. In other research

institutions, electrical characteristics and uniform La-silicate/SiC interface

reported with SiO2 capped anneal (PDA). In addition, La2O3 have

characteristics change external oxygen (O2) to radical oxygen (O*), it is

considered that result in Chapter 3 obtained effect of radical oxygen.

Therefore, annealing ambient is changed to 5%O2 to O2 only.

In this thesis, electrical characteristics of SiC MOS capacitor with SiO2

capped anneal in O2 ambient. And then, we investigated effect to electrical

characteristics by confirming composition of interfacial la-silicate layer.

40

4.2 Thickness dependence of insertion La2O3 layer on

capacitance-voltage characteristics

Fig. 4.1 shows CV characteristics of samples that with and without La2O3

interface layer. Humps in CV curves is decreased by insertion La2O3. In this

result, electron trap of SiO2/La-silicate interface and oxygen vacancy in SiO2

are decreased by insertion La2O3 layer. Fig. 4.2 shows thickness dependence

of insertion La2O3 layer on CV characteristics at 100 kHz. These samples is

not carried out POA process. A sample without capped anneal (Fig. 3.8) is

also mentioned as a reference. A sample with capped anneal is improved

stretch-out in CV curves more than without capped anneal sample. This

result shows Dit is decreased by capped anneal. Fig. 4.3 shows hysteresis

voltage range of all samples. Clockwise hysteresis is effective reduced by

inserting more than 4nm-thick La2O3 interface layer. And there is little

difference with the amount of La2O3 insertion, a sample with 10nm-thick

La2O3 layer obtained lowest hysteresis voltage at 0.3V. Fig. 4.4 shows

flatband voltage of all samples. Negative shift of flatband voltage is carried

out by increasing insertion La2O3 thickness. Hence, it considered negative

charge in oxide is also eliminated in capped anneal.

41

Fig. 4.1 CV curves (a) w/o, (b) with 10nm-thick La2O3.

140

40

0

Ca

pa

cita

nce

(n

F/cm

2)

80

Gate voltage (V)20-2-4-6 4 6 8 10 1412

120

: 1MHz

: 500kHz

: 100kHz

: 10kHz

W/TEOS-SiO2/SiC1050oC oxidation50mm/50mm100

60

20

140

40

0

Ca

pa

cita

nce

(n

F/cm

2)

80

Gate voltage (V)20-2-4-6 4 6 8 10 1412

120

: 1MHz

: 500kHz

: 100kHz

: 10kHz

W/TEOS-SiO2/La2O3(10nm)/SiC1050oC oxidation50mm/50mm100

60

20

(b)

(a)

42

Fig. 4.2 Insertion La2O3 thickness dependence of capacitance-voltage characteristics


Fig. 4.3 Decreasing hysteresis voltage range in CV curves by insertion La2O3.

140

40

0

Cap

acit

ance

(n

F/cm

2)

80

Gate voltage (V)20-2-4-6 4 6 8 10 1412

120W/TEOS-SiO2/La2O3/SiC50mm/50mm

100

60

20

: La2O3 = 10nm

: La2O3 = 6nm

: La2O3 = 4nm

: La2O3 = 2nm

: 10nm,POA800oC

0.2

0

Hys

tere

sis

(V)

La2O3 thickness10nm4nm2nm 6nm

W/TEOS-SiO2/La2O3/SiC1050oC oxidation

500kHz0.6

0.8

0.4

43

Fig. 4.4 Negative shift of flatband voltage by increasing La2O3 thickness.


Fig.4.5 showed cross sectional transmission electron microscope (TEM)

image of Metal-Oxide-Semiconductor interface in the case of capped anneal.

It showed formation of uniform La-silicate layer. In addition, La-silicate

layer is separated about 10nm from interface. Therefore, electron can’t

tunnel to SiO2/La-silicate interface state, the electrical properties are not

affected by the interface. EELS analysis has been conducted to identify the

composition of each region. Specific spots in each region has been selected

and numbered respectively, as shown in Fig.4.5. Fig 4.6 show the EEL

spectra of Spot 1 to 4, respectively. From this result, La atom is presented at

4.0

2.0

0

6.0

Flat

ban

dvo

ltag

e (

V)

La2O3 thickness10nm4nm2nm 6nm

W/TEOS-SiO2/La2O3/SiC1050oC oxidation

500kHz

44

Fig. 4.5 TEM image of SiO2 capped oxidation indicate formation of La-silicate layer

.

Fig 4.6 Electron energy loss spectra (a) Spot 1 (b) Spot 2 (c) Spot 3 (d) Spot 4

oxide /semiconductor interface at spot 4. Hence, interface property is

improved depending on interface strain relaxing by presented La atom at

interface[4.1].

4H-SiC (0001), 4ooff

SiO2

La-silicate

30nm

Gate metal(W)

c

o

u

n

t

s

c

o

u

n

t

s

c

o

u

n

t

s

c

o

u

n

t

s

500 600 700 800 900 1000

500 600 700 800 900 1000 500 600 700 800 900 1000

500 600 700 800 900 1000

(a) (b)

(c) (d)

Energy loss (eV) Energy loss (eV)

Energy loss (eV) Energy loss (eV)

O

La

O

La

O

La

O

45

4.4 Conclusion

In this chapter, electrical characteristics of SiC-MOS capacitor with La2O3

interface layer investigated by measuring capacitance-voltage characteristics

in the case of carrying out SiO2 capped anneal. First, increasing insertion

La2O3 layer at oxide /semiconductor interface is effective improved electrical

characteristics. In addition, uniform La-silicate layer is formed by carrying

out SiO2 capped anneal, and La atom is presented at oxide /semiconductor

interface. These La atom at the interface is effective relaxed the SiO4 network,

it obtained more reduced Dit and hysteresis than La2O3 capped anneal of

chapter.3.

Reference

[3.1] S. D. Kosowsky, et al., APL, 73, p.3119 (1997).

46

Chapter 5

Effect of SiN interfacial layer on

electrical characteristics

5.1 Introduction


characteristics


characteristics by SiO2 capped anneal

5.4 TEM image of SiO2 capped anneal with interfacial SiN

5.5 Conclusion

References

47

5.1 Introduction

Improvement of interface properties of SiC-MOS capacitor is general

employed interface nitridation by NO and N2O Anneal. In addition,

deposited SiO2/SiN stack gate structures have been investigated to improve

SiC MOS interface quality [5.1].

Step bunch of SiC surface has plane direction different from terrace (Si-face

(0001))[5.2]. Therefore, oxidation rate in part of step bunch is different, too.

As a result, non-uniform oxide is formed by effect of step bunch. However,

it is considered insertion SiN at interface can buffer reaction of La2O3 from

effect of step bunch.

From these factors, in this thesis, we investigated interface nitridation of SiC-

MOS capacitor with interfacial SiN layer. In order to investigate interface

nitridation, capacitance voltage characteristics is mainly evaluated. In

addition, we make a comparison of electrical properties between SiN

interface and La2O3 interface (Chapter 3 and Chapter 4), better material as

interfacial layer is decided.

48


characteristics

Fig. 5.1 shows comparison of CV characteristics at 1MHz capacitors with

SiN interface layer. SiN thickness are 2.7nm, 4.6nm and 8.0nm, respectively.

Humps in CV curves is increased by increasing insertion SiN thickness. As

this cause, it is considered that remained defect in SiN and plasma damage

by PECVD during SiN deposition. Fig. 5.2 shows trapped charge and

released charge at capacitors with SiN interface layer. These charge is

calculated from CV curves from Fig. 5.1. From the result, it is necessary to

use an at least thinner than 2.7nm SiN as an interfacial layer to eliminate

these charge.

Fig. 5.1 Insertion SiN thickness dependence of capacitance-voltage characteristics


90

70

50

40

30

20

0

60

Cap

acit

ance

(n

F/cm

2)

10

80

Gate voltage (V)1050-5-10 15 20 25 30 35

La2O3 = 10nm1MHz

4.6nm

8.0nm

SiN = 2.7nm

49

Fig. 5.2 Calculated trap and released charge with SiN thickness as a parameter.

2.0

1.0

0.5

0

1.5

Trap

ped

ch

arge

() 2.5

2.7nm

4.6nm

8.0nm

La2O3 = 10nm1MHz

SiN thickness (nm)6.04.02.01.0 8.07.05.03.0

× 1013

1.2

0.4

0

0.8

Rel

ease

d c

har

ge (

) 1.6

2.7nm

4.6nm

8.0nm

La2O3 = 10nm1MHz

SiN thickness (nm)6.04.02.01.0 8.07.05.03.0

× 1013

50


characteristics using SiO2 capped anneal

Fig. 5.3 shows capacitance-voltage (CV) characteristics of samples (a) 1.5-

nm-thick SiN insertion. (b) 6-nm-thick La2O3. Oxide of measured device is

fabricated SiO2 capped anneal. Humps in CV curves is decreased by

decreasing insertion SiN thickness. This result suggested that an absolute

quantity of defect in SiN is decreased by decreasing SiN thickness. Moreover,

frequency dispersion is also decreased. The main cause of frequency

dispersion is trapping and releasing of electron in the SiN/SiC interface states

are not able to follow the frequency of input signal. Therefore, sample with

thicker SiN has larger interface state density than thinner SiN sample.

Comparing stretch-out of these results and Fig. 4.1(b), sample with SiN

interfacial layer shows gentry sloping characteristics. La atom is able to relax

the SiO4 network, consequently eliminate defects of oxide/semiconductor

interface and bulk of oxide. However, La atom is not arrived

oxide/semiconductor interface by inserting SiN layer. Hence, it is consider

that in the case of sample with SiN interfacial layer obtained larger Dit.

http://ejje.weblio.jp/content/dispersion

http://ejje.weblio.jp/content/dispersion

51

Fig. 5.3 Insertion SiN thickness dependence of capacitance-voltage characteristics

of SiC-MOS capacitor, and using SiO2 capped anneal.

100

20

0

Cap

acit

ance

(n

F/cm

2)

80

Gate voltage (V)20-2-4-6 4 6 8 10 1412

: 1MHz

: 500kHz

: 100kHz

: 10kHz

W/SiO2/La2O3(10nm)/SiN(1.5nm)SiC

1050oC oxidation100mm/100mm

60

40

100

20

0

Cap

acit

ance

(n

F/cm

2)

80

Gate voltage (V)20-2-4-6 4 6 8 10 1412

: 1MHz

: 500kHz

: 100kHz

: 10kHz

W/SiO2/La2O3(10nm)/SiN(6nm)SiC1050oC oxidation100mm/100mm

60

40

52

5.4 TEM image and analysis of nitrogen in interface by EELS

Fig. 5.4 shows Cross sectional transmission electron microscope (TEM)

image of formed La-silicate by SiO2 capped anneal. La-silicate is formed like

layer on SiC substrate. However, agglomerated la-silicate is observed in a

part. Fig. 5.5 shows EELS analysis of agglomerated la-silicate and

oxide/semiconductor interface. In this result, nitrogen was not present at

oxide/semiconductor interface. Therefore, effect of interface nitridation was

not expected by inserting SiN layer. This reason is outward diffusion of

nitrogen during high temperature anneal after SiO2 deposition.

Fig. 5.4 TEM image of SiO2 capped oxidation indicate formation of La-silicate layer.

Fig. 5.5 EELS analysis of agglomerated la-silicate and oxide/semiconductor interface.

La-silicate

SiO2

4H-SiC (0001), 4ooff 30nm

0 5 10 15 20 25 30 35

Intensity[a.u.]

Distance[nm]

N-K

O-K

La-M

53

5.6 Conclusion

In this chapter, electrical characteristics of SiC-MOS capacitor with SiN


First, in the case of SiN insertion, there is a tendency which humps and Dit

are large. It is considered La atom is not arrived oxide/semiconductor

interface by inserting SiN layer. In addition, nitrogen was not present at

oxide/semiconductor interface from EELS result (Fig. 5.4). Therefore, effect

of interface nitridation was not expected by inserting SiN layer. These results,

it is necessary to choice La2O3 as inserting interfacial layer.

Reference

[5.1] M. Noborio, J. Suda, T. Kimoto, Materials Science Forum Vols. 600-

603 (2009) pp 679-682.

[5.2] K.Ueno. phys. Stat. sol. (a) 162, 299 (1997).

54

Chapter 6

Conclusions

In this thesis, physical understanding of interface improvements in La-

silicate gate dielectrics on silicon carbide substrate is investigated. In this

chapter, the studies are summarized below.

a)Electrical characteristics improved by insertion La2O3 (Chapter 3)

In chapter 3, electrical characteristics of SiC-MOS capacitor with La2O3

interface layer investigated. It is revealed that La2O3 insertion between

SiO2/4H-nSiC have shown improved interface properties. In addition, further

Dit and hysteresis reduction by post-oxidation-anneal was obtained. However,

non-uniform oxide by effect of step bunch at SiC surface are concerned

degradation of dielectric breakdown by topical electric field concentration.


55

b) MOS interface is achieved that indicates the uniform and

good characteristics by SiO2 capped anneal (Chapter 4)

In chapter 4, electrical characteristics of SiC-MOS capacitor with La2O3

interface layer investigated in the case of carrying out SiO2 capped anneal.

First, increasing insertion La2O3 layer at oxide /semiconductor interface is

effective improved electrical characteristics. In addition, uniform La-silicate

layer is formed by carrying out SiO2 capped anneal, and La atom is presented

at oxide /semiconductor interface. These La atom at the interface is effective

relaxed the SiO4 network, it obtained more reduced Dit and hysteresis than

La2O3 capped anneal of chapter.3.

c) Necessary to choice La2O3 as inserting interfacial layer (Chapter 5)

In this chapter, electrical characteristics of SiC-MOS capacitor with SiN


First, in the case of SiN insertion, there is a tendency which humps and Dit

are large. It is considered La atom is not arrived oxide/semiconductor

interface by inserting SiN layer. In addition, nitrogen was not present at

oxide/semiconductor interface from EELS result (Fig. 5.4). Therefore, effect

of interface nitridation was not expected by inserting SiN layer. These results,

it is necessary to choice La2O3 as inserting interfacial layer.

56

In conclusion, this thesis provides useful information and further

understanding for La-silicate/SiC structure. These studies are also expected

to contribute to the future progress of SiC power devices.

57

Acknowledgments

First of all, I would like to express my gratitude to my supervisor Prof.

Hiroshi Iwai for his continuous encouragement and advices for my study. He

also gave me many chances to attend conferences. The experiences are

precious for my present and future life.

I deeply thank to Kenji Natori, Prof. Kazuo Tsutsui, Prof. Hitoshi

Wakabayashi, Prof. Nobuyuki Sugii, Prof, Akira Nishiyama, Prof. Yoshinori

Kataoka, and Associate Prof. Kuniyuki Kakushima for useful advice and

great help whenever I met difficult problem.

I also thank research colleagues of Iwai Lab. for their friendship, active

many discussions and many of encouraging words.

I would like to appreciate the support of secretaries, Ms. Nishizawa and

Ms. Matsumoto.

Finally, I would like to thank my parents Tsuyoshi and Akemi and my

sister Yuri for their endless support and encouragement.

Shu Munekiyo

February, 2014

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