High Performance Carbon Nanofiber Supercapacitor Electrode ...
ELECTRICAL CHARACTERIZATION OF CARBON NANOFIBER …Poster ELECTRICAL CHARACTERIZATION OF CARBON...
2
TNT2005 29 August - 02 September, 2005 Oviedo-Spain Electrical Characterization of Carbon Nanofiber Arrays for On-chip Interconnect Applications Quoc Ngo 1,2 , Jun Li 2* , Alan M. Cassell 2 , Shoba Krishnan 1 , M. Meyyappan 2 , and Cary Y. Yang 1 1 Santa Clara University, Center for Nanostructures, 500 El Camino Real, Santa Clara, California, USA 95050 2 NASA Ames Research Center, Center for Nanotechnology, Moffett Field, California, USA 94035 *Corresponding author e-mail: [email protected] On-chip interconnects fabricated using copper damascene technology have provided the performance necessary to keep pace with the International Technology Roadmap for Semiconductors (ITRS) [1] since the adoption of copper as a replacement for aluminum-based wiring schemes. As microelectronics moves towards the 45 nm node and beyond, however, a multitude of factors provide a formidable challenge for the science and engineering community. Issues such as reliability under high current stress, and high resistivity due to enhanced electron scattering processes at small dimensions provide the motivation for new on-chip interconnect material development. Carbon-based nanostructures such as carbon nanotubes (CNTs) and carbon nanofibers (CNFs) have been shown to possess outstanding electrical [2-4], thermal [5-7], and mechanical [8-9] properties suitable for on-chip interconnect integration schemes. This work presents a critical evaluation of both the reliability and resistivity of carbon nanofiber structures as they apply to interconnect systems. A model system for the work presented here is shown in figure 1. A free-standing, vertically aligned CNF array is grown by plasma enhanced chemical vapor deposition (PECVD) [10] as shown in figure 1 (a), and is subsequently gap-filled with SiO 2 and subjected to chemical mechanical polishing [11] as shown in figure 1 (b). Figure 1 (c) shows the microstructural characteristics of a single as- grown CNF investigated by transmission electron microscopy (TEM). Initial electrical testing performed on single CNFs show the metallic behavior of our plasma-grown nanofibers at room temperature (figure 2). Stress tests performed at room temperature indicate the robustness of the CNF array, as shown in figure 3. The inset of figure 3 shows the I-V characteristics of the array after approximately 180 hours of high current density stress (1x10 7 A/cm 2 ), showing no degradation of the ohmic behavior. Similar measurements conducted at elevated temperatures exhibited the same characteristics. In addition to the outstanding reliability demonstrated by the CNF array, low temperature measurements were performed to elucidate their fundamental electron transport processes. The low-temperature conductance of the CNF array (figure 4) can be explained by examining transport processes at low temperatures of pure basal plane graphite, where the conductance monotonically increases with respect to temperature. At temperatures above 180K, the material behaves as a metallic conductor, exhibiting a low temperature coefficient of resistance (TCR). Fundamental measurements of temperature-dependent conductance and reliability of carbon nanofiber array structures have been investigated. The results of these studies demonstrate progress towards the possible integration of these carbon-based nanostructures into next- generation ultra-large scale integrated (ULSI) on-chip interconnect schemes. While the preliminary electrical measurements demonstrate the viability of this material for interconnect applications, further work is required to eliminate integration issues before such structures are implemented. Poster ELECTRICAL CHARACTERIZATION OF CARBON NANOFIBER ARRAYS FOR ON-CHIP INTERCONNECT APPLICATIONS
Transcript of ELECTRICAL CHARACTERIZATION OF CARBON NANOFIBER …Poster ELECTRICAL CHARACTERIZATION OF CARBON...
TNT2005 29 August - 02 September, 2005 Oviedo-Spain
Electrical Characterization of Carbon Nanofiber Arrays for On-chip Interconnect
Applications
Quoc Ngo1,2, Jun Li2*, Alan M. Cassell2, Shoba Krishnan1, M. Meyyappan2, and Cary Y. Yang1
1Santa Clara University, Center for Nanostructures, 500 El Camino Real, Santa Clara, California, USA 95050
2NASA Ames Research Center, Center for Nanotechnology,
Moffett Field, California, USA 94035 *Corresponding author e-mail: [email protected]
On-chip interconnects fabricated using copper damascene technology have provided the performance necessary to keep pace with the International Technology Roadmap for Semiconductors (ITRS) [1] since the adoption of copper as a replacement for aluminum-based wiring schemes. As microelectronics moves towards the 45 nm node and beyond, however, a multitude of factors provide a formidable challenge for the science and engineering community. Issues such as reliability under high current stress, and high resistivity due to enhanced electron scattering processes at small dimensions provide the motivation for new on-chip interconnect material development. Carbon-based nanostructures such as carbon nanotubes (CNTs) and carbon nanofibers (CNFs) have been shown to possess outstanding electrical [2-4], thermal [5-7], and mechanical [8-9] properties suitable for on-chip interconnect integration schemes. This work presents a critical evaluation of both the reliability and resistivity of carbon nanofiber structures as they apply to interconnect systems. A model system for the work presented here is shown in figure 1. A free-standing, vertically aligned CNF array is grown by plasma enhanced chemical vapor deposition (PECVD) [10] as shown in figure 1 (a), and is subsequently gap-filled with SiO2 and subjected to chemical mechanical polishing [11] as shown in figure 1 (b). Figure 1 (c) shows the microstructural characteristics of a single as-grown CNF investigated by transmission electron microscopy (TEM). Initial electrical testing performed on single CNFs show the metallic behavior of our plasma-grown nanofibers at room temperature (figure 2). Stress tests performed at room temperature indicate the robustness of the CNF array, as shown in figure 3. The inset of figure 3 shows the I-V characteristics of the array after approximately 180 hours of high current density stress (1x107 A/cm2), showing no degradation of the ohmic behavior. Similar measurements conducted at elevated temperatures exhibited the same characteristics. In addition to the outstanding reliability demonstrated by the CNF array, low temperature measurements were performed to elucidate their fundamental electron transport processes. The low-temperature conductance of the CNF array (figure 4) can be explained by examining transport processes at low temperatures of pure basal plane graphite, where the conductance monotonically increases with respect to temperature. At temperatures above 180K, the material behaves as a metallic conductor, exhibiting a low temperature coefficient of resistance (TCR). Fundamental measurements of temperature-dependent conductance and reliability of carbon nanofiber array structures have been investigated. The results of these studies demonstrate progress towards the possible integration of these carbon-based nanostructures into next-generation ultra-large scale integrated (ULSI) on-chip interconnect schemes. While the preliminary electrical measurements demonstrate the viability of this material for interconnect applications, further work is required to eliminate integration issues before such structures are implemented.
Poster
ELECTRICAL CHARACTERIZATION OF CARBON NANOFIBER ARRAYS FOR ON-CHIP INTERCONNECT APPLICATIONS
TNT2005 29 August - 02 September, 2005 Oviedo-Spain
References:
[1] International Technology Roadmap for Semiconductors (ITRS, 2004) http://public.itrs.net. [2] Q. Ngo, D. Petranovic, S. Krishnan, A. M. Cassell, Q. Ye, J. Li, M. Meyyappan, and C. Y. Yang, IEEE
Trans. Nanotech., 3 (2004) 311. [3] M. Nihei, D. Kondo, A. Kawabata, S. Sato, H. Shioya, M. Sakaue, T. Iwai, M. Ohfuti, and Y. Awano,
Proc. IEEE Intl. Interconnect Tech. Conf. (2005) 234. [4] F. Kreupl, A. P. Graham, G. S. Duesberg, W. Steinhogl, M. Liebau, E. Unger, and W. Honlein,
Microelectronic Engineering, 64 (2002) 399. [5] P. Kim, L. Shi, A. Majumdar, and P. L. McEuen, Phys. Rev. Lett., 87 (2001) 215502-1. [6] Q. Ngo, B. A. Cruden, A. M. Cassell, G. Sims, M. Meyyappan, J. Li, and C. Y. Yang, Nano Lett., 4
(2004) 2403. [7] H. F. Chuang, S. M. Cooper, M. Meyyappan, B. A. Cruden, J. Nanoscience and Nanotechnology, 4
(2004) 964. [8] J.-P. Salvetat-Delmotte and A. Rubio, Carbon, 40 (2002) 1729. [9] C. Wei and D. Srivastava, Appl. Phys. Lett., 85 (2004) 2208. [10] B. A. Cruden, A. M. Cassell, Q. Ye, and M. Meyyappan, J. Appl. Phys., 94 (2003) 4070. [11] J. Li, Q. Ye, A. Cassell, H. T. Ng, R. Stevens, J. Han, and M. Meyyappan, Appl. Phys. Lett, 82 (2003)
2491.
Figure 1. (a) cross-sectional SEM view of plasma-grown CNF array. (b) Angled view of CNFs protruding from SiO2 matrix. (c) TEM image showing nickel catalyst particle and fiber-like microstructure of a single CNF.
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Figure 4. Conductance per unit length versus temperature for a CNF array. The conductance exhibits a monotonic increase with respect to temperature for T < 180K, and exhibits metallic behavior at temperatures approaching room temperature.
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Poster
