Electrical Characterization of Advanced MOS DevicesSlide No. 3 WMED Tutorial April 3, 2009 Eric M....
Transcript of Electrical Characterization of Advanced MOS DevicesSlide No. 3 WMED Tutorial April 3, 2009 Eric M....
Slide No. 1
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 1Slide No. 1 1
Eric M. VogelAssociate Professor
Dept. of Materials Science and EngineeringDept. of Electrical Engineering
The University of Texas at Dallas
Electrical Characterization of Advanced MOS Devices
Slide No. 2
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 2Slide No. 2 2
Acknowledgments
• SEMATECH• FUture Semiconductor innovatION (FUSION) Center funded by COSAR (Korea) and Texas Emerging Technology Fund• The National Institute of Standards and Technology (NIST), Semiconductor Electronics Division (SED)
Slide No. 3
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 3Slide No. 3 3
Books for Review
• Semiconductor Material and Device Characterization, by D. K. Schroeder, Wiley InterScience.
• Device Electronics for Integrated Circuits, by R. S. Muller and T. I. Kamins, John Wiley & Sons.
• Operation and Modeling of the MOS Transistor, by Y. P. Tsividis, McGraw Hill
• Handbook of Semiconductor Manufacturing Technology, ed. by Y. Nishi and R. Doering, Marcel Dekker.
• Handbook of Silicon Semiconductor Metrology, ed. by A. Diebold, Marcel Dekker.
• High-k Gate Dielectrics, ed. by M. Houssa, Institute of Physics.
• Silicon-on-Insulator: Materials to VLSI, by J.-P. Colinge, Springer.
• Electrical Characterization of Silicon On Insulator Materials and Devices, by S. Cristoloveanu and S. S. Li, Kluwer Academic Publishers.
Slide No. 4
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 4Slide No. 4 4
Goals for this Tutorial
• The experimental techniques, theory, and fundamental understanding necessary to extract parameters of interest from MOS capacitance-voltage and MOS transistor characterization.
• Issues related to applying these techniques, theory and understanding to advanced MOS devices especially including high-k gate dielectrics, and non-silicon (e.g. III-V) semiconductors.
Slide No. 5
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 5Slide No. 5 5
Ken David, “Intel Makes Transistor Breakthrough Using New Materials”, ftp://download.intel.com/technology/silicon/InSb_press_presentation.pdf, Dec. 2005.
Technology Scaling
Slide No. 6
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 6Slide No. 6 6
Electrical Characterization Challenges
• Changes to all of the materials that make the MOS transistor (semiconductor, gate dielectric, gate electrode, source-drain) are being considered.
• The challenges to electrical characterization are numerous.
Slide No. 7
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 7Slide No. 7 7
Outline
• Capacitance-Voltage• Transistor Parameter Extraction
Slide No. 8
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 8Slide No. 8 8
Capacitance-Voltage
• Measurement Issues• Theory (Without Interface States)• Parameter Extraction• Including Interface States
Slide No. 9
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 9Slide No. 9 9
Measurement Conditions
• The ac voltage should be as small as possibleto ensure small signal approximation while still allowing accurate measurement.
• Assuming that the device capacitance is properly extracted from the measured capacitance, either parallel or series mode may be used since the one can be derived from the other (Cs=Cp*(1+D2), D=1/ωRpCp).
• Quasi-static C-V measurements generally can not be performed (using standard q-s meters) due to the large leakage currents.
Slide No. 10
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 10Slide No. 10 10
Measurement Errors
Relative Measurement Accuracy for HP4284A
Calculations from HP4284A Precision LCR Meter Operation Manual p. 9-7 to 9-15
This is only valid for: medium/long integration100Hz <= F <= 1MHz1 m cableVdc < 20 V30mV <= Vac <= 150mV <or> Vac = 10mV,20mV,25mVCp-Gp measurement modeshort and open correction performed
InputC (F) 1.30E-10G (S) 1.00E-02F (Hz) 1.00E+03Vac (Vrms) 5.00E-02
OutputC_relacc (+/-%) 1288.996212 (FYI: CalG_relacc (+/-%) D too large (D>0.1)* 1.05296E-05 (FYI: CalD_relacc (+/-%) 157833.5641 (FYI: Cal
• The relative measurementaccuracy of an LCR meterdepends on the frequency and the nominal capacitanceand conductance of the deviceunder test.
• We have developed a spreadsheet which calculatesthe relative measurementaccuracy of the HP4284A.
Slide No. 11
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 11Slide No. 11 11
Measurement Errors
• The relative capacitancemeasurement error of an LCR meter increases with:
→ decreasing frequency→ increasing conductance→ decreasing capacitance
Frequency (Hz)102 103 104 105 106
Cap
acita
nce
Erro
r (+/
- %)10-2
10-1
100
101
102
103
104
105
C = 10-11 F, G = 10-3 SC = 10-11 F, G = 10-6
SC = 10-10 F, G = 10-6 S
Slide No. 12
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 12Slide No. 12 12
Capacitor Equivalent Circuits
Cox
Csub
Gt
Cit Git
Rs
Lo
Rs
Lo
Cc Gc
• The equivalent circuit of the capacitor can be thought of those parts intrinsic to the capacitor (Cc and Gc) and those extrinsic (Rs and Lo).• The intrinsic capacitor can be thought of as having parts related to the dielectric (Cox and Gt), interface states (Cit and Git) and the semiconductor (Csub).
Slide No. 13
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 13Slide No. 13 13
Equivalent Circuits
LCR Measurement Capacitor Equivalent Circuit
Transistor Equivalent Circuit†
†K. Ahmed, et al., IEEE Trans. Elec. Dev., vol. 46, pp. 1650-1655, 1999.
• The LCR meter measures an equivalent capacitance in parallel with a conductance.• The equivalent circuit of a transistor is a distributed version of the capacitor.
Slide No. 14
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 14Slide No. 14 14
Examples of Measured Behavior
Vg (V)-3 -2 -1 0 1 2 3
Cap
acita
nce
(pF)
0
20
40
60
80
100
120
140 102 Hz103
Hz104 Hz105 Hz106 Hz
ISSG 2.1 nmArea = 5x10-5 cm2
Vg (V)-3 -2 -1 0 1 2
Cap
acita
nce
(pF)
0
100
200
300
400
500
600
F = 10 kHzF = 1 MHz
• For thicker dielectrics, a simple reduction in capacitance athigh frequencies due to seriesresistance is many times observed.
• For thinner or leakier dielectrics, capacitance roll-over, negative capacitance, and increasing capacitance with bias is sometimes observed.
Slide No. 15
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 15Slide No. 15 15
Correcting Measured Capacitance
• Previous work provided methodologies to correct measured capacitance for leakage and series resistance1,2
including the impact of series inductance3.
• It is unknown whether theseries inductance is due to measurement (e.g. cabling)4
or a physical phenomenon5.
1K. J.Yang and C. Hu, IEEE Trans. Elec. Dev., vol. 46, pp. 1500-1501, 1999.2E. M. Vogel, W. K. Henson, C. A. Richter, and J. S. Suehle, IEEE Trans. Elec. Dev., vol. 47, p. 601, 2000.3H.-T. Lue, C.-Y. Liu, and T.-Y. Tseng, IEEE Elec. Dev. Lett., vol. 23, pp. 553-555, 2002.4A. Nara, N. Yasuda, H. Satake, and A. Toriumi, IEEE Trans. Semi. Manuf., vol. 15, pp. 209-213, 2002.5M. Matsumura, and Y. Hirose, Jap. J. Appl. Phys., vol. 39, pp. L123-L125, 2000.
Slide No. 16
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 16Slide No. 16 16
Modeling “Measured” Capacitance
( )( ) ( )2222
22
1
1
ocscocsc
ococcm
LGRCLCRG
LGLCCC+++−
−−=
ωω
ω
( )( ) ( )2222
22
11
ocscocsc
scsccm
LGRCLCRGRCRGGG
+++−
−+=
ωωω
Vg (V)-3 -2 -1 0 1
Cap
acita
nce
(pF)
-200
0
200
400
600
800
1000Correct CapacitanceRs=20Ω, L=0μHRs=20Ω, L=10μHRs=20Ω, L=45μH
Rs=103Ω, L=0μH
F=1MHz
• Series resistance alone cannot explain an increase in or negative measured capacitance at high frequency.
• Inductance is necessary to observe an increase in or negative capacitance at high frequency.
Slide No. 17
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 17Slide No. 17 17
An example: HfO2 on GaAs
• Is this behavior due to Rs?• Extraction of Rs is not possible.
-1 0 1 2
1.00
2.00
3.00
4.00
Cap
acita
nce,
μF/
cm2 100Hz
1KHz 10KHz 100KHz1MHz
100 μm Pad
CV Characteristics
Slide No. 18
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 18Slide No. 18 18
Modeling “Measured” Capacitance
( ) ( )2 221c
mc s c s
CCG R C Rω
=+ +
• The conductance at low frequency is due to dc leakage through the dielectric (Gt ~ Gc).• By breaking down the dielectric, an estimate of the of the series resistance can be determined (Rs). • A simulation can be used to determine the approximate device capacitance (Cc) at a given frequency.
Vg (V)
-4 -3 -2 -1 0 1 2 3
Cm
(μF/
cm2 )
0.00.40.81.21.62.02.42.83.23.64.0
log(Gm ) (S/cm
2)
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
200μmX200μm Capacitor
102 Hz103 Hz104 Hz105 Hz106 HzD.C.
~2.0 nm RTO
• The previous example was not due to Rs.
Slide No. 19
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 19Slide No. 19 19
C-V Theory
• Potential and Charge Balance• Built-in Voltage• Total Semiconductor Charge• Regions of Operation• Capacitance• Quantum Mechanical Effects
Slide No. 20
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 20Slide No. 20 20
Equations for C-V
bioxpolysubg VVVVV ++−=
( ) ( ) 0=++ oxpolypolysubsub QVQVQ
• To calculate C-V, we need to solve the above equations.
• Vpoly is measured from the oxide-poly interface to the bulk of the poly. Vpoly = 0 for metal gate electrodes.• Qox is charge in the oxide that is fixed with bias.• We will first neglect defects in the dielectric that change occupancy with applied bias (interface states).• Vbi is the built-in potential between the gate and substrate.
Potential Balance:
Charge Balance:
Slide No. 21
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 21Slide No. 21 21
Equations for C-V
( )−+ −+−= ad NNnpqρ
( )
( )
1 2
1 2
2
2
1 2exp
1 4exp
gapv
t
c
t
d
d c
t
a
a c
t
EN F
N F
NqE E
NE E
ηϕπ
ηϕπ
ρη
ϕ
ηϕ
⎛ ⎞− −⎛ ⎞⎜ ⎟⎜ ⎟
⎝ ⎠⎜ ⎟⎜ ⎟⎛ ⎞⎜ ⎟− ⎜ ⎟⎜ ⎟⎝ ⎠⎜ ⎟⎜ ⎟= +⎜ ⎟⎛ ⎞− −⎜ ⎟+ ⎜ ⎟⎜ ⎟⎝ ⎠⎜ ⎟⎜ ⎟−⎜ ⎟⎛ ⎞− −
+⎜ ⎟⎜ ⎟⎜ ⎟⎝ ⎠⎝ ⎠
( )
( )
( )
( )⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥⎥
⎦
⎤
⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢⎢
⎣
⎡
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜
⎝
⎛
⎟⎠
⎞⎜⎝
⎛ −−−+
⎟⎠
⎞⎜⎝
⎛ −−++−
+
⎟⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜⎜
⎝
⎛
⎟⎟⎟⎟
⎠
⎞
⎜⎜⎜⎜
⎝
⎛
⎟⎠
⎞⎜⎝
⎛ −−++
⎟⎠
⎞⎜⎝
⎛ −−++
+⎟⎟⎠
⎞⎜⎜⎝
⎛⎟⎟⎠
⎞⎜⎜⎝
⎛ +−⎟⎟
⎠
⎞⎜⎜⎝
⎛
+⎟⎟⎠
⎞⎜⎜⎝
⎛⎟⎟⎠
⎞⎜⎜⎝
⎛ −−−−⎟⎟
⎠
⎞⎜⎜⎝
⎛ −−
=Ε
t
subba
t
ba
t
suba
t
dsubb
t
db
t
subd
t
subb
t
bc
t
gapsubb
t
gapbv
tsurf
VE
EVN
EV
EVN
VFFN
EVF
EFN
q
φφ
φφ
φ
φφ
φφ
φ
φφ
φφ
π
φφ
φφ
π
εφ
c
c
c
c
2323
2323
2
Eexp41
Eexp41ln
Eexp21
Eexp21ln
34
34
2
Slide No. 22
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 22Slide No. 22 22
MOS Band Diagrams
Device Electronics for Integrated Circuits, by Richard S. Muller and Theodore I. Kamins, John Wiley & Sons. Inc.
Slide No. 23
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 23Slide No. 23 23
MOS Band Diagrams
Device Electronics for Integrated Circuits, by Richard S. Muller and Theodore I. Kamins, John Wiley & Sons. Inc.
Slide No. 24
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 24Slide No. 24 24
Regions of Operation
• Accumulation occurs when the Ef is near the valence band.• Inversion occurs when the Ef is near the conduction band.
Vg
-4 -3 -2 -1 0 1 2 3 4
Qsu
b
-4e-6
-3e-6
-2e-6
-1e-6
0
1e-6
2e-6
3e-6
Inversion
Depletion
Accumulation
Vg
-4 -3 -2 -1 0 1 2 3 4
Vsu
b
-0.4-0.20.00.20.40.60.81.01.21.4
Inversion
Depletion
Accumulation
Ef-Ec=-Egap+nkT/q
Ef-Ec=-nkT/q
Slide No. 25
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 25Slide No. 25 25
Common Approximations
• Qinv = Cox (Vg-Vt)
• Qacc = Cox (Vg-Vfb)
Vg
-4 -3 -2 -1 0 1 2 3 4
Qsu
b
-4e-6
-3e-6
-2e-6
-1e-6
0
1e-6
2e-6
3e-6
Inversion
Depletion
Accumulation
Qacc
Qinv
2dep s a subQ q N Vε=
Slide No. 26
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 26Slide No. 26 26
Quasi-static vs. Deep Depletion
• The previous analysis assumes minority carrier generation can keep up with the dc bias (quasi-static).• However, deep depletion is typically seen for MOS capacitors with ultra-thin oxides.
Vg
-4 -3 -2 -1 0 1 2 3 4
Vsu
b
-1
0
1
2
3
4
Quasi-staticDeep Depletion
Vg
-4 -3 -2 -1 0 1 2 3 4V
ox
-3
-2
-1
0
1
2
3
Quasi-staticDeep Depletion
Slide No. 27
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 27Slide No. 27 27
Calculating Capacitance
Total Device Capacitance:
Substrate/Poly Capacitance:
( )( ) 1111 −−−− ++= oxpolysubtot CCCC
( )( )
( )polysub
polysubpolysub dV
dQC =
Slide No. 28
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 28Slide No. 28 28
Calculating Capacitance
Device Electronics for Integrated Circuits, by Richard S. Muller and Theodore I. Kamins, John Wiley & Sons. Inc.
Slide No. 29
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 29Slide No. 29 29
Typical C-V Characteristics
Vg (V)-4 -3 -2 -1 0 1 2 3 4
C (μ
F/cm
2 )
0.0
0.2
0.4
0.6
0.8
1.0
1.2
LFHFDD
Nsub = 1017 cm-3
Vg (V)-4 -3 -2 -1 0 1 2 3 4
C (μ
F/cm
2 )
0.0
0.2
0.4
0.6
0.8
1.0
1.2
LFHFDD
Nsub = 6x1014 cm-3
• High frequency means that carriers can respond to the dc signal but not the ac signal• Low Frequency means that carriers can respond to the dc and ac signals.• Deep-depletion means that the carriers cannot respond to either the dc or ac signals.
Slide No. 30
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 30Slide No. 30 30
Quantum Mechanical Effects
• The splitting of energy levels and the shifting of the carriers away from the interface leads to a decrease of the inversion layer or accumulation layer charge density as a function of the surface potential as compared to classical simulation.
• van Dort et al. pursued a more computationally efficient approach of modeling these effects via an increase in the effective bandgap of silicon.
S. A. Hareland et al., IEEE TED, vol. 45, p. 1487 (1998)
( ) 3231
8
41092.5 s
sig kTq
E Ε⎟⎠
⎞⎜⎝
⎛×=Δ − ε
Slide No. 31
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 31Slide No. 31 31
Quantum Mechanical Effects
• Quantum Mechanical Effects result in a drop of the maximum capacitance and a slight shift of the threshold voltage.
Vg (V)-4 -3 -2 -1 0 1 2 3 4
C (μ
F/cm
2 )
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5Classical
Metal GateTox = 1.0 nmNsub = 2x1017cm-3
QM
MB
Slide No. 32
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 32Slide No. 32 32
Density of States Effects
-10 -5 0 5 101015
1016
1017
1018
1019
1020
1021
1022
1023
Si GaAsEl
ectr
on C
once
ntat
ion
(n/c
m3 )
η (EF-EC) in units of KT
Open Circle: Maxwell-BoltzmannSolid Lines: Fermi-Dirac
⎟⎟⎠
⎞⎜⎜⎝
⎛ −≈⎟⎟
⎠
⎞⎜⎜⎝
⎛ −=
kTEE
NkT
EEFNn cf
ccf
c exp21
Slide No. 33
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 33Slide No. 33 33
Density of States Effects
NCSU : In-House : Schred :
0.0
0.5
1.0
1.5
Cap
acita
nce
(μF/
cm2 )
Bias (V)3210-1-3 -2
FD
MB
C.A. Richter, E.M. Vogel, A.M. Hodge, and A.R. Hefner. Simulation of Semiconductor Processes and Devices 2001, Dimitri Tsoukalas and Christos Tsamis eds., (SpringerWienNewYork 2001) pp. 340-343.
• This result shows that classicalsimulations are strongly affectedby the carrier statistics used:Maxwell-Boltzmann (MB) vs.Fermi-Dirac (FD).
• In general, the density of states in inversion or accumulation can strongly affect the maximum capacitance.
Slide No. 34
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 34Slide No. 34 34
Density of States Effects
• The asymmetry of the effective density of states for holes and electrons in III-V, causes a strong asymmetry in the modeled C-V characteristics.
Nc = 2.1x1017 cm-3
Nv = 7.7x1018 cm-3
Slide No. 35
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 35Slide No. 35 35
In.53Ga.47As Band Structure
mΓ = 0.041mL = 0.29mX = 0.68
In53Ga47As
Density of States Effects
• The low density of states for III-V causes heavily degenerate Fermi levels.
Slide No. 36
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 36Slide No. 36 36
In.53Ga.47As Band Structure
mΓ = 0.041mL = 0.29mX = 0.68
In53Ga47As
Density of States Effects
• The low density of states for III-V causes heavily degenerate Fermi levels.
Slide No. 37
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 37Slide No. 37 37
Density of States Effects
Fully Ionized
Deionized
In53Ga47As
( )( )kTEEgNN
dfd
dd −+
=+
exp1
value)(standard 2=dg
1 2f c
c d
E En N F N
kT+−⎛ ⎞
= =⎜ ⎟⎝ ⎠
• The low density of states for III-V causes heavy dopant deionization.
Slide No. 38
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 38Slide No. 38 38
C-V Parameter Extraction
• Methodology• Oxide Thickness• Substrate Doping• Polysilicon Doping• Flatband Voltage• Oxide Charge and Workfunction
Slide No. 39
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 39Slide No. 39 39
Parameter Extraction using Modeling
• NCSU CVC program fits experimental C-V data using a model that has the following parameters: Vfb, Tox, Nsub, Npoly
• NCSU CVC does not include interface states.
Vg (V)-4 -3 -2 -1 0 1 2 3
C (μ
F/cm
2 )
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
MeasuredModeled
Vfb = -0.987 VTox = 2.01 nmNsub = 2.97x1017 cm-3
Npoly = 1.61x1020 cm-3
Slide No. 40
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 40Slide No. 40 40
Impact of Simulation Code
• Simulators show a difference of up to 20% in the calculated accumulation capacitance.
• Possible reasons include: the use of approximations for quantum effects vs. Schrödinger equation, wave function boundary conditions, and type of carrier statistics.
Vg (V)-3 -2 -1 0 1 2 3
C ( μ
F/cm
2 )
0.00
0.25
0.50
0.75
1.00
1.25
1.50
UTQuant [30]NIST Schred [32]NCSU [25]NEMO [29]Berkeley [31]
Tox = 2.0 nmNsub = 1018 cm-3
Npoly = 1020 cm-3
n-channel, n-poly gate
Slide No. 41
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 41Slide No. 41 41
Oxide Thickness Definitions
• The Equivalent Oxide Thickness (EOT) is obtained from the gate dielectric capacitance alone.
• EOT must be determined from C-V measurements using a fitting or extraction algorithm which includes QM effects, polysilicon depletion, etc.
• The Capacitance Equivalent Thickness (CET) is determined by simply taking the ∈SiO2xArea/Cmeas where Cmeas is the measured capacitance in inversion or accumulation at some defined voltage.
Slide No. 42
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 42Slide No. 42 42
Oxide Thickness Definitions
• EOT is the thickness of SiO2 which would produce the same capacitance as that obtained from a high-K dielectric.
• In order to achieve a small EOT, the interfacial thickness must be controlled.
Physical Thickness of High-κ Dielectric (nm)
0 1 2 3 4 5
EOT
(nm
)
0.0
0.5
1.0
1.5
2.0
T(SiO2) = 1 nm, k(High-k) = 20T(SiO2) = 1 nm, k(High-k) = 40T(SiO2) = 0.5 nm, k(High-k) = 20T(SiO2) = 0.5 nm, k(High-k) = 40
Slide No. 43
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 43Slide No. 43 43
Thickness Extraction
• The maximum capacitance in accumulation is close to Cox.
• The minimum capacitance is due to the substrate capacitance.
Vg (V)-4 -3 -2 -1 0 1 2 3 4
C (μ
F/cm
2 )
0
2
4
6
8
10
12
14Ctot
Csub
Cox
( )( ) 1111 −−−− ++= oxpolysubtot CCCC
Slide No. 44
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 44Slide No. 44 44
Thickness Extraction
• The capacitance in accumulation (represented here by CET) is not strongly impacted by the substrate or polysilicon doping.
• The CET does depend strongly on whether the gate is metal or polysilicon. Nsub (cm-3)
1015 1016 1017 1018 1019C
ET (n
m)
1.40
1.45
1.50
1.55
1.60
1.65
1.70
1.75
Npoly = 1019 cm-3
Npoly = 1020 cm-3
Metal
EOT = 1.0 nmN-channel DeviceVg = -2 V
Slide No. 45
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 45Slide No. 45 45
Substrate Doping Extraction
• The substrate doping strongly impacts the minimum capacitance but does not strongly impact the maximum capacitance in accumulation.
• The minimum capacitance can be used to determine substrate doping. Vg (V)
-4 -3 -2 -1 0 1 2 3 4C
(μF/
cm2 )
0.0
0.2
0.4
0.6
0.8
1.0
1.2
Nsub = 1017 cm-3
Nsub = 6x1014 cm-3
Slide No. 46
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 46Slide No. 46 46
Substrate Doping Extraction
⎟⎟⎠
⎞⎜⎜⎝
⎛−=
oxs CC
W 11ε
Vg (V)-4 -3 -2 -1 0 1 2 3 4
C (μ
F/cm
2 )
0.0
0.2
0.4
0.6
0.8
1.0
1.2
LFHFDD
Nsub = 1017 cm-3
• The MOS capacitor must be in deep depletion to apply this technique.• This can be done using a rapidly varying dc ramp or pulsed gate voltage.
( ) ( ) dVCdqdVdCqCWp
ss2
3
12
εε=−=
Slide No. 47
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 47Slide No. 47 47
Substrate Doping Extraction
subox
subox
CCCCC+
=
a
invssinv qN
WW ,22 φε==
• Valid for uniformly doped samples.
( )2
22
14
RCR
qN ox
s
fa −
=εφ
ox
inv
CCR =
Slide No. 48
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 48Slide No. 48 48
Polysilicon Doping Extraction
• The depletion of polysilicon results in a large drop of the capacitance.
• The capacitance in inversion can be used to determine polysilicon doping.
Vg (V)-4 -3 -2 -1 0 1 2 3 4
C (μ
F/cm
2 )
0.0
0.5
1.0
1.5
2.0
2.5
3.0Metal
Poly=1020 cm-3
Tox = 1.0 nmNsub = 2x1017cm-3
Poly=5x1019 cm-3
Slide No. 49
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 49Slide No. 49 49
Flatband Voltage Extraction
• If the oxide capacitance and substrate doping is known, the flatband capacitance (and hence Vfb) can be found.
• There are numerous sources of possible error with this technique.
Tox (nm)10-1 100 101
Cfb
/Cox
10-3
10-2
10-1
100
N a = 1014 cm
-31015
1016
1017
1018
Slide No. 50
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 50Slide No. 50 50
Workfunction and Oxide Charge Extraction
ox ox oxfb ms ms
ox ox
Q t QVC
ϕ ϕε
= − = −
Slide No. 51
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 51Slide No. 51 51
Workfunction and Oxide Charge Extraction
( )
( ) ( ) ⎥⎦
⎤⎢⎣
⎡+−=
⎥⎦
⎤⎢⎣
⎡−=
∫∫
∫EOT
EOTbulkf
EOT
oxmsfb
EOT
oxmsfb
dxxxdxxxV
dxxxV
12
1
0
0
1
1
ρρε
φ
ρε
φ
For a stacked dielectric
Slide No. 52
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 52Slide No. 52 52
Workfunction and Oxide Charge Extraction
⎥⎦⎤
⎢⎣⎡−= 2
1211 EOTV bulkf
oxmsfb ρ
εφ
( )[ ]EOTEOTQQ bulkfbulkfffffox
221int2int11 ρρ
ε−−+−
( ) 2int1221211 EOTQEOT ffbulkfbulkf
ox⎥⎦⎤
⎢⎣⎡ −−− ρρ
εFor a SiO2/high-k stack where EOT1(2) is the EOT of the high-k (SiO2), Qf1(2)int are the charges at the high-k/SiO2 (SiO2/Si) interface, ρf1(2)bulk are charges uniformly distributed within the high-k (SiO2).
R. Jha, et al., IEEE EDL 25, 420 (2004)( )0
1 EOT
fb msox
V x x dxϕ ρε
⎡ ⎤= − ⎢ ⎥
⎣ ⎦∫
Slide No. 53
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 53Slide No. 53 53
Workfunction and Oxide Charge Extraction
[ ] [ ]EOTQEOTQV ffox
ffox
msfb int21int111
εεφ +−=
If interface charges dominate bulk charges:R. Jha, et al., IEEE EDL 25, 420 (2004)
The intercepts and slopes of Vfb vs. EOT with varying EOT1and EOT2 can provide Φms, Qf1intf, and Qf2intf.
[ ] [ ]2int1int2int111 EOTQEOTQQV ffox
ffffox
msfb εεφ ++−=
Slide No. 54
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 54Slide No. 54 54
Workfunction and Oxide Charge Extraction
R. Jha, et al., IEEE EDL 25, 420 (2004)
• Set I: THfO2 = 4.5 nm, TSiO2 = 1, 2, 4 nm• Set II: THfO2 = 3, 4.5, 6 nm, TSiO2 = 2 nm• Set III: THfO2 = 0 nm, TSiO2 = 2, 4, 6 nm
Slide No. 55
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 55Slide No. 55 55
Effective Workfunction
• The vacuum work function of a metal does not necessarily equal the effective work function of the metal due to charge transfer, defects, and dipoles.
Slide No. 56
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 56Slide No. 56 56
C-V Including Interface States
• Theory• Interface State Capacitance• Interface State Density “Extraction”
Slide No. 57
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 57Slide No. 57 57
Including Interface States
• Qit is charge in the oxide that changes occupancy with bias.• Dita(d) is the density of acceptor(donor)-like interface states
( )( ) ( ) ( )( )( ) ( ) ( )( ) t
E
E ifitsdititd
ifitsaititasubit dE
EEEEFEEqD
EEEEFEEqDVQ
c
v
∫ ⎥⎦
⎤⎢⎣
⎡−−−−+
−−−−−=
( ) ( ) 1
exp25.01−
⎟⎟⎠
⎞⎜⎜⎝
⎛⎟⎟⎠
⎞⎜⎜⎝
⎛ −+=−
t
ftftsa
EEEEF
φ( ) ( ) 1
exp21−
⎟⎟⎠
⎞⎜⎜⎝
⎛⎟⎟⎠
⎞⎜⎜⎝
⎛ −−+=−
t
ftftsd
EEEEF
φ
( ) ( ) ( ) 0=+++ oxsubitpolypolysubsub QVQVQVQ
( )ox
subit
ox
subfbpolysubg C
VQCQVVVV −−+−=
Slide No. 58
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 58Slide No. 58 58
Interface State Capacitance
• At very high frequencies (infinite), interface states do not respond to the ac signal.
• At very low frequencies (quasi-static), interface states respond to the ac signal over the entire bias range resulting in a capacitance.
sub
itditaQSit V
QQCΔ
Δ+Δ=,( )( ) 1111 −−−− +++= oxpolysubittot CCCCC
Vg (V)-3 -2 -1 0 1 2 3
Cap
acita
nce
( μF/
cm2 )
0.05
0.10
0.15
0.20
0.25
0.30
0.35
Ideal HFHF with Dit
QS with Dit
Tox = 10 nmDit = 1012 cm-2eV-1
Slide No. 59
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 59Slide No. 59 59
Interface State Capacitance
• At intermediate frequencies, SRH theory must be used including the effect of surface potential variation across the interfacial plane.•P(Vs) is the probability that the band bending is Vs, ps is the free carrier concentration.
( ) ( )
( )
section cross capture
tan
p
1
1
=≡
=
=
−
∞
∞−
−∫
th
p
spp
sspp
itit
vc
pc
dVVPqDC
σ
τ
ωτωτ
Vg (V)-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0
Cap
acita
nce
( μF/
cm2 )
0.0
0.5
1.0
1.5
2.0
2.5
FETCap (102 Hz)Cap (103 Hz)Cap (104 Hz)Cap (105 Hz)Cap (106 Hz)
Tox = 1.0 nmDit = 1012 cm-2eV-1
Slide No. 60
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 60Slide No. 60 60
Dit Extraction
• Some have attempted extracting Dit from the “hump” observed in C-V using a quasi-static approach.
• Proper modeling requires including the interface state capacitance as a function of frequency.
Gate Voltage (V)
-2.0 -1.5 -1.0 -0.5 0.0
Cap
acita
nce
( μF/
cm2 )
0
1
2
3
4
Exp. Data (105 Hz)Simulation: 105 Hz (Dit profile 1)σs = 4 (kT/q)σp = 10-14 cm2
Simulation: Quasi-static (Dit profile 2)Simulation: No Dit
EOT = 0.62 nmNsub = 4x1017 cm-3
Et - Ei (eV)
-1.0 -0.5 0.0 0.5 1.0
Dit (
x1012
cm
-2eV
-1)
0
2
4
6
8
10
profile 1profile 2
Slide No. 61
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 61Slide No. 61 61
Dit Extraction on Thick Oxides
Vg (V)-3 -2 -1 0 1 2 3
Cap
acita
nce
( μF/
cm2 )
0.05
0.10
0.15
0.20
0.25
0.30
0.35
Ideal HFHF with Dit
QS with Dit
Tox = 10 nmDit = 1012 cm-2eV-1
1) Low-High Frequency: A quasi-static (QS) and a high-frequency (HF) CV curve is measured and interface state capacitance is determined.
2) Terman: A HF CV curve ismeasured and compared to a theoretical ideal (no Dit) CV curve to obtain the amount of voltage stretch-out.
Slide No. 62
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 62Slide No. 62 62
Dit Extraction on Thin Dielectrics
1) Low-High Frequency: Quasi-static measurements cannot be performed on advanced dielectrics due to leakage current
2) Terman: With decreasing EOT (increasing dielectric capacitance), the voltage shift (Qit/Cox) due to charging of traps (stretch-out)becomes smaller. EOT (nm)
0 2 4 6 8 10 12
ΔV (V
)
10-4
10-3
10-2
10-1
100
Nit = 1010 cm-2
Nit = 1011 cm-2
Nit = 1012 cm-2
Slide No. 63
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 63Slide No. 63 63
Dit Extraction
• Dit can be extracted by properly modeling the frequency dependence of the interface state capacitance.
• However the number of parameters that can provide a reasonable fit is large.
Gate Voltage (V)
-2.0 -1.5 -1.0 -0.5 0.0
Cap
acita
nce
( μF/
cm2 )
0
1
2
3
4
σs = 4 (kT/q), σp = 10-14 cm2
σs = 1 (kT/q), σp = 10-14 cm2
σs = 4 (kT/q), σp = 10-17 cm2
Nsub = 4x1017 cm-3
EOT = 0.62 nmDit profile 1F = 105 Hz
Slide No. 64
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 64Slide No. 64 64
Interface States on III-V
~10 nm Al2O3 on GaAs~10 nm Al2O3 +
~1 nm PECVD a-Si on GaAs
• It has typically been assumed that dispersion in the maximum capacitance is due to a high interface state density and associated Fermi level pinning.
• Dispersion on n-type is typically worse than on p-type.
• Silicon and other interlayers have mitigated this effect, although the use of an interlayer is likely not scalable.
Slide No. 65
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 65Slide No. 65 65
These effects are well documented• It has typically been assumed that dispersion in the maximum capacitance is due to a high interface state density and associated Fermi level pinning.
• Dispersion on n-type is typically worse than on p-type.
• Silicon and other interlayers have mitigated this effect, although the use of an interlayer is likely not scalable.
H. Hasegawa and T. Sawada, IEEE Trans. Elec. Dev. ED-27, 1055-1061 (1980).
S. Koveshnikov, et al., APL 88, 022106 (2006)
Slide No. 66
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 66Slide No. 66 66
Interface State Capacitance
Cox
CS
Gate
Oxide
Semiconductor
Cit Gp
( ) 111)( −−− ++= oxitstot CCCC
• The interface state capacitance is in parallel with the substrate capacitance.
• The total capacitance is dominated by the interface state capacitance.
• The appearance of maximum capacitance at low frequency does not imply the presence of free carriers.
-2 -1 0 1 2 30.1
0.2
0.3
0.4
0.5
0.6
0.7
100Hz 1kHz 10kHz 100kHz 1MHz
C/A
(μF/
cm2 )
Vg (Volts)
Slide No. 67
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 67Slide No. 67 67
Nicollian and Brews Interface State Model
( ) ( ) ( ) ( )( ) ssApss
ss
p
itit dNcqDC υυωυ
συυ
ωτexptanexp
2exp 11
2
2−−
∞
∞−
−⎥⎥⎦
⎤
⎢⎢⎣
⎡ −−= ∫
( ) 1−= spp pcτ pth
p
vc
≡σ
The Nicollian and Brews model for interface state capacitance cannot fit the experimental data.
Interface State Capacitance – N&B
Slide No. 68
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 68Slide No. 68 68
H. Hasegawa and T. Sawada, IEEE Trans. Elec. Dev. ED-27, 1055-1061 (1980).
Hasegawa and Sawada have previously shown that the frequency dispersion behavior of GaAs MOS capacitors cannot be explained by the Nicollian and Brews model.
Nicollian and Brews Interface State Model
( ) ( ) ( ) ( )( ) ssApss
ss
p
itit dNcqDC υυωυ
συυ
ωτexptanexp
2exp 11
2
2−−
∞
∞−
−⎥⎥⎦
⎤
⎢⎢⎣
⎡ −−= ∫
( ) 1−= spp pcτ p
th
p
vc
≡σ
Interface State Capacitance – N&B
Slide No. 69
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 69Slide No. 69 69
Hasegawa and Sawada Model
Hasegawa and Sawada proposed a model in which carriers can transport into a lossy, highly defective interfacial region.
The defect density is assumed exponentially distributed into the depth of the interfacial region, although the exact distribution is not critical.
The trapping time constant is assumed exponentially dependent on depth.
( )( ) ( ) ( )dzzzNqC Tit
11
0
220
0
02
tan2
0
00 −∫=ωτ
κακαωτκ
( ) ( )xx 00 2exp κττ = ( ) 10
−= sp pcτ pth
p
vc
≡σ( )xNN TT α−= exp0
-2 -1 0 1 2 30.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Cap
acita
nce
(μF/
cm2 )
VG (V)
100 Hz 1 kHz 10 kHz 100 kHz 1 MHz
nm 2.010 =−κ
nm 0.51 =−α
n-type GaAs
E. M. Vogel, A. M. Sonnet, and C. L. Hinkle. “Characterization of electrically active interfacial defects in high-κ gate dielectrics., ECS Transactions 11, 393 (2007).
Interface State Capacitance – H&S
Slide No. 70
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 70Slide No. 70 70
Hasegawa and Sawada Model
The difference in dispersion between n-type and p-type is simply related to the difference in time constant for electrons and holes associated with the large difference between effective density of states.
( )( ) ( ) ( )dzzzNqC Tit
11
0
220
0
02
tan2
0
00 −∫=ωτ
κακαωτκ
( ) ( )xx 00 2exp κττ =
( ) 1−= spp pcτ
( )xNN TT α−= exp0
Nc (GaAs) = 4.2x1017 cm-3
Nv (GaAs) = 1.2x1019 cm-3
( ) 1−= spn ncτ -3 -2 -1 0 1 20.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Cap
acita
nce
(μF/
cm2 )
VG (V)
100 Hz 1 kHz 10 kHz 100 kHz 1 MHz
See: Hinkle, et al., APL 93 (2008) 113506
Interface State Capacitance – H&S
Slide No. 71
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 71Slide No. 71 71
Summary: Capacitance-Voltage
• C-V is one of the most widely used techniques to extract parameters (EOT, Nsub, Npoly, Qox, Dit) from MOS devices.• The presence of high leakage strongly impacts the measurement of capacitance.• Classical MOS capacitor equations and parameter extraction methodologies must be modified to include quantum mechanical and polysilicon depletion effects.• Metal gate electrodes, high-k gate dielectrics, and non-silicon devices also change parameter extraction.
Slide No. 72
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 72Slide No. 72 72
MOSFET Parameter Extraction
• Measurement Conditions• Threshold Voltage • Subthreshold Slope• Effective Mobility• Drain Induced Barrier Lowering• Series Resistance and Effective Channel Length/Width
Slide No. 73
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 73Slide No. 73 73
Measurement Conditions
SMU
S D
G
SMUSMU
SMU
Slide No. 74
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 74Slide No. 74 74
MOSFET Band Diagram
Device Electronics for Integrated Circuits, by Richard S. Muller and Theodore I. Kamins, John Wiley & Sons. Inc.
Slide No. 75
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 75Slide No. 75 75
MOSFET Approximations
Device Electronics for Integrated Circuits, by Richard S. Muller and Theodore I. Kamins, John Wiley & Sons. Inc.
ds eff inv dsWI Q VL
μ=
0 0
ds dsV V
ds inv eff invW WI Q d Q dL L
μ φ μ φ= =∫ ∫
( )ds eff ox g t dsWI C V V VL
μ= −
( )2
, 2ds sat eff ox g tWI C V V
Lμ= −
Linear:
Linear Approx.:
Sat. Approx.:
Slide No. 76
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 76Slide No. 76 76
Threshold Voltage
LogI
ds(A)
Vgs
(V)0
Constant Current VT
VT
IT
WL
Constant-Current Method• A linear Ids-Vgs characteristic is measured with Vgs = Vdd and Vdsat a low voltage (< 0.1 V).• The threshold voltage (Vt) is defined based on a specialized drain current Ids = It (W/L).• It = 10-7 A is typically used.
+ This method is very fast and is often used in process monitoring.- Depends on a variety of parameters (e.g. subthreshold slope)
Slide No. 77
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 77Slide No. 77 77
Threshold Voltage
Linear Extrapolation Method• A linear Ids-Vgs characteristic is measured with Vgs = Vdd and Vdsat a low voltage (< 0.1 V).• The extrapolated threshold voltage (Vte) is defined as the gate voltage obtained by extrapolating the linear portion of the Ids-Vgs, from maximum slope to zero drain current.
Linear I ds (A)
V gs (V)
Peak g m
Linear l i0 V TE
gm(1/Ω)
+ Less dependent on other parameters (e.g. degraded mobility)- Not valid for high series resistance.
Slide No. 78
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 78Slide No. 78 78
Threshold Voltage
Saturation Threshold Method• A saturation Ids-Vgs characteristic is measured with Vgs = Vddand high Vds (Vdd).• The saturation threshold voltage (Vtsat) is defined as the gate voltage obtained by extrapolating the SQRT(Ids) -Vgs, from maximum slope to zero drain current.
+ This method is important from a circuit perspective since the threshold voltage can depend on drain bias due to short channel effects.
Slide No. 79
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 79Slide No. 79 79
Subthreshold Swing
( )1 exp 1 expgs T ds
D D
q V V qVI InkT kT
⎛ ⎞− ⎛ ⎞−⎛ ⎞⎜ ⎟= −⎜ ⎟⎜ ⎟⎜ ⎟ ⎝ ⎠⎝ ⎠⎝ ⎠
( )ox
itd
CCC
1n+
+=
• The drain current of a MOSFET below threshold voltage can be written as:
[ ] decade/mV 300Tn60
qnkT)10ln(S ⎟
⎠⎞
⎜⎝⎛≈=
Slide No. 80
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 80Slide No. 80 80
Mobility
( )inv ox gs tQ C V V→ −
dsds eff inv
ds
I Wg QV L
μ= =
In the linear regime.
• At large Vgs > Vt:
dsm fe ox ds
gs
dI Wg C VdV L
μ= =
Effective Silicon Surface Field:
( )
( )
( )
1
1 10021 , 110 , 1113
eff inv bSi
E Q Q
electrons
holes electrons
ηε
η
η
= +
= < >
= < > < >
Effective Mobility
Field Effect Mobility
• At low Vgs < Vt: ( )expinv gs tQ V V∝ −
J. R. Hauser, IEEE Trans. Elec. Dev. 38, 1981-1988 (1996).
Slide No. 81
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 81Slide No. 81 81
Mobility
• The field effect mobility does not include the dependence of mobility on gate voltage.
Effective Field (MV/cm)0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
Mob
ility
(cm
2 /Vs)
0
100
200
300
400
500Field EffectEffective
Slide No. 82
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 82Slide No. 82 82
Split C-V
dsds eff inv
ds
I Wg QV L
μ= =
gsV
inv gc gsQ C dV−∞
= ∫
0 10 0
2 10 -15
4 10 -15
6 10 -15
8 10 -15
1 10 -14
-4 -3 -2 -1 0 1 2 3 4
C gc
(F)
V gs
(V)
L m
=4 μ m
L m
=2 μ m
L m
=1 μ m
C ov
L m
=0.8 μ m
• The gate to channel (source-drain) capacitance can be measured to determine the inversion charge density.
Slide No. 83
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 83Slide No. 83 83
Effective Mobility
Effective Field (MV/cm)
0.5 1.0 1.5 2.0 2.5 3.0
Mob
ility
(cm
2 /Vs)
101
102
103
104
105
106
Total Mobility
Dopant (Coulombic)
Surface Roughness
Fixed Charge (Coulombic)
Phonon
Components of surface scattering:1) Phonon 2) Coulombic due to dopants3) Coulombic due to oxide charge4) Surface roughness
1 1 1 1 1
eff ph c if srμ μ μ μ μ= + + +
Mathiesson’s Rule:
Slide No. 84
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 84Slide No. 84 84
Effective Mobility
• Simple models have been developed to describe the 4 components of mobility.
• The only adjustable parameters in these models are the substrate doping, oxide charge scattering parameter, and surface roughness parameter.
Effective Field (MV/cm)0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Mob
ility
(cm
2 /Vs)
0
100
200
300
400
500
1017, 3x1010, 241017, 6x1010, 241017, 3x1010, 321018, 3x1010, 24
Nsub, Nif, SRcm-3, cm-2, Å2
J. R. Hauser, IEEE Trans. Elec. Dev. 38, 1981-1988 (1996).
Slide No. 85
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 85Slide No. 85 85
Short Channel Effects
Drain Induced Barrier Lowering (DIBL):• In short channel devices, the
depletion of the drain has a larger impact on the channel charge.
• The threshold voltage of the device decreases as a function of channel length.
Slide No. 86
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 86Slide No. 86 86
Series Resistance and Effective Channel Length
D. K. Schroeder, in Semiconductor Material and Device Characterization, Wiley-Interscience: 1990.
• The source and drain series resistance consists of the source/drain contact resistance, the sheet resistance of the source/drain, spreading resistance at the transition from the source diffusion to the channel, and any additional resistance associated with probes and wiring.
• The effective channel length and width differ from the drawn channel length and width.
• These properties are frequently determined with one technique
Slide No. 87
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 87Slide No. 87 87
Series Resistance and Effective Channel Length
( )dsdsTgsoxeff
ds V)V5.0VV(L
WCI ′′−−′=
μ
Sdsgsgs RIVV +′=
( )ds ds ds S DV V I R R′= + +
( )( ) SDTgsoxeffm
dsTgsoxeffds RVVCWLL
VVVWCI
−+Δ−
−=
μμ
)(
SDchds
dsm RR
IV
R +==
)( Tgsoxch VVWC
LR−
≈μ
Some Equations
Slide No. 88
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 88Slide No. 88 88
Series Resistance and Effective Channel Length
Channel Resistance Method• RSD should be independent of
the external bias• A should be independent of
channel length.
0
200
400
600
800
1000
1200
0 0.5 1 1.5 2 2.5 3 3.5 4
L m(μm)
R SD
R m (Ω)
V gs
=2V V gs
=3V V gs
=4V
LΔ
BLAR mm +⋅=
LARB SD Δ⋅−=
)(1
Tgsox VVWCA
−=
μ
Slide No. 89
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 89Slide No. 89 89
FET Measurement Issues with High-k
Y. Zhao, C. D Young, R. Choi, and B. H. Lee, “Pulsed Characterization of Charge-Trapping Behavior in High κ Gate Dielectrics,” A Keithley White Paper, www.keithley.com
• High-k dielectrics typically exhibit trapping which affects Id-Vg measurements.• A pulsed Id-Vg measurement can be used to eliminate the effect of trapping on the measured Id-Vg.
Slide No. 90
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 90Slide No. 90 90
FET Measurement Issues with High-k
Y. Zhao, C. D Young, R. Choi, and B. H. Lee, “Pulsed Characterization of Charge-Trapping Behavior in High κ Gate Dielectrics,” A Keithley White Paper, www.keithley.com
• High-k dielectrics typically exhibit trapping which affects Id-Vg measurements.• A pulsed Id-Vg measurement can be used to eliminate the effect of trapping on the measured Id-Vg.
Slide No. 91
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 91Slide No. 91 91
Example: In0.53Ga0.47As MOSFETs
g Much higher drive current is achieved using Si interlayer.g Effect is much greater for In0.20Ga0.80As (x103) as compared to In0.53Ga0.47As (x2).g Drive current is much higher in In0.53Ga0.47As compared to In0.20Ga0.80As.
A. M. Sonnet, C. L. Hinkle, M. N. Jivani, R. A. Chapman, G. P. Pollack, R. M. Wallace, and E. M. Vogel, “Performance enhancement of n-channel inversion type InxGa1-xAs metal-oxide-semiconductor field effect transistor using ex situ deposited thin amorphous silicon layer”, Applied Physics Letters 93, 122109 (2008).
P.D.Ye, et al., IEEE EDL 28 (2007) 935
Closed symbols: With Si interlayer
Open symbols: Without Si interlayer
Slide No. 92
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 92Slide No. 92 92
Split C-V on In0.53Ga0.47As MOSFETs
• Qinv is overestimated due to interface state capacitance.
• Split C-V was used to estimate the inversion charge density for calculation of the effective channel mobility.
• A large interface state capacitance is found.
• In the literature, similar C-V behavior on n-type MOS capacitors is many times misidentified as inversion response.
Slide No. 93
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 93Slide No. 93 93
-4 -2 0 2 4
10
20
30
40
-4 -2 0 2 40
10
20
30
40
-4 -2 0 2 40
10
20
30
40
-4 -2 0 2 402468
101214
0
1
2
3
4
5
10 K 100 K 1 MHz
Cap
acita
nce
(pF)
VG (V)
Area: 1.0X10-4cm-2
Split C-V: W/L=100 μm/100 μm, With Si
In0.53Ga0.47As
(a) 295 K
Area: 1.0X10-4cm-2
295 K 190 K 77 K
(b) 1 MHz
I d (mA
/mm
)
VG (V)
In0.53Ga0.47As
(c) 77 K
10 kHz 100 kHz 1 MHz
Cap
acita
nce
(pF)
VG (V)
Area: 1.0X10-4cm-2
In0.53Ga0.47As
Cap
acita
nce
(pF)
VG (V)
W/L = 50μm/2μm
In0.53Ga0.47As(d) 295 K
gm (m
S/m
m)
Freeze-out of interface traps
• Reducing the temperature lowers the trap time constant effectively “freezing out” the Cit caused by the ac signal response.
• There is still a stretch out of the C-V curve compared to a theoretical curve (no Dit) due to the traps causing a change in the surface potential.
Split C-V on In0.53Ga0.47As MOSFETs
Slide No. 94
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 94Slide No. 94 94
• Experimental low temperature (77K) split C-V was modeled with a III-V semiconductor C-V simulator developed at UT-Dallas.
• The corresponding parameters were used to model room temperature (295K) split C-V excluding the Ditresponse.
• The corrected mobility increases ~3600 cm2/Vs.
Mobility extraction corrected for Dit responseCorrected Mobility of InGaAs FETs
C. L. Hinkle, A. M. Sonnet, R. A. Chapman, and E. M. Vogel, IEEE Elec. Dev. Lett. 30, 316-318 (2009)
Slide No. 95
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 95Slide No. 95 95
Summary: MOSFET Parameter Extraction
• MOSFET transfer characteristics can be used to extract a variety of parameters (threshold voltage, channel mobility, series resistance, and effective channel length and width.
• The primary issue with characterizing high-k gate dielectrics is that trapping impacts the true channel mobility.
Slide No. 96
WMED Tutorial April 3, 2009Eric M. Vogel “Electrical Characterization of Advanced MOS Devices” 96Slide No. 96 96
THANK YOU!!!