Electric Vehicle Warning Sound System User Guide...One Technology Way • P.O. Box 9106 • Norwood,...

Electric Vehicle Warning Sound System User GuideUG-1305

One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com

Electric Vehicle Warning Sound System User Guide

PLEASE SEE THE LAST PAGE FOR AN IMPORTANT WARNING AND LEGAL TERMS AND CONDITIONS. Rev. 0 | of 21

FEATURES ADSP-BF706 Blackfin processor

88-lead QFN package 24.576 MHz input clock (CLKIN) oscillator

Quad SPI 256 Mb serial flash memory

USB to UART interface bridge Controller area network Debug interface

JTAG header for use with Analog Devices, Inc., emulators Four LEDs

One power (green), one board reset (red), one hardware fault (red), and one general-purpose (yellow)

Two push-buttons One reset and one IRQ/flag

Class A/B audio power amplifier High efficiency, digital input, automotive quad power amplifier with built in diagnostics features Single, 12 V power supply with 42 V quad, monolithic, synchronous step-down regulator

EVALUATION KIT CONTENTS ADSP-BF706 Blackfin processor USB Mini Connector

ADDITIONAL HARDWARE REQUIRED ICE-1000 or ICE-2000 emulator

ADDITIONAL SOFTWARE REQUIRED CrossCore Embedded Studio

GENERAL DESCRIPTION The ADSP-BF706 Blackfin® processor combines a dual-MAC signal processing engine, the advantages of a clean, orthogonal microprocessor instruction set (similar to instruction sets for reduced instruction set computer (RISC) processors), and single instruction, multiple data (SIMD) multimedia capabilities into a single instruction set architecture. Enhancements to the Blackfin+™ core add 32-bit MAC and 16-bit complex MAC support, cache enhancements, branch prediction and other instruction set improvements, while simultaneously maintaining the instruction set compatibility for previous versions of Blackfin products. The electric vehicle warning sound system (EVWSS) demo system is used in conjunction with the CrossCore® Embedded Studio (CCES) development tools to test the capabilities of the ADSP-BF706 Blackfin processor.

EVALUATION BOARD PHOTO

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Figure 1.

http://www.analog.com/ADSP-BF706?doc=UG-1305.pdf


https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/emulators.html?doc=UG-1305.pdf

https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/emulators.html?doc=UG-1305.pdf

http://www.analog.com/CCES?doc=UG-1305.pdf


http://www.analog.com/EVWSS?doc=UG-1305.pdf




http://www.analog.com


UG-1305 Electric Vehicle Warning Sound System User Guide

Rev. 0 | of 21

TABLE OF CONTENTS Features .............................................................................................. 1 Evaluation Kit Contents ................................................................... 1 Additional Hardware REquired ...................................................... 1 Additional Software Required ........................................................ 1 General Description ......................................................................... 1 Evaluation Board Photo ................................................................... 1 Revision History ............................................................................... 2 Evaluation Board Hardware ............................................................ 3

Hardware Installation .................................................................. 3 Power Supplies .............................................................................. 3 SPI Flash ........................................................................................ 3 UART Interface ............................................................................. 3 CAN0 Interface ............................................................................. 3 CAN1 Interface ............................................................................. 3 Debug Interface ............................................................................ 3

Expansion Interface ......................................................................3 Power Architecture .......................................................................4 EVWSS Demo System ..................................................................4 Reference Design Information ....................................................4 System Architecture ......................................................................4 Software-Controlled (SoftConfig) Switches ..............................5 Push-Buttons and Switches ..........................................................6 Jumpers ...........................................................................................7 LEDs ................................................................................................8 Connectors .....................................................................................9

Evaluation Board Software Quick Start Procedures .................. 10 Evaluation License ...................................................................... 10

Evaluation Board Schematic ......................................................... 11 Ordering Information .................................................................... 19

Bill of Materials ........................................................................... 19

REVISION HISTORY 12/2018—Revision 0: Initial Version


Electric Vehicle Warning Sound System User Guide UG-1305

Rev. 0 | of 21

EVALUATION BOARD HARDWARE The EVWSS demo system is designed to run as a standalone unit.

When removing the EVWSS demo system from the package, handle the board carefully to avoid the discharge of static electricity, which can damage some components.

Figure 2 shows the default jumper settings and boot mode switch used in installation. Confirm that the board is in the default configuration before use.

HARDWARE INSTALLATION Install and run the CCES software on the PC.

To connect an emulator to the EVWSS demo system, take the following steps:

1. Plug one side of the included Mini USB cable into theUSB connector port of the emulator. Plug the other sideof the cable into a USB port on the PC.

2. The status LED is green when the connection with the PCis working and the proper Windows® driver is installed.Refer to the ICE-1000 or ICE-2000 emulator user guide ifthe status LED does not illuminate.

3. Attach the emulator header (J2) on the bottom of theICE-1000 or ICE-2000 to the J12 connector on theEVWSS demo system.

4. Attach a 12 V power supply and appropriate plug to the12 V power adapter.

a. Plug the jack of the assembled power adapter into theJ14 power connector (12 V input) on the EVWSSdemo system.

b. Plug the other end of the power adapter into a poweroutlet. The power LED (LED2) is green when power isapplied to the board.

POWER SUPPLIES The EVWSS demo system uses an audio power amplifier that can draw high current. It is recommended to use a 12 V power supply, such as the GST90A12-P1M (12 V, 6.67 A, and 80 W), and a 2.5 mm × 5.5 mm plug.

SPI FLASH The ADSP-BF706 processor has three serial peripheral interfaces (SPIs): SPI0, SPI1, and SPI2. SPI2 is connected to a Winbond W25Q256/SO16, 256 Mb, serial flash memory with dual-SPI and quad-SPI support. This flash is used for booting, sound file storage, and scratchpad space.

Quad mode is enabled by default. The processor flag signals, PB_15 (SPI2_SEL1), PB_13 (SPI2_D2), and PB_14 (SPI2_D3) are straight connected.

UART INTERFACE The ADSP-BF706 processor has two built in universal asynchronous transmitters (UARTs). UART0 is connected to a USB to UART converter IC (FT232RQ).

The UART functionality must be enabled through the SoftConfig. Refer to the Software-Controlled (SoftConfig) Switches section for details.

The EVWSS warning sound application configures the SoftConfig switch to enable the UART interface.

CAN0 INTERFACE The Controller Area Network 0 (CAN0) interface of the EVWSS demo system is connected to the CAN transceiver (TJA1041). The transceiver is attached to the CAN0 port of the ADSP-BF706 processor via the J2 connector.

The CAN0 transmit, receive, and error signals are connected through the SoftConfig switches and disabled by default. CAN0_EN is enabled by default and #CAN0_STB is disabled. See the Software-Controlled (SoftConfig) Switches section for details.

CAN1 INTERFACE The Controller Area Network 1 (CAN1) interface of the EVWSS demo system is connected to the TJA1041 CAN transceiver. The transceiver is attached to the CAN1 port of the ADSP-BF706 processor via the J3 connector.

The CAN1 signals are straight connected and do not require configuration by the SoftConfig switches.

DEBUG INTERFACE The EVWSS demo system provides a 0.05 inch pitch header JTAG/SWD/SWO connection via the J12 connector. See the JTAG/SWD/SWO Connector (J12) section for details.

EXPANSION INTERFACE The expansion interface allows the testing of a custom design daughter board across various hardware platforms that have the same expansion interface.

The Expansion Interface 3 (EI3) is implemented on the EVWSS demo system and consists of a single connector, J4. This connector contains a majority of the signals of the processor. For details, see the Evaluation Board Schematic section.

When using the expansion interface, consider the limits to the current and interface speed. The current for the extenders that are connected to the EI3 connectors can be sourced from the EVWSS demo system. Therefore, the current must be limited to 250 mA for the 5 V planes, and 300 mA for the 3.3 V planes. If a greater current is required, a design a separate power connector and a regulator on the daughter board. Implementing additional circuitry on the daughter boards can add extra loading to signals, which decreases the maximum effective speed of these cards. Note that Analog Devices does not support and is not responsible for the effects of additional circuitry.





http://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/emulators.html?doc=UG-1305.pdf



















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POWER ARCHITECTURE The EVWSS demo system has four primary voltage levels: 12 V, 5 V, 3.3 V, and 1.1 V. The power input of the system is a 12 V wall adapter.

The Analog Devices LT8602 42 V, quad, monolithic step-down regulator provides the voltage levels for the 12 V input, the VDD_EXT signal (3.3 V) and the 3.3 V power requirements of the board, the VDD_INT signal (1.1 V), and the voltage for the CAN interface supply (5 V).

The audio power amplifier (U16) is supplied directly by the 12 V input.

Voltage levels can be measured for VDD_INT (J13), and VDD_EXT (J1). Current consumption of the power rail can be measured when the corresponding jumpers are removed.

EVWSS DEMO SYSTEM See the EVWSS product page and request the ADSP-BF706 code. A how-to start guide is included with the software package.

REFERENCE DESIGN INFORMATION The reference design information package is available for download from the EVWSS product page. The package provides information on the design, layout, fabrication, and assembly of the EVWSS demo system.

SYSTEM ARCHITECTURE This section describes the EVWSS demo system configuration (see Figure 2).

The EVWSS demo system demonstrates the capabilities of the ADSP-BF706 processor. The EVWSS demo system has an audio-friendly, 24.576 MHz input clock.

The user input and output to the processor is provided in the form of one user push-button and three LEDs. The software-controlled (SoftConfig) switches facilitate the switch multifunctionality by disconnecting the push-button from the associated processor pins and reusing the processor pins elsewhere on the board. See the Evaluation Board Schematic section for details.

ADSP-BF706WCCPZ4xx1MB L2 SRAM WITH ECC

512kB L2 ROMU1

EVWWS REFERENCE BOARDELECTRIC VEHICLE WARNING SOUND SYSTEM

12V (EXTERNAL)

CLKIN

JTAG

NXPTJA1041

QUAD SPIFLASH

FTDIFT232RQ

USB TO UART

HVBUCK2

0.5A

TRKSS2OUT2

PVIN2

PBsRST/GP

RESET

LEDs

5V

6VTO24V

5V

3.3V

1.1V

3.3V_SLEEP

6V TO 18.5V SPEAKER × 4

5V

UART0

SYS_EXTWAKE

HVBUCK1

0.5A

ST MicroTDA7803

CLASS A/CLASS B

TRKSS1OUT1

VDD

_EXT

SPI1

SWT027ROTARY

CA

N0

NXPTJA1041

CA

N1

SPI2

GPI

O: P

C_0

2

GPI

O: P

C_0

3

PWR

PVIN1

LVBUCK2

0.5A

RUN4OUT4

PVIN4

LVBUCK1

0.5A

RUN3OUT3

PVIN3

LT8602VIN

VDD

_IN

T

SPO

RT0

A/I2

S/TD

M

STD

BY/

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INPUT

I2C

I2S/TDMTWI0

SPORT1A/B

5V

24.576MHz OSCILLATORFOR 48kHz AUDIO CLOCK

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Figure 2. EVWSS Demo Block Diagram


http://www.analog.com/LT8602?doc=UG-1305.pdf












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SOFTWARE-CONTROLLED (SOFTCONFIG) SWITCHES Most of the traditional mechanical switches on the EVWSS demo system are replaced by an I2C software-controlled switch. The remaining mechanical switches are provided for the boot mode, push-buttons, and controlling modes of the audio power amplifier.

This section of the user guide serves as a reference to modify an existing software example. If the firmware provided from Analog Devices is used, there is little need to reference this section.

Programming SoftConfig Switches

The EVWSS demo system contains an 8-bit, general-purpose, parallel input/output IC (MCP23008) with the following programming characteristics:

A switch with one programmable general-purpose input/output (GPIO) register (Address 0x09).

A GPIO register with control of eight signals. By default, the MCP23008 GPIO signals function as input

signals. The signals must be programmed as output signals to override their default values. The EVWSS programs the SoftConfig switch.






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PUSH-BUTTONS AND SWITCHES This section describes operation of the push-buttons and switches (see Figure 3).

LT8602QFN40

U15


512kB L2 ROMU1

SW2 PB1

SW1 RESET

SW3


U16TDA7803A

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Figure 3. Push-Button and Boot Mode Switch Locations

Reset Push-Button (SW1)

The reset push button (SW1) resets the processor (U1), SoftConfig switch (U12), and SPI flash (U4) ICs. The reset push-button also is connected to the expansion interface (J4) via the SYS_HWRST signal.

GPIO Push-Button (SW2)

The GPIO push button (SW2) are connected to the PA_15/ EPPI0_FS3/SPT0_ATDV/SPT0_BTDV/SPT0_BTDV/CNT0_UD signal of the ADSP-BF706 processor, and the signal is connected by default.

Boot Mode Select Switch (SW3)

The rotary switch (SW3) determines the boot mode of the processor. Table 1 describes the available boot mode settings. By default, the ADSP-BF706 processor boots from the SPI flash memory.

Table 1. Boot Mode Select Switch (SW3) SW3 Position Processor Boot Mode 0 No boot, idle. 1 SPI master boot mode (SP12). Default boot

mode. 2 SPI slave boot (SPI2). 3 UART boot (UART0).





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JUMPERS This section describes functionality of the configuration jumpers (see Figure 4).

LT8602QFN40

U15

J1

VDD

_EXT

J13 VDD

_IN

T

P2

J15

J17

J11


512kB L2 ROMU1


U16TDA7803A

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Figure 4. Jumper Locations

Table 2. Power Jumpers Parameter Processor Boot Mode J1 Connects VDD_EXT signal to the processor. J13 Connects VDD_INT signal to the processor.

Table 3. Mode Configuration Jumpers Mode Value J11 Header used to configure the TDA7803A audio power amplifier. J11.1 Insert. J11.2 Remove. J11.3 Remove. J11.4 Remove. J15 Insert to mute the power amplifier. Removed by default. J17 Header can be used to directly program the audio power amplifier with the respective I2C programmer device. Inserted by default. J17.1 Connects the SCL power amplifier signal to the I2C network or processor of the board. Inserted by default. J17.2 Connects the SDA power amplifier to the I2C network or processor of the board. Inserted by default. J17.3 Ground. Removed by default. P2 Remove.



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LEDS This section describes the on-board LEDs (see Figure 5).

LT8602QFN40

U15

LED

1

RES

ET

LED

3

FAU

LT

LED

2

PWR

LED

0

GP


512kB L2 ROMU1


U16TDA7803A

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Figure 5. LED Locations

GPIO LED (LED0)

LED0 is connected to the GPIO pins of the processor. The LED is active high and can be illuminated (yellow) by writing a 1 to the correct processor signal.

Reset LED (LED1)

When LED1 illuminates red, the master reset of all the major ICs is active. LED1 is controlled by the ADM6315 supervisory reset circuit. The TARGET_RESET signal is driven from an emulator. EI3 extender cards can also drive a reset as an input to this reset circuit. Press the SW2 switch to perform a master reset and activate LED1. For more information, see the Reset Push-Button (SW1) section.

Power LED (LED2)

When LED2 illuminates green, power is being properly supplied to the board. For more information, see the Power Architecture section.

SYS_FAULT LED (LED3)

When LED3 (SYS_FAULT LED) illuminates red, a system fault has occurred. For more information, refer to the ADSP-BF70x Blackfin+ Processor Hardware Reference Manual.

http://www.analog.com/ADM6315?doc=UG-1305.pdf

http://www.analog.com/media/en/dsp-documentation/processor-manuals/BF70x_BlackfinProcessorHardwareReference.pdf?doc=UG-1305.pdf

http://www.analog.com/media/en/dsp-documentation/processor-manuals/BF70x_BlackfinProcessorHardwareReference.pdf?doc=UG-1305.pdf



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CONNECTORS This section describes connector functionality and provides information about mating connectors. The connector locations are shown in Figure 6.

Connectors located on the back of the board are noted with dotted lines in Figure 6.

EI3 Connector (J4)

One board-to-board connector (J4) provides signals from the SPI, two-wire interface (TWI), UART, SPORT, and GPIO interfaces of the processor. The connectors are located on the back of the board.

For more information, see the Expansion Interface section.

JTAG/SWD/SWO Connector (J12)

The JTAG/SWD/SWO header (J12) provides debug connectivity for the processor in the form of 0.05 inch, shrouded, through-hole connector (SHF-105-01-L-D-TH). This connector mates with the ICE-1000 and ICE-2000 emulators, or any future Analog Devices emulators. For more information, see the Expansion Interface section.

LT8602QFN40

U15

J12


512kB L2 ROMU1

J2 CAN0

J3 CAN1

USB UARTP3

+12V INPUTJ14

OUT1 LF J5OUT2 LR J5OUT3 RF J7OUT4 RR J8


U16TDA7803A

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CONNECTION ON THE BACK OF THE BOARD

Figure 6. Connector Locations





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EVALUATION BOARD SOFTWARE QUICK START PROCEDURES For full details, refer to the EVWSS Software Architecture Design manual, which is included in the EVWSS software files.

Ensure that the CCES software is installed and running on the PC.

1. Navigate to the CCES software via the Start menu. Note that the CCES software is not connected to the board. a. Use the Debug Configurations Wizard to connect to

the EVWSS demo system. If a debug configuration already exists, select the appropriate configuration and click Debug, and then proceed to Step 8. To create a debug configuration, click the down arrow next to the bug icon, select Debug Configurations > Run > Debug Configurations. The Debug Configuration dialog box appears.

2. Select CrossCore Embedded Studio Application and click (New launch configuration). The Select Processor pane of the Session Wizard appears.

3. Ensure that Blackfin is selected in Processor family pane. In the Processor type pane, select ADSP-BF706, and then click Next. The Select Connection Type pane of the Session Wizard appears.

4. Select Emulator and click Next. The Select Platform pane of the Session Wizard appears.

5. From this pane, select the type of emulator that is connected to the EVWSS demo system, and click Finish to close the wizard. The new debug configuration is created and added to the Debug Configurations list.

6. In the Name edit box, users enter an appropriate name to describe the configuration, otherwise a default name is provided.

7. In the Program(s) to load pane, select the program to load if the appropriate program is not already populated when connecting to the board. Do not make changes if there is no need to load any program when connected to the board.

Note that when connected to the board, it is not possible to choose a program to download. To load a program when

connected to the board, terminate the session and then load the new program.

To delete a configuration, navigate to the delete box, indicated by a red cross, and select the configuration to delete. Click Close and select Yes in the Debug Configurations dialog box when asked if the user wishes to delete the selected launch configuration, and then close the dialog box.

To disconnect from the board, click the terminate icon or choose Run > Terminate.

To delete a session, select Target > Session > Session List. Select the session name from the list, click Delete, and then click OK.

The default configurations that appear in the CCES Debug Configurations Wizard are for JTAG mode debugging only. To use SWD mode, create a new platform with the Target Configurator.

EVALUATION LICENSE When running the CCES software for the first time, the user is prompted to install either a 90-day evaluation license or a permanent, full license. To automatically install an unrestricted, 90-day evaluation license, select I do not have a serial number and would like to evaluate the product. If the evaluation license is installed but not activated, the license allows 10 days of unrestricted use and then is disabled. The license can be re-enabled by activation. When the license is activated, the evaluation license offers 90 days of unrestricted use and then is permanently disabled.

An evaluation license can be upgraded to a full license by purchase from Analog Devices.

Note that the EVWSS demo hardware must be connected and powered up to use the CCES software with a valid evaluation license or full license.













Rev. 0 | of 21

EVALUATION BOARD SCHEMATIC


512kB L2 ROMU1


12V (EXTERNAL)

CLKIN

JTAG

NXPTJA1041

QUAD SPIFLASH

FTDIFT232RQ

USB TO UART

HVBUCK2

0.5A

TRKSS2OUT2

PVIN2

PBsRST/GP

RESET

LEDs

5V

6VTO24V

5V

3.3V

1.1V

3.3V_SLEEP

6V TO 18.5V SPEAKER × 4

5V

UART0

SYS_EXTWAKE

HVBUCK1

0.5A

ST MicroTDA7803

CLASS A/CLASS B

TRKSS1OUT1

VDD

_EXT

SPI1

SWT027ROTARY

CA

N0

NXPTJA1041

CA

N1

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GPI

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I2S/TDMTWI0

SPORT1A/B

5V

24.576MHz OSCILLATORFOR 48kHz AUDIO CLOCK

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Figure 7.



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_11

27P

B_1

225

PB

_13

24P

B_1

423

PB

_15

16P

C_0

013

PC

_01

10P

C_0

29

PC

_03

8P

C_0

47

PC

_05

6P

C_0

65

PC

_07

3P

C_0

82

PC

_09

1P

C_1

0

76G

ND

89E

P[G

ND

]

U1

AD

SP-B

F706

KC

PZ-3

PA

_14/

LED

0P

A_1

5/P

B0

PA

_13/

CA

N1_

TXP

A_1

2/C

AN

1_R

XP

A_1

1/S

PT1

_AD

1P

A_1

0/S

PT1

_AD

0P

A_0

9/S

PT1

_AFS

PA

_08/

SP

T1_A

CLK

PA

_07/

SP

T1_A

TDV

/SP

T1_B

TDV

PA

_06/

TM0_

TMR

1P

A_0

5/TM

0_TM

R0

PA

_04/

SP

I1_S

EL1

#/S

PI1

_SS

#P

A_0

3/S

P1_

RD

YP

A_0

2/S

PI1

_MO

SI

PA

_01/

SP

I1_M

ISO

PA

_00/

SP

I1_C

LK

PB

_00/

SP

T1_B

CLK

PB

_01/

SP

T1_B

FSP

B_0

2/S

PT1

_BD

0P

B_0

3/S

PT1

_BD

1P

B_0

4/E

I3_G

PIO

0P

B_0

5/E

I3_G

PIO

1P

B_0

6/E

I3_G

PIO

2P

B_0

7/S

YS

_WA

KE

0

PB

_10/

SP

I2_C

LKP

B_1

1/S

PI2

_MIS

OP

B_1

2/S

PI2

_MO

SI

PB

_13/

SP

I2_D

2P

B_1

4/S

PI2

_D3

PB

_15/

SP

I2_S

EL1

#

PC

_00/

SP

T0_A

D1

PC

_01/

EI3

_GP

IO3

PC

_02/

UA

RT0

_RTS

#/C

AN

0_R

XP

C_0

3/U

AR

T0_C

TS#/

CA

N0_

TXP

C_0

4/E

I3_G

PIO

4P

C_0

5/S

PT0

_AFS

PC

_06/

EI3

_GP

IO5

PC

_07/

CA

N0_

ER

RP

C_0

8/S

PT0

_AD

0P

C_0

9/S

PT0

_AC

LK

PC

_10/

CA

N1_

ER

R

VD

D_E

XT

VD

D_I

NT

3.3V

SY

S_X

TAL

SY

S_C

LKIN

SY

S_E

XTW

AK

E

SY

S_F

AU

LT#

SY

S_H

WR

ST#

3.3V

SY

S_B

MO

DE

1S

YS

_BM

OD

E0

SY

S_N

MI#

JTG

_TC

K/S

WC

LK

JTG

_TD

I

JTG

_TD

O/S

WO

JTG

_TM

S/S

WD

IO

JTG

_TR

ST#

3.3V

VD

D_I

NT

3.3V

PB

_08/

UA

RT0

_TX

#P

B_0

9/U

AR

T0_R

X#

TWI0

_SC

L

TWI0

_SD

A3.

3V

JTG

_TR

ST#

JTG

_TM

S/S

WD

IOJT

G_T

CK

/SW

CLK

JTG

_TD

O/S

WO

JTG

_TD

ITA

RG

ET_

RE

SE

T#

SY

S_C

LKO

UT

SY

S_F

AU

LT#

SY

S_N

MI#

3.3V

VD

D_E

XT

CA

N0_

EN

CA

N0_

TX_E

N#

CA

N0_

RX

_EN

#C

AN

0_S

TB#

CA

N0_

ER

R_E

NU

AR

T0_E

N#

UA

RT0

_RTS

_EU

AR

T0_C

TS_E

3.3V

TWI0

_SC

LTW

I0_S

DA

3.3V

SC

LS

DA

SY

S_H

WR

ST#

Figure 8. Processor Schematic



Rev. 0 | of 21

16878-010

1V

CC

IO

2R

XD

3R

I#

4D

GN

D4

5N

C5

6D

SR

#

7D

CD

#

8C

TS#

9C

BU

S4

10C

BU

S2

11C

BU

S3

12N

C12

13N

C13

14U

SB

DP

15U

SB

DM

163V

3OU

T

17D

GN

D17

18R

ES

ET#

19V

CC

20D

GN

D20

21C

BU

S1

22C

BU

S0

23N

C23

24A

GN

D

25N

C25

26TE

ST

27O

SC

I28

OS

CO

29N

C29

30TX

D

31D

TR#

32R

TS#

33G

P

U7

FT23

2_Q

FN32

SH

8S

H9

SH

7S

H6

GN

DIDD

+D

-V

BU

S1 2 3 4 5 6 7 8 9

P3

CO

N_U

SB

_MIN

I_A

B

12

3 45

6

D4

DIO

_ES

DA

5V3

1 23

4 5 678

9

10

D5

DIO

_ES

D70

04

FB2

600R

1206

C27

100n

F04

02

R56 1M 06

03

FB3

600R

1206

C71

100n

F04

02

C72

100n

F04

02

C73

4.7u

F

R45

0R04

02

C74

100n

F04

02

C75

10nF

0402

1O

E#

2A

3G

ND

4B

5V

CC

U10

ICS

_SN

74X

XX

1G12

5

1O

E#

2A

3G

ND

4B

5V

CC

U18

ICS

_SN

74X

XX

1G12

5

1O

E#

2A

3G

ND

4B

5V

CC

U19

ICS

_SN

74X

XX

1G12

5

1O

E#

2A

3G

ND

4B

5V

CC

U20

ICS

_SN

74X

XX

1G12

5

R46 10

K04

02

R94 10

K04

02

R95 10

K04

02

R96 10

K04

02

R97 10

K04

02

C76

100n

F04

02

C77

100n

F04

02

C78

100n

F04

02

C79

100n

F04

02

FT23

2_3P

3V

PB

_09/

UA

RT0

_RX

#

PB

_08/

UA

RT0

_TX

#

PC

_03/

UA

RT0

_CTS

#/C

AN

0_TX

PC

_02/

UA

RT0

_RTS

#/C

AN

0_R

X

UA

RT0

_EN

#

UA

RT0

_CTS

_EN

#

UA

RT0

_RTS

_EN

#

3V3_

SLE

EP

3V3_

SLE

EP

Figure 9. USB/UART Schematic



Rev. 0 | of 21

16878-011

LAB

EL

"PB

1"

"RES

ET"

"RES

ET"

PR

OC

CR

YST

AL

SPI

FLA

SH

BO

OT

MO

DE

SW

ITC

H

BO

OT

MO

DE

(1:0

)

00 01 10 11

No

Boo

t

SP

I Mas

ter B

oot (

SP

I2) D

EFA

ULT

SP

I Sla

ve B

oot (

SP

I2)

UA

RT

Boo

t (U

AR

T0)

SO

IC12

7P10

30X

265-

16N

1 23 4

SW

2

EV

Q-Q

2K03

WS

witc

h 6m

m S

Q P

ush

But

ton

SM

D

R55

10K

0402

R51

330R

0402

R52

330R

0402

LED

0LE

D Y

ello

w 0

603

LED

2LE

D G

reen

060

3

1A

2B

3V-

4Y

5 V+

U8

SN74

LVC

1G08

DBV

RS

OT2

3-5

4V

CC

1G

ND

3*M

R2

*RE

SE

T

U3

ADM

6315

R47

330R

0402LE

D1

LED

Red

060

3

R49 10

K04

02

R48 10

K04

02

C42

100n

F04

02

C43

100n

F04

02R

50 10K

0402

R77 10

K04

02

1 23 4

SW

1

EV

Q-Q

2K03

WS

witc

h 6m

m S

Q P

ush

But

ton

SM

D

R69

0402

3K01

1A

2B

3V-

4Y

5 V+

U17

SN74

LVC

1G08

DBV

RS

OT2

3-5

Y124.576Mhz

C3

18pF

0402

C2

18pF

0402

R23 0R 0402

R24 2K 0402

R74 10

K04

02

R73 10

K04

02

R18

0R

0402

R21

100K

0402

R22 10

K04

02

R19

100K

0402

R17

100K

0402

R20

100K

0402

C1

100n

F04

02

012

3 4 56

7

C1 2

34

SW

3

SW

_S-8

110

R27 10

K04

02

R28 10

K04

02

R29 10

K04

02

1H

OLD

#(IO

3)2 VCC

3R

ES

ET#

4N

C4

5N

C5

6N

C6

7C

S#

8D

0(IO

1)

9W

P#(

IO2)

10GND

11N

C11

12N

C12

13N

C13

14N

C14

15D

I(IO

0)16

CLK

U2

W25

Q25

6/S

O16

PA

_15/

PB

0

3V3_SLEEP

PA

_14/

LED

0

3.3V

SY

S_H

WR

ST#

3.3V

EI3

_RE

SE

T_IN

#

3.3V

TAR

GE

T_R

ES

ET#

3.3V

SY

S_C

LKIN

SY

S_X

TAL

3.3V

PB

_08/

UA

RT0

_TX

#

PB

_12/

SP

I2_M

OS

I

PB

_11/

SP

I2_M

ISO

PB

_12/

SP

I2_M

OS

I

PB

_10/

SP

I2_C

LK

PB

_15/

SP

I2_S

EL1

#

PB

_13/

SP

I2_D

2

PB

_14/

SP

I2_D

3

3.3V

3.3V

SY

S_B

MO

DE

1S

YS

_BM

OD

E0

3V3_

SLE

EP

SY

S_H

WR

ST#

Figure 10. Clock/Reset/Memory Schematic



Rev. 0 | of 21

16878-012

"CAN

0"

"CAN

1"

SO

IC12

7P60

0X17

5-14

N

SO

IC12

7P60

0X17

5-14

N

1TX

D

2GND3 VDD

4R

XD

5 VIO

6E

N7

INH

8E

RR

#

9W

AK

E

10 VBAT

11S

PLI

T12

CA

NL

13C

AN

H

14S

TB#

U4

TJA

1041

T/C

M,1

18C

304.

7nF

0402

R9 60R

0603

R10 60

R06

03

R12

10R

0603

R13

10R

0603

1 2 3 4

J2

R14

10K

0402

DN

P

R15

10K

0402

R33

10K

0402

1O

E#

2A

3G

ND

4B

5V

CC

U5

ICS

_SN

74X

XX

1G12

5

1O

E#

2A

3G

ND

4B

5V

CC

U6

ICS

_SN

74X

XX

1G12

5

1O

E#

2A

3G

ND

4B

5V

CC

U9

ICS

_SN

74X

XX

1G12

5

R34

10K

0402

R35

10K

0402

R36

10K

0402

R37

10K

0402

DN

P

C31

10nF

0402

C32

10nF

0402

C33

100n

F04

02

C34

100n

F04

02

C35

100n

F04

02

1TX

D

2GND3 VDD

4R

XD

5 VIO6

EN

7IN

H

8E

RR

#

9W

AK

E10 VBAT

11S

PLI

T12

CA

NL

13C

AN

H

14S

TB#

U11

TJA

1041

T/C

M,1

18C

384.

7nF

0402

R38 60

R06

03

R39 60

R06

03

R40

10R

0603

R41

10R

0603

1 2 3 4

J3

R42

10K

0402

DN

P

R43

10K

0402

R44

10K

0402

C39

10nF

0402

C40

10nF

0402

C28

100p

F04

02

C29

100p

F04

02

C36

100p

F04

02

C37

100p

F04

02

3V3_

SLE

EP

CA

N0_

EN

CA

N0_

STB

#

3V3_

SLE

EP

5V

3V3_

SLE

EP

CA

N0_

ER

R#

3V3_

SLE

EP

3V3_

SLE

EP

CA

N0_

TX

CA

N0_

RX

PC

_07/

CA

N0_

ER

R

PC

_03/

UA

RT0

_CTS

#/C

AN

0_TX

PC

_02/

UA

RT0

_RTS

#/C

AN

0_R

X

CA

N0_

ER

R_E

N#

CA

N0_

TX_E

N#

CA

N0_

RX

_EN

#

3V3_

SLE

EP

3V3_

SLE

EP

3V3_

SLE

EP

5V

3V3_

SLE

EP

3V3_

SLE

EP

5V

3V3_

SLE

EP

5V

PC

_10/

CA

N1_

ER

R

PA

_13/

CA

N1_

TX

PA

_12/

CA

N1_

RX

Figure 11. CAN Schematic



Rev. 0 | of 21

16878-013

Pla

ce P

VIN

cap

s ve

ry c

lose

to in

put P

WR

&G

ND

pin

s (3

7&38

, 14&

13)

Use

min

of 2

x vi

as fo

r PW

R a

nd G

ND

con

nect

ion

SY

NC

Pin

:

HIG

H =

Pul

se-s

kipp

ing

mod

e

LOW

= B

urst

mod

e

L2 1uH

L4

600n

H

C48

5pF

C49

22uF

R54

806K

C50

5pF

C51

22uF

C54

5pF

R67

24K

3

C56

47uF

R68

75K

R70

1.74

M

R78

499K

C60

1uF

C62

2700

pF

R81

28K

7

R64

806K

L1 1uH

R66

348K

1P

G1

2G

ND

2

3S

W1

4B

ST1

5B

ST2

6S

W2_

67

SW

2_7

8G

ND

89

GN

D9

10B

IAS

11P

G2

12P

G4

13G

ND

13

14P

VIN

2

15S

W4

16G

ND

16

17P

VIN

4

18R

UN

4

19N

C19

20TR

KS

S2

21TR

KS

S1

22E

N/U

VLO

23V

IN

24FB

4

25FB

2

26FB

1

27FB

3

28IN

TVC

C

29R

T

30R

UN

3

31C

PO

R

32R

ST#

33S

YN

C

34P

VIN

3

35G

ND

35

36S

W3

37P

VIN

1

38G

ND

38

39P

OR

EN

40P

G3

41C

P

U15

LT86

02_Q

FN40

L3

600n

HC

66

5pF

R88

200K

C67

47uF

R89

75KR

9120

0K

C68

22uF

C69

22uF

C57

4.7u

F

C61

220p

FD

NP

TP131 2

J13

CO

N_2

X1

1 2

J1

CO

N_2

X1

1 2

J14

Dig

ikey

CP

-063

BH

-ND

R63

0R

0402

R71

0R

0402

DN

P

TP7

TP8

TP14

TP15

TP16

C25 10uF

R80

1R0

C44 10uF

L6

6.8u

H

C45 10uF

C55

2.2u

F

C59

2.2u

F

C58

100n

F04

02

C80

100n

F04

02

C46

100n

F

0402

C47

100n

F

0402

C53

100n

F04

02

C52

100n

F04

02D

NP

C41

100n

F04

02

FB1

600R

1206

R82

10K

0402

R83

0402

DN

P

5V

3.3V

+12V

_PS

U

+12V

_PS

U

+12V

_PS

U

INTV

CC

3V3_

SLE

EP

5V

VD

D_E

XT

VD

D_I

NT

+12V

SY

S_E

XTW

AK

E

3V3_

SLE

EP

+12V

_PS

U

INTV

CC

Figure 12. PSU Schematic



Rev. 0 | of 21

16878-014

OU

T1_L

F

OU

T2_L

R

OU

T3_R

F

OU

T4_R

R

CD

/DIA

G

IN

OU

T

EX

T

STB

Y E

XT

IN

OU

T

EX

T

STB

Y E

XT

JUM

PE

R S

ETT

ING

S

1TA

B1

2O

UT4

-

3VCC34_3

4P

WG

ND

4

5O

UT4

+

6N

C6

7CD/DIAG

8S

DA

9S

CL

10A

DD

11S

TBY

12W

S

13U

NM

UTE

HW

14O

UT2

+

15P

WG

ND

2

16VCC12_16

17O

UT2

-

18TA

B18

19TA

B19

20O

UT1

-

21VCC12_21

22P

WG

ND

1

23O

UT1

+

24S

CK

25S

D24

26S

D13 27

DGND

28AGND

29D3V3

30A3V3

31N

C31

32O

UT3

+

33P

WG

ND

3

34VCC34_34

35O

UT3

-

36TA

B36

37G

P37

U16

TDA

7803

_PO

WE

RS

O

1 2 3

J5 CO

N_3

X1

1 2 3

J6 CO

N_3

X1

1 2 3

J7 CO

N_3

X1

1 2 3

J8 CO

N_3

X1

C65

2200

uF

1 2 3 4

P2

CO

N_4

X1

22-2

8-40

40

J11

HE

AD

ER

-4X

2PO

L

R85 2K

204

02

DN

P

R86 2K

204

02

DN

P

R79

10K

0402

L5

10uH

C82

100n

F04

02

C83

100p

F04

02C

8410

0nF

0402

C85

100p

F04

02

C70

4.7n

F04

02

C81

4.7n

F04

02

C86

4.7n

F04

02

C87

4.7n

F04

02

C88

100n

F04

02

C89

100p

F04

02

C64

4.7u

F

C90

100n

F04

02

C91

100p

F04

02

C92

1uF

R90

47K

0402

1 2

J15

CO

N_2

X1

C63

22uF

R65 47K

0402

PC

_05/

SP

T0_A

FSP

C_0

9/S

PT0

_AC

LKP

C_0

8/S

PT0

_AD

0P

C_0

0/S

PT0

_AD

1+12V

_AM

P

3.3V

STB

Y

3.3V

SD

AS

CL

3.3V

+12V

Figure 13. Power Amplifier Schematic



Rev. 0 | of 21

1687

8-01

5

94PPI0_CLK95PPI0_FS2101PPI0_D0102PPI0_D2103PPI0_D4105PPI0_D6106PPI0_D8107PPI0_D10108PPI0_D1212PPI0_D14111PPI0_D16112PPI0_D18113PPI0_D20114PPI0_D2299PPI0_INT

27PPI0_FS1 26PPI0_FS3 20

PPI0_D1 19PPI0_D3 18PPI0_D5 16PPI0_D7 15PPI0_D9 14

PPI0_D11 13PPI0_D13 110PPI0_D15 10PPI0_D17 9PPI0_D19 8PPI0_D21 7PPI0_D23

87SPORT0_CLK89SPORT0_FS29SPORT0_TDV88SPORT0_D032SPORT0_D135SPORT_INT

92SPORT1_CLK 90

SPORT1_FS 30SPORT1_TDV 91

SPORT1_D0 31SPORT1_D1

82SPI0_CLK83SPI0_MISO33SPI0_D239SPI0_SEL1/SPI0_SS#37SPI0_SEL_B61EXT_BOOT

56TWI0_A0#

50SPI0_RDY 84

SPI0_MOSI 34SPI0_D3 85

SPI0_SEL_A 38SPI0_SEL_C

42SCL1# 41SDA1#

78GPIO1 77GPIO3 76GPIO5 74

GPIO7#73

TMR_B 72TMR_D#

62UART0_TX

64SLEEP#

57RESET_OUT#

5USB_VCC 116

VIO

79SCL0#80SDA0#

43GPIO044GPIO245GPIO447GPIO6

48TMR_A49TMR_C

59UART0_RX

65WAKE#

60RESET_IN#

71CLKOUT

1VIN120PS_IN

3GND16GND317GND528GND740GND952GND1163GND1375GND1586GND1798GND19109GND21117GND23

4GND2 11GND4 23GND6 36GND8 46

GND10 58GND12 69GND14 81GND16 93GND18 104GND20 115GND22 118GND24

2RSVD1

21RSVD222

RSVD324

RSVD425RSVD5

51RSVD653

RSVD754

RSVD855RSVD9

66RSVD1067

RSVD1168

RSVD1270RSVD13

96RSVD1497

RSVD15100

RSVD16119RSVD17

J4CONN_HIROSE_FX8_120PSV

R87 10K0402

R25

0402

DNP R26

0402

DNP

PB_00/SPT1_BCLKPB_01/SPT1_BFSPA_07/SPT1_ATDV/SPT1_BTDVPB_02/SPT1_BD0PB_03/SPT1_BD1

PA_08/SPT1_ACLKPA_09/SPT1_AFS

PA_07/SPT1_ATDV/SPT1_BTDVPA_10/SPT1_AD0PA_11/SPT1_AD1

TWI0_SCLTWI0_SDA

PB_04/EI3_GPIO0PB_06/EI3_GPIO2PC_04/EI3_GPIO4

PA_05/TM0_TMR0

PB_09/UART0_RX#

PB_07/SYS_WAKE0

SYS_CLKOUT

5V

TWI0_SCLTWI0_SDA

PB_05/EI3_GPIO1

PA_06/TM0_TMR1

PB_08/UART0_TX#

SYS_EXTWAKE

SYS_HWRST#

3.3V

PA_00/SPI1_CLKPA_01/SPI1_MISO

PA_04/SPI1_SEL1#/SPI1_SS#

EI3_RESET_IN#

PA_03/SP1_RDYPA_02/SPI1_MOSI

PC_01/EI3_GPIO3PC_06/EI3_GPIO5

Figure 14. SDP Connector Schematic



Rev. 0 | of 21

ORDERING INFORMATION BILL OF MATERIALS

Table 4. Qty. Reference Designator Description Part Number 33 C1, C6, C8 to C10,

C15, C17, C21, C23, C27, C33 to C35, C41 to C43, C46, C47, C52, C53, C58, C71, C72, C74, C76 to C80, C82, C84, C88, C90

Capacitor, 0.1 μF, 10 V, 10%, X5R, 0402 0402ZD104KAT2A

2 C2, C3 Capacitor, 18 pF, 50 V, 5%, NP0, 0402 GRM1555C1H180JA01D 6 C7, C16, C24, C25,

C44, C45 Capacitor, 1206, 10 μF, 25 V, X5R FEC 1833825

14 C11 to C14, C18 to C20, C22, C26, C31, C32, C39, C40, C75

Capacitor, 0.01 μF, 16 V, 10%, 0402, X7R 0402YC103KAT2A

8 C28, C29, C36, C37, C83, C85, C89, C91

Capacitor, 0402 (1005 metric), 100 pF, 50 V, ±5%, C0G/NP0 FEC 2496792

6 C30, C38, C70, C81, C86, C87

Capacitor, 4700 pF, 16 V, 10%, X7R, 0402 FEC 2507329

4 C48, C50, C54, C66 Capacitor, 0402 (1005 metric), +5 pF, 50 V, ±0.25 pF, C0G/NP0, CGA series

FEC 2458210

5 C49, C51, C63, C68, C69

Capacitor, ceramic, 22 μF, 6.3 V, X7R, 10%, 1206 FEC 1845771

2 C55, C59 Capacitor, 1206, 2.2 μF, 50 V, X7R FEC 2470443 2 C56, C67 Capacitor, ceramic, 47 μF, 6.3 V, X5R, 20%, 1206 FEC 1907351 3 C57, C64, C73 Multilayer ceramic capacitor, 0603, 6.3 V, 4.7 μF, X5R FEC 1740638 2 C60, C92 Capacitor, low effective series resistance (ESR), 1 μF, 16 V, X7R FEC 2112839 1 C61 Capacitor, ceramic, 220 pF, 50 V, X7R, 10%, 0402, do not populate FEC 2210798 1 C62 Capacitor, 2700 pF, 0402 FEC 2627354 1 C65 Capacitor, aluminum electrolytic, 2200 μF, 16 mm, 25 V FEC 2326204 1 D4 Diode, electrostatic discharge (ESD), quad array 497-6633-1-ND 1 D5 Diode, transient voltage suppressor, high speed ESD7004MUTAG 3 FB1 to FB3 Ferrite bead, 600 Ω, 1206 HZ1206B601R-10 3 J1, J13, J15 Connector, two position header, cuttable connector, 0.100 inch

(2.54 mm), through hole, gold Digikey 952-2261-ND

2 J2, J3 Connector, RJ-11, 4-pin, 4P4C 5558872-1 1 J4 Connector, FX8, series, receptacle 0.6 mm, 120 SMD plug Hirose FX8 120PSV 4 J5 to J8 Connector, standard terminal block, wire to board, CTB5202 series,

5 mm, printed circuit board (PCB) mount FEC 1717002

1 J11 Connector, inline header, 8-pin, two rows, through hole, 2.54 mm pitch FEC 1593441 1 J12 Connector, 1.27 mm, 10 contacts, header, through hole, two rows SHF-105-01-L-D-TH 1 J14 Connector, power jack, 2.5 mm × 5.5 mm Digikey CP-063BH-ND 1 J17 Connector, inline header, 6-pin, two rows, through hole, 2.54 mm pitch FEC 2135961 2 L1, L2 Inductor, XFL3010, low dc resistance, 1 μH, 20%, 2.3 A Mouser 994-XFL3010-102MEB 2 L3, L4 Inductor, XFL3010, low dc resistance, 0.6 μH, 20%, 2.5 A Mouser 994-XFL3010-601MEB 1 L5 Inductor, MSS1260 series, 10 μH, 4 A, 6.18 A, shielded, 0.0239 Ω FEC 2288425 1 L6 Inductor, SRN3015TA, 6.8 μH, 20%, 1 A Digikey SRN3015TA-6R8MCT-ND 1 LED0 LED, yellow, 0603 475-2793-1-ND 2 LED1, LED3 LED, red, 0603 67-1549-2-ND 1 LED2 LED, green, 0603 67-1549-2-ND 1 P2 Connector, wire to board, 2.54 mm, four contacts, header, KK 42375

series, through hole, one row FEC 2381172



Rev. 0 | of 21

Qty. Reference Designator Description Part Number 1 P3 Connector, USB Mini A or USB Mini B H125271TR-ND 43 R1, R7, R8, R14, R15,

R22, R27 to R29, R31 to R37, R42 to R44, R46, R48 to R50, R53, R55, R57, R60, R74, R77, R79, R82, R83, R87, R92 to R100

Resistor, 10 kΩ, 5%, 0402 CRCW040210K0FKED

18 R2, R3, R6, R11, R16, R18, R23, R25, R26, R45, R58, R59, R61 to R63, R71 R76, R84

Resistor, 0 Ω, 1/10 W, 5%, 0402 ERJ-2GE0R00X

2 R4, R5 Resistor, 2.2 kΩ, 1/10 W, 5%, 0402 ERJ-2GEJ222X 4 R9, R10, R38, R39 Resistor, 60.4 kΩ, 1/10 W, 1%, 0603 ERJ-3EKF60R4V 4 R12, R13, R40, R41 Resistor, 10 Ω, 1/10 W, 5%, 0603 CRCW060310R0JNEA 4 R17, R19 to R21 Resistor, 100 kΩ, 1/16 W, 5%, 0402 541-100KJTR-ND 1 R24 Resistor, 2 kΩ, 1/10 W, 1%, 0402 ERJ-2RKF2001X 4 R30, R47, R51, R52 Resistor, 330 Ω, 1/16 W, 1%, 0402 541-330LCT-ND 2 R54, R64 Resistor, 806 kΩ, 0402, 1% FEC 2141028 1 R56 Resistor, 1 MΩ, 1/10 W, 5%, 0603 CRCW06031M00JNEA 2 R65, R90 Resistor, 47 kΩ, 1/16 W, 5%, 0402 FEC 1358087 1 R66 Resistor, 348 kΩ, 0402, 1% FEC 2302898 3 R67, R68, R89 Resistor, 75 kΩ, 5%, 0402 Any 1 R69 Resistor, 3.01 kΩ, 1/16 W, 1%, 0402 MCR01MRTF3011 1 R70 Resistor, 1.74 MΩ, 75 V, 100 mW, ±1%, 0603 FEC 2138635 1 R78 Resistor, 499 kΩ, 63 mW, 1%, 0402 FEC 2073089 1 R80 Resistor, 1 Ω, 50 V, 63 mW, ±5%, 0402 FEC 1739054 1 R81 Resistor, 0402, 1%, 28.7 kΩ ERJ-2RKF2872X 2 R85, R86 Resistor, 2.2 kΩ, 1/10 W, 5%, 0402, do not populate ERJ-2GEJ222X 2 R88, R91 Resistor, 200 kΩ, 1/10 W, 5%, 0402 Any 2 SW1, SW2 Switch, 6 mm, square push-button, SMD EVQ-Q2K03W 1 SW3 Switch, rotary dual inline package, octal, 100 mA, 5 V Digikey 563-1057-ND 16 TP1 to TP16 Test pad, do not populate Not applicable 1 U1 IC, DSP, low power, 1024 kB flash, L2 SRAM, 88-lead, LFCSP ADSP-BF706BCPZ-4 1 U2 IC, flash, SOIC-16 W25Q256FV 1 U3 IC, open drain, microprocessor supervisory circuit ADM6315-29D2ARTZR7CT-ND 2 U4, U11 IC, CAN transceiver TJA1041T/CM,118 7 U5, U6, U9, U10,

U18, U19, U20 IC, 1-bit, field effect transistor (FET), bus switch, SC-70-5 FEC 2424774

1 U7 IC, USB, full speed serial UART, 32-QFN FT232RQ 2 U8, U17 IC, single, two inputs, AND gate SN74LVC1G08DBVR 1 U12 IC, 8-bit, general-purpose, parallel input/output expansion MCP23008 1 U15 IC, dc-to-dc switching regulator, synchronous, four outputs, 3 V to 42 V

input, 42 V/2.5 A output, 2 MHz LT8602EUJ#PBF

1 U16 IC, Class D, audio power amplifier ST Micro TDA7803A 1 Y1 Crystal, 24.576 MHz, 18 pF, 4-SMD DigiKey 535-13393-1-ND


http://www.analog.com/ADM6315?doc=UG-1305.pdf

http://www.analog.com/LT8602?doc=UG-1305.pdf



Rev. 0 | of 21

NOTES

I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.

Legal Terms and Conditions By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) and Analog Devices, Inc. (“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to Customer a free, limited, personal, temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted is expressly made subject to the following additional limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third Party to access the Evaluation Board. As used herein, the term “Third Party” includes any entity other than ADI, Customer, their employees, affiliates and in-house consultants. The Evaluation Board is NOT sold to Customer; all rights not expressly granted herein, including ownership of the Evaluation Board, are reserved by ADI. CONFIDENTIALITY. This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI. Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason. Upon discontinuation of use of the Evaluation Board or termination of this Agreement, Customer agrees to promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited to soldering or any other activity that affects the material content of the Evaluation Board. Modifications to the Evaluation Board must comply with applicable law, including but not limited to the RoHS Directive. TERMINATION. ADI may terminate this Agreement at any time upon giving written notice to Customer. Customer agrees to return to ADI the Evaluation Board at that time. LIMITATION OF LIABILITY. THE EVALUATION BOARD PROVIDED HEREUNDER IS PROVIDED “AS IS” AND ADI MAKES NO WARRANTIES OR REPRESENTATIONS OF ANY KIND WITH RESPECT TO IT. ADI SPECIFICALLY DISCLAIMS ANY REPRESENTATIONS, ENDORSEMENTS, GUARANTEES, OR WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THE EVALUATION BOARD INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, TITLE, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS. IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT, OR CONSEQUENTIAL DAMAGES RESULTING FROM CUSTOMER’S POSSESSION OR USE OF THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT. Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable United States federal laws and regulations relating to exports. GOVERNING LAW. This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed.

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