ELEC 2200-002 Digital Logic Circuits Fall 2015 Logic Synthesis (Chapters 2-5) Vishwani D. Agrawal...

ELEC 2200-002Digital Logic Circuits

Fall 2015Logic Synthesis (Chapters 2-5)

Vishwani D. AgrawalJames J. Danaher Professor

Department of Electrical and Computer EngineeringAuburn University, Auburn, AL 36849http://www.eng.auburn.edu/~vagrawal

[email protected]

Fall 2015, Nov 6 . . .Fall 2015, Nov 6 . . . ELEC2200-002 Lecture 6ELEC2200-002 Lecture 6 11

http://www.eng.auburn.edu/~vagrawal

mailto:[email protected]

Logic SynthesisDefinition: To design a logic circuit such that it meets the specifications and can be economically manufactured:

Performance – meets delay specification, or has minimum delay.Cost – uses minimum hardware, smallest chip area, smallest number of gates or transistors.Power – meets power specification, or consumes minimum power.Testablility – has no redundant (untestable) logic and is easily testable.


Synthesis ProcedureMinimization – Obtain MSOP or MPOS. This is also known as two-level minimization because the result can be implemented as a two-level AND-OR or NAND-NAND or NOR-NOR circuit.Technology mapping – Considering design requirements, transform the minimized form into one of the technologically realizable forms:

Programmable logic array (PLA)Standard cell libraryField programmable gate array (FPGA)Others . . .


References on Synthesis

G. De Micheli, Synthesis and Optimization of Digital Circuits, New York: McGraw-Hill, 1994.S. Devadas, A. Ghosh and K. Keutzer, Logic Synthesis, New York: McGraw-Hill, 1994.


Programmable Logic Array (PLA)

A direct implementation of multi-output function as a two-level circuit in MOS technology.PLA styles:

NAND-NANDNOR-NOR

Textbook, Chapter 5.


0

4

12

8 1

1

5

13 1

9 1

3 7 1

15 1

11 1

2 6

14

10 1

0

4

12 8

1 1

5 1

13 1

9 1

3 7 1

15 1

11

2 6

14

10

Example: Two-Output FunctionNeed four products: P1, P2, P3, P4


F1 A

B

C

D

F2 A

B

C

D

Two-Level AND-OR ImplementationAlso known as technology-independent circuit.


A

B

C

D

F1

F2

P1

P2

P3

P4

INPUTS AND OR

INPUTS NAND NAND

NAND-NAND Implementation


A

B

C

D

F1

F2

1P

2P

4P

3P

A NAND Gate in nMOS Technology


VDD

X

Y

XY

GND

VDD

X

Y

XY

GND

VDD

X

Y

XY

GND

R. C. Jaeger and T, N. Blalock, Microelectronic Circuit Design,Boston: McGraw-Hill, 2008, Section 6.8.2.

Depletionload

Enhancementload

NAND-NAND PLA


A B C D F1 F2

1P

2P

4P

3P

VDD

VDD

VDD

VDD

VDD

VDD

GND

NAND-NAND PLA SCHEMATIC


A B C D F1 F2

1P

2P

4P

3P

INP

UTS

OU

TPU

TS

AND-plane OR-plane

Tran

sist

ors

atcr

oss-

poin

ts

Standard-Cell DesignObtain two-level minimized form.Map the design onto predesigned building blocks called standard cells (technology mapping).Standard-cell library contains predesigned logic cells in the technology of manufacture. Examples of technology:

90 nanometer CMOS65 nanometer CMOS45 nanometer CMOS. . .

This is known as application-specific integrated circuit (ASIC).


Technology MappingFind a common logic element, e.g., two-input NAND gate or inverter (one-input NAND).MSOP is converted into NAND-NAND circuit.Split larger input gates into two-input NAND gates and inverters.Cover the circuit with standard cells, also split into two-input NAND gates and inverters (graph-matching).


A Typical Cell LibraryName Area units (cost) Inputs Output function, Z

Inverter 2 A

NAND2 3 A, B

NAND3 4 A, B, C

NAND4 5 A, B, C, D

AOI21 4 A, B, C

OAI21 4 A, B, C

AOI22 5 A, B, C, D

XOR 4 A, B


AZ ABZ

ABCZ

ABCDZ CABZ

CDABZ BABAZ

S. Devadas, A. Ghosh and K. Keutzer, Logic Synthesis, New York: McGraw-Hill1994, Section 7.7, pp. 185-198.

CBAZ )(

NAND3 Cell in TransistorsNAND3 Cell in Transistors


A

B

C

Z

VDD

GND

NAND3 Cell Graphs


Directed AcyclicGraph (DAG)(tree)Root ≡ OutputOne-input node (NOT)Two-input node (NAND)

NAND4 Cell


AOI21 Cell


OAI21 Cell


AOI22 Cell in TransistorsAOI22 Cell in Transistors


A

B

C

D

VDD

GND

Z

Observe that in a CMOS circuit, any vector of input variables connects the output Zeither to GND or to VDD, giving it a value 0 or 1, respectively. Examining the pull-downnetwork, we notice that the output is connected to GND if AB = 1 or CD =1. Thatgives the output function as, . The cell, therefore, is AOI22.CDABZ

Pull-up network

Pull-down network

AOI22 Cell


XOR Cell


NAND Graphs for Library CellsName Area units (cost) Inputs NAND graph

Inverter 2 A

NAND2 3 A, B

NAND3 4 A, B, C

NAND4 5 A, B, C, D

AOI21 4 A, B, C

OAI21 4 A, B, C

AOI22 5 A, B, C, D

XOR 4 A, B


Technology Mapping ProcedureObtain MSOP.Convert to two-level AND-OR circuit.Transform to two-level NAND-NAND circuit.Transform to two-input NAND and inverter tree network.Perform an optimal pattern matching to obtain a minimum cost tree covering.


INPUTS NAND NAND

Previous Example: 2-Level NAND(Slide 8)


A

B

C

D

F1

F2

1P

2P

4P

3P

A Simple Technology Mapping


B

C

F1

F2

2PD

A

Cost = 24

NAND2 (3)NAND2 (3)

NAND2 (3)

NAND3 (4) NAND3 (4)

(2)

(2)

NAND2 (3)

Optimum Mapping: Convert NAND Circuit to Directed Acyclic Graph (DAG)


A

B

C

D

F1

F2

2P

4P

3P

1P

Each node is aNAND gate.(NOT ≡ 1-input NAND)

Split DAG into Trees (Forest)


A

B

C

D

F1

F2

2P

D

CB

2P

2P

A

D Cost = 24

Split Nodes With More Than Split Nodes With More Than Two BranchesTwo Branches

(Use NAND3, NAND4 Graphs)(Use NAND3, NAND4 Graphs)


≡2P 2Por F2 or F2

≡NAND4

or

Uniform Branching (1 or 2)


A

B

C

D

F1

F2

2PC

B

D

D

2P

2P

ACost = 32

Graph Matching


A

B

C

D

F1

F2

2PC

B

D

D

2P

2P

A

NAND3 (4)

NAND3 (4)

OAI21 (4)

NAND2 (3)

NAND2 (3)

(2)

(2)

Cost = 22

Nodes insertedFor pattern matching

Technology Mapping


A

B

C

D

F1

F2

2PC

B

D

D

2P

2P

A

OAI21 (4)

NAND3 (4)

NAND3 (4)

NAND2 (3)

NAND2 (3)

(2)

(2)

Cost = 22

Inverters insertedFor pattern matching

(2)

Mapped Circuit


B

C

F1

F2

2PD

A

Cost = 22NAND2 (3)

NAND3 (4) NAND3 (4)

(2)

(2)

NAND2 (3)

AOI21 (4)

Original Reference

K. Keutzer, “DAGON: Technology Binding and Local Optimization by DAG matching,” Proc. 24th Design Automation Conf., 1987, pp. 341-347.


ELEC 2200-002 Digital Logic Circuits Fall 2015 Logic Synthesis (Chapters 2-5) Vishwani D. Agrawal...

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