Efficient Multi-Ported Memories for FPGAs Eric LaForest Greg Steffan University of Toronto Computer...
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Transcript of Efficient Multi-Ported Memories for FPGAs Eric LaForest Greg Steffan University of Toronto Computer...
![Page 1: Efficient Multi-Ported Memories for FPGAs Eric LaForest Greg Steffan University of Toronto Computer Engineering Research Group February 22, 2010.](https://reader035.fdocuments.in/reader035/viewer/2022081519/56649e4a5503460f94b3eadd/html5/thumbnails/1.jpg)
Efficient Multi-Ported Memories for FPGAs
Eric LaForestGreg Steffan
University of TorontoComputer Engineering Research Group
February 22, 2010
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Parallelism in FPGAs Larger SoCs on FPGAs →Parallel Systems Parallel systems on FPGAs will need:
Queueing Data sharing Communication Synchronization
Boils down to: FIFOs Register files
We can do all these with multi-ported memories
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Multi-Ported Memory
X
X
X
X
Existing workarounds are ad-hoc, “roll-your-own”,and have limited parallelism.
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Conventional Approaches
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2W/2R Multi-Ported Memory
Doesn't exist on FPGAsAltera used to have one (Mercury)
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Stratix III Building Blocks
M9K (eg: 32 x 256)M144K (eg: 32 x 4098)
Adaptive Logic Modules RegistersLUTsAdders
Block RAMs
Flexible, but slow
Fast, but inflexible
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2W/2R Pure-ALM
Scales very poorly with memory depth
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1W/nR Replication
Multiple read portsOnly one write port
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mW/nR Banking
Multiple write ports Fragmented data
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mW/nR “Multipumping”
Multiple read/write portsNo fragmentation
Divides clock speedRead/write ordering
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Block RAMs: Simple Dual Port
ReadWrite
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Block RAMs: True Dual Port
R / W R / W
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“Pure Multipumping”
Read as banked memory (multiple reads)
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“Pure Multipumping”
Write as replicated memory (avoids fragmentation)
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Methodology Generate design variations over space
Vary # of ports, depth, type of memories 1W/2R to 8W/16R 2 to 256 elements deep Pure-ALM, M9K, MLAB, Multipumped
Wrap in testbench for timing and correctness Target Quartus 9.0 to Stratix III
No synthesis optimizations for speed or area Standard P&R effort (speed, avg. over 10 runs)
Measure area as Total Equivalent Area Expresses area in a single unit (ALMs)
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Conventional Multi-PortingPerformance
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1W/2R Pure-ALM Area vs. Speed
NiosII/f290 MHz500 ALMs
Smaller
Faster
Too big and slow!
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1W/2R Replicated vs. Pure-ALM
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1W/2R “Pure Multipumping”
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LVT-Based Multi-Ported Memories
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LVT-Based Memory
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LVT-Based Memory
Begin with oneblock RAM
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LVT-Based Memory
Replicate for two read ports
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LVT-Based Memory
Bank for twowrite ports
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LVT-Based Memory
Select bankto read from
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LVT-Based Memory
Add banklookup table
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LVT-Based Memory
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Live Value Table Operation
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LVT Operation
2W/2R, 4-deep
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W0
LVT Operation
W0
W1
R0
R1
Live Value Table
Write Addresses Read Addresses
0
1
2
3
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W0
LVT Operation: Write
W0
W1
R0
R1
42 @ 1
23 @ 3
0
Records which write port last updated a location
0
1
2
3 1
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W0
LVT Operation: Read
W0
W1
R0
R1
0
@ 1
@ 3
10
1
Steers read port to correct memory bank
0
1
2
3
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LVT Implementation
LVT remains practical because it is very narrow
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LVT Operation
Small Pure-ALM memory controlling larger block RAMs
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Advantages of LVTs
LVTs add a layer of indirection Everything operates in parallel Makes banked memory behave as consistent unit
LVTs are narrow Word width = log
2(# of write ports) < 4 bits typically
Pure-ALM, but practical size and speed
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LVT Performance
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2W/4R Pure-ALM
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2W/4R LVT-based vs. Pure-ALM
84% smaller
43% faster
412 MHzto
375 MHz
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2W/4R Multipumping
Must be careful about read/write ordering!
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Multipumping Performance
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2W/4R Multipumping
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2W/4R Multipumping
Pure Multipumping(279 MHz)
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4W/8R Multipumping
Worsens as # of ports increases
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2W/4R Multipumping
28% smalleron average
193 MHzto
174 MHz
54% slower on average
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Conclusions
Pure multipumped memories are better for memories with few ports or low speed.
LVT-based memories are faster and smaller than Pure-ALM memories.
LVT-based memories are faster than pure multipumping, but at a cost in area.
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Future Work
Pure multipumping for LVT-based memories Build banks with 2W/4R pure multipumping blocks Possible further area improvement
Relaxing the read/write order for multipumping Allows multiplexing the write ports Leaves designer to watch for WAR violations
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Thank You