https://doi.org/10.1007/s10836-019-05842-8

Efficient Built-In Test and Calibration of High Speed Serial I/OSystems Using Monobit Signal Acquisition

Thomas Moon1 ·HyunWoo Choi1 ·David C. Keezer1 · Abhijit Chatterjee1

Received: 26 April 2019 / Accepted: 26 November 2019© Springer Science+Business Media, LLC, part of Springer Nature 2020

AbstractThis paper proposes a new high-speed self-calibrating digital transmitter with the ability to deliver high quality signalsat low hardware cost. The proposed self-calibrating system performs on-line monitoring of the channel by performingmeasurements on the time-domain reflected (TDR) waveform. Unlike complex TDR instrumentation, the proposed systemhas the capability to reconstruct the reflected waveform using a single bit (monobit) sampler. Using very little hardware, aspecific feature of the reflected waveform (area over time or integral) is extracted and used to drive a signal pre-emphasisscheme that maximizes the opening of the signal eye diagram without any communication with the receiver. The absence ofsuch physical loopback significantly reduces the time and complexity of feedback based transmitter calibration techniques,especially where multiple transmission channels are concerned. Further, the proposed scheme is useful in the presence ofsingle or multiple transmission line imperfections or defects. The proposed technique is implemented via a printed circuitboard (PCB) prototype and measurement results demonstrate that it is capable of detecting defects in the digital I/O channeland adapting the channel to improve the received signal eye-diagram without direct feedback from the receiver.

Keywords High-speed digital I/O · Self-calibration · Monobit sampler · Eye-diagram

1 Introduction

Recent advances in the design of high-speed circuits haveplaced great emphasis on signal integrity across high-speedinterconnect [1]. To mitigate high-speed signal degradationand intersymbol interference (ISI), various equalizationtechniques have been considered. In the receiver front-end, continuous-time linear equalizers (CTLE) [2–4] anddecision feedback equalizers (DFE) [5–7] are commonlyemployed to compensate for signal distortion and loss.

However, tuning the equalization in the transmitter is notstraightforward and requires the use of an extra physicallink to convey signal integrity information from the receiverback to the transmitter. In [8], the optimal equalizercoefficients of the transmitter are obtained through a

Responsible Editor: B. Ghavami

� Thomas Moontmoon@gatech.edu

1 School of Electrical and Computer Engineering,Georgia Institute of Technology, Atlanta, GA 30332, USA

physical feedback line using handshaking with adaptationlogic within the receiver. In [9–12], the pre-emphasis isdetermined by estimating the channel link length. Whilethe channel link length is calculated by the time of flightmeasured by an extra physical line forming a loop in[9], an adaptive pre-emphasis calibration scheme basedon time-domain reflectometry (TDR) using time-to-digitalconverter (TDC) is proposed in [11, 12]. The techniques,however, consider the effects of channel link length onsignal integrity rather than the combined effects of linklength and impedance mismatch.

In order to achieve energy-efficient I/O communication,smart I/O management with dynamic output voltageswing is discussed in [13, 14]. The bit error rate (BER)requirement is not always necessary to be low and dependson instantaneous workload. By adaptively adjusting theoutput-voltage swing under dynamic BER constraints,one can enable energy-efficient I/O communication. Inrecent research [15–17], on-line machine learning basedpower management has been proposed. In [17], theslow convergence of conventional Q-learning algorithmsimproved by adaptively adjusting the output-voltage swinglevels of 2.5D through-silicon interposer (TSI) I/Os.Furthermore, BER analysis is performed at the receiver and

Journal of Electronic Testing (2019) 35:809–822

/ Published online: 20 January 2020

the analysis results (eye opening) need to be sent backto the transmitter to enable adaptive equalization of thetransmitted signal. In the proposed work, no informationfeedback from the receiver is necessary. Instead, thetransmitter performs adaptive signal power control bysensing the reflected TDR waveform.

Various techniques for detecting transmission linefailures have been studied. The most widely used methodis TDR or frequency-domain reflectometry (FDR) [18–23].A pulsed signal (or a high-frequency signal) is transmittedthrough the wire and the reflected signals including theinformation of the impedance mismatch or the fault areanalyzed. In [11, 24, 25], joint time-frequency domainreflectometry (TFDR) technique to improve the accuracyof TDR/FDR is proposed. However, these methods requirea high-speed arbitrary waveform generator (AWG) togenerate a chirp signal and a wideband circulator to isolatethe reflected signal from the fault. In [26], spread spectrumtime domain reflectometry (SSTDR) and sequence timedomain reflectometry (STDR) are developed. A spreadspectrum signal is injected into the transmission lines andthe observed reflected signal is correlated with a copyof the injected signal to detect failures. This approach,however, demand a pair of duplicated pseudo-noise digitalsequence generators and a correlator which is composed ofa wideband mixer and an integrator circuit. Therefore, thesemethods are not adequate and cost-efficient for diagnosingfaults in digital high-speed interconnection due to extrasignal generators and special circuitry.

In this paper, a new transient response tuning schemeis proposed for high-speed serial transceivers withoutinformation feedback from the receiver. In the proposedscheme, a full TDR waveform is reconstructed by arobust monobit reconstruction algorithm and the impedancediscontinuity causing reflections between the transceiveris detected. Once the discontinuity (fault) is detected, thesignal degradation in the receiver can be predicted andcan be compensated by pre-emphasis of the transmitter.The main objective of the proposed system is to improvethe signal integrity at the receiver without the need tominimize the reflected signal at the transmitter. As thehigh-frequency components of the signal at the receiverare often lost due to capacitive failures, emphasizing thehigh-frequency loss by pre-emphasis at the transmitter helpsto improve the received signal at the receiver. However,over-emphasizing incurs excessive power consumption at

the transmitter, and needs to be modulated carefully. Table 1provides a comparison of this work with other related workson adaptive pre-emphasis calibration.

The proposed test architecture uses field programmablegate arrays (FPGAs) for pattern synthesis and sample acqui-sition. The FPGA logic is complemented by customizedpin electronics (PE) modules including high-speed driversand comparators. As FPGAs are capable of multi-channelIOs and the PE modules are constructed using off-the-shelfcomponents, the cost of the test module is minimized andmulti-channel high-speed testing is achieved. A novel algo-rithm that reconstructs a full TDR waveform without extratiming circuitry is developed. Diagnosing multiple faults inchannel link achieves a robust channel monitoring with min-imum hardware cost. The contribution of this work can besummarized as:

– TDR based architecture: Our proposed test archi-tecture enables us to stimulate/reconstruct TDR testsignal. Opposed to the DFE approach that requires thefeedback from the receiver, the TDR approach can char-acterize the channel without any communication withthe receiver. This can reduce the test time and cost fromthe extra physical loopback.

– Monobit sampler: Our unique signal reconstructionalgorithm using monobit sampler significantly reducesthe complexity of the test system. While relaxing thecomplexity, the accuracy and the robustness of thereconstruction is achieved by the statistical estimator.

– Adaptive pre-emphasis: Characterizing the channelby reconstructing the TDR test signal allow us to predictthe eye-opening in the receiver. Hence, the transmittercan adapt the channel information by tuning the pre-emphasis strength.

This paper is an extended version of work published in [27,28] . Our previous works are limited to the basic idea ofmonobit reconstruction without the statistical enhancementproposed in this paper.

2 Proposed Test Architecture

Out prototype implementation of the proposed test architec-ture consists of a main FPGA board and a pin electronicsmodule.

Table 1 Related works comparison

[11, 12] [10] [7] This work

Architecture TDR based DFE based DFE based TDR based

Channel model Length only Length only Multi-impedance mismatch Multi-impedance mismatch

Sampler TDC Multibit ADC Multibit ADC Monobit ADC

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(a) Main FPGA board This board serves the central unitthat performs the regular high-speed I/O functionality andinterfaces with a commercial ATE system. On top ofthe basic functionality, the board also receives the highgranularity samples from the pin electronics (PE) moduleson the board and monitors the signal integrity. The FPGAcan control the parameters of each PE module so that it canadapt the response of each channel.

A floor plan of the prototype test system and aphotograph is shown in Fig. 1. The test system isconstructed on a printed circuit board that fits within the testhead of a commercial ATE, taking up two of its standardexpansion slots. On the bottom of the card are severalmulti-pin connectors that support communication buses andobtain power through the host ATE backplane. Central to thedesign is a Xilinx Kintex-7 28nm CMOS FPGA that servesas a local test controller for the card.

The FPGA performs the desired tests autonomously,without real-time interaction with the host ATE. Essentiallythe FPGA is programmed to act as a stand-alone local tester.High-speed signals are generated and received by XilinxGTX multi-Gigabit transceiver logic. The particular FPGAused in the prototype has 16 TX and 16 RX fully-differentialports, each capable of supporting signals up to 13Gbps.

Multi-pin connectors are arranged near the top edge ofthe PCB for attaching 16 of these PE modules, for a totalof 64 channels. During the development phase only four ofthe 16 PE modules were actually populated on the prototypePCB. Nevertheless, all 16 positions are shown to illustrate

(a)

(b)

Fig. 1 Main FPGA board. a floor plan and b photograph of theprototype PCB

the feasibility of scaling up to the full 64-channel testsystem.

(b) Pin electronics (PE) module While the FPGA is verygood at generating and receiving multi-Gbps serial testpatterns, it has limited ability to vary the test signal analogcharacteristics, such as voltage amplitude, offset, time-delay, signal pre-emphasis, etc. Therefore, to complementthe FPGA and provide a wider range of signal variation,PE modules are added to the signal paths. Beyond the basicfeatures, we have included a shadow-sampling circuitrythat monitors the test signal independently from the data-gathering activity of the primary receiver.

In Fig. 2, the block diagram of a PE module is shown.The patent-pending design of the PE module includes signaldrivers (Micrel SY58626L), primary samples (Comp1, Hit-tite HMC674), shadow samplers (Comp2, Hittite HMC874),serial DACs (Linear Technology LTC2656), and high-bandwidth connectors (for passing the signals between themodule and the FPGA and the DUT). The driver is capa-ble of changing the signal amplitude, DC offset and signalpre-emphasis. The driver has five-bits to control the pre-emphasis parameters: three bits select the pre-emphasisamplitude 0% (disabled), 15%, 25%, and 33%, and twoother bits selects one of four duration 60ps, 100ps, 200ps,and 400ps. The primary sampler determines whether theincoming signal from the DUTs is logic 0 or 1. By compar-ing a programmed reference level (generated by DAC), theprimary receiver produces standard logic levels for FPGA.Note that the primary comparator is a continuous com-parator that outputs either logic 0 or 1 anytime a high orlow signal is applied in the input. The driver with this pri-mary sampler complements the limited voltage range of theFPGA I/O and provides a wider voltage range of the testsignal.

The secondary sampler (a.k.a shadow sampler) is thekey component that uniquely allows us to fully reconstruct

Fig. 2 Block diagram of the proposed multi-channel testing system

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Table 2 4-channel PE moduleperformance characteristics Number of channels 4

Maximum data rate (DNRZ) 5.0Gbps

Driver rise-time(20-80%) 45ps (typical)

Driver amplitude range 100mV to 1000mV (single-ended)

Driver DC offset range −0.2V to +1.2V

Driver pre-emphasis control 5-bit digital, including amplitude and duaration

Comparator input sensitivity <10mV (typically <5mV)

Comparator range 0V to 2.5V

Transmission line bandwidth >5GHz

FPGA system clock 100MHz

the test signal. The shadow sampler is a clocked comparatorthat compares the input signal with the reference at theclock edge, such as a monobit ADC. Unlike the continuouscomparator whose output is only dependent on the input(no time-dependency), the clocked comparator outputsupdates only at the clock edge. The detailed reconstructionalgorithm using the shadow sampler will be discussed in thenext section. More detailed performance characteristics arelisted in Table 2.

3Monobit signal reconstruction

3.1 Monobit fractional equivalent sub-sampling

A waveform is reconstructed in the time-domain bytwo different approaches: real-time sampling (RTS) andequivalent-time sampling (ETS) [29]. While the RTS plotsthe samples in sequence, the ETS reconstructs the waveformby re-ordering the samples over the period of the waveform.The ETS is commonly used to scope a high-speed digitalwaveform over the RTS because the ETS can take advantageof sub-sampling due to the periodicity of the digitalwaveform whereas RTS can suffer from the aliasing issue.

The conventional ETS varies the sample delay to sweepacross the waveform. The sample delay is sequentiallyincreasing by �T to sample across the waveform. However,the resolution of the reconstruction is limited by theminimum amount of the sample delay. In [27], fractionalequivalent-time sampling (FETS) is introduced. Comparedto the conventional ETS where both sampling clock and theinput share the same frequency or an integer relationship,the FETS uses a frequency offset between the samplingclock and the input waveform. In Fig. 3, the conventionalETS and the FETS are compared. In the example ofthe conventional ETS, the sampling clock has the samefrequency with the input waveform (Ts = Tc). In general,the frequency of the input waveform (Tc) is integer multipleof that of the sampling clock (Ts). On the other hand, thesampling frequency in FETS has fractional relationship with

the input waveform. Because of the fractional relationship,a periodic phase offset is created over the input waveform.

To generalize, we define the frequency relationshipbetween the sampling clock (fs = 1/Ts) and the inputwaveform (fc = 1/Tc) as following

fs = n

mfc (1)

where m and n are coprime. Then, the total numberof the sampling time-location (or the resolution of thereconstruction) is n. Thus, the time-resolution of thereconstruction is configurable by changing the frequencyrelationship. There are infinitely many choices of thefrequency relationship given a time-resolution because m

is independent with the resolution. The sequence of thesampling time-location is defined as

s[k] = mod (kTs, Tc) (2)

The sequence, s[k], contains a relative phase informationof k-th sample. When the sampling clock and the inputwaveform hold the relationship as (1), the sampling time-location can be expressed in integer rather than in realnumber. The definition can be re-defined as

s[k] = mod (km, n) (3)

In the proposed testing system, a clocked-comparatorperforms as a monobit receiver. The input waveform and thethreshold voltage level are compared at the rising edge ofthe sampling clock. When the input signal is higher than thethreshold at the clock edge, the comparator outputs a logicone. Otherwise, the comparator outputs a logic zero.

The reconstruction by monobit sampler is achieved bythe combination of FETS and varying the threshold level. Asdiscussed in earlier, the phase of the sampling clock sweepsacross the input waveform. In Fig. 4, 30 different samplingpoints are formed by 6 threshold levels and 5 clock edges(n = 5) as an example. Note that the phase of the sampling-clock-edge is periodic with n but the sequence does nothave to be in order. The threshold level is sequentiallyincreased by every n clock-cycles. The output logic of thecomparator is sampled and stored in FPGA corresponding

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Fig. 3 Conventional ETS(above) and fractional ETS(below)

to the sampling point. In Fig. 4, the output logics areshown for a square waveform. The figure illustrates that theoriginal waveform seats between the boundary of the logic‘1’ and ‘0’. One of the naive approach to reconstruct thewaveform is taking ‘middle’ value of the logic boundary. Inthis example, the reconstructed waveform by this approachwill be {0.5, 0.5, 2.5, 4.5, 4.5}. However, a robust signalreconstruction algorithm is desired in the presence of whiteGaussian noise in the input waveform and the thresholdvoltage and jitter noise in both of the input waveform and

Fig. 4 Monobit subsampling

the sampling clock. In the next section, a robust signalreconstruction algorithm based on the proposed monobitFETS is described.

3.2 Robust monobit reconstruction

Unlike a multi-bit resolution ADC, a monobit receiverprovides boolean-type information whether a waveform isgreater or less than a given threshold value. We first assumethat the sample noise is white Gaussian. For simplicity’s

Fig. 5 The threshold levels, the original signal level (red cross line),and its noise distribution

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sake, we fix the sampling-clock-edge and only considerthe samples given by different threshold levels. The inputwaveform in the presence of noise is described as

Yi ∼ N(x, σ 2) (4)

where x is the original input waveform and σ is the standarddeviation of the white Gaussian noise. The independent andidentically distributed (i.i.d.) random samples Y1, Y2, ..., YN

can be thought as samples from a multi-bit resolution ADC.In monobit receiver, however, the outcome of the samples isboolean. Thus, the random sample of monobit receiver is

Zi ={0 , Yi < βi

1 , Yi ≥ βi(5)

where βi is the i-th threshold level. Fig. 5 shows an exampleof the waveform at x with the normal distributed noise.Let N-number of the observed sample values be D =[d1, d2, ..., dN ], di ∈ {0, 1} and the parameters to beestimated be θ = {x, σ 2}.

An intuitive and naive way to estimate the originalwaveform is taking the middle of the min/max threshold ofthe logic ‘1’ and ‘0’. In Fig. 4, one can find that the originalwaveform lies between the minimum threshold of the logic‘0’ (β2) and the maximum threshold of the logic ‘1’ (β4) foreach sampling time-location. The estimation of x using themin/max threshold is

x̂min/max = (maxZi=1

βi , minZi=0

βi )/2 (6)

The above estimator, however, only exploits two values,the minimum threshold of the logic ‘0’ and the maximumthreshold of the logic ‘1’. Hence, the priori informationabout the noise probability distribution is not incorporatedin the estimator. To include the noise probability distribu-tion, the maximum likelihood estimator (MLE) is adapted.The likelihood function is defined as

L(θ) = Pr(D|θ) (7)

= Pr(Z1 = d1|θ) Pr(Z2 = d2|θ) · · ·Pr(ZN = dN |θ) (8)

=N∏

i=1

Pr(Zi = di |θ) (9)

=N∏

i=1

Pr(Yi < (−1)di βi |θ) (10)

The likelihood function states that the probability of theobservations (D) given the parameter (θ ). Note that theobservations give us the one-sided range of the randomsamples. Therefore, the likelihood function is composed ofthe cumulative distribution function (CDF) of the normaldistribution. Since the natural log function is one-to-one andmonotonically increasing, it is more convenient to use thelogarithm of the likelihood function defined by

lnL(θ) =N∑

i=1

lnPr(Yi < (−1)di βi |θ) (11)

Fig. 6 a The boolean outputs ofthe comparator across thethreshold levels b The logarithmof the likelihood function withrespect to mean and standarddeviation. c The projectedlogarithm likelihood function

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The maximum likelihood estimator (MLE) of θ is thevalue of θ that maximizes lnL(θ).

θ̂MLE = argmaxθ

lnL(θ) (12)

As there does not exist a closed form of the CDF for thenormal distribution, the MLE of θ is found by a numericalapproach. In our case, the CDF of normal distribution canbe easily evaluated by the standard normal distribution tableor any computer tools for statistics. Consider an examplewith Yi ∼ N(0, 1). The random samples are evaluated withN = 100 different threshold levels (β) linearly spaced by0.1 and centered at 0. Fig. 6a shows the boolean outcomesof the comparator. Since there are two parameters (x, σ )to be estimated, the likelihood function is evaluated bysweeping both parameters. Figure 6b shows the logarithmof the likelihood function with respect to x and σ . In thisexample, the maximum value is at the point of x̂ = 0and σ̂ = 1.05. The result shows that the MLE gives veryclose estimations to the true values. In Fig. 6c, the same

results are projected across σ̂ . As one can see, the plot hasthe maximum around x̂ = 0 for each σ̂ . As we are moreinterested in estimating x than σ , this observation suggestthat the MLE of x is not too sensitive to that of σ . Inother words, we may compute the MLE over one parameter(x) by fixing the other (σ ) at an arbitrary value. However,choosing a fixed σ requires careful considerations becauseoverestimated σ can force the likelihood function to be flatover x and results in a mislead estimation. For example inFig. 6c, the likelihood function with overestimated σ (1.5)becomes flatter than the other values of σ (0.5 and 1). Whenit is extremely overestimated, finding the peak of the curvewill become less accurate.

In Fig. 7a, a clock waveform as TDR stimulus issimulated with noise and jitter. The waveform has 1Vamplitude with noise of standard deviation σ = 0.08. Thereconstruction waveforms by min/max and MLE are shownin Fig. 7b. Both of the reconstructions are fairly close tothe original waveform but MLE has closer reconstructionto the original. The mean squared error between the

Fig. 7 Eye-diagram of the simulated input waveform: a clock signal and b PRBS-3 (7-bit period). b and d The reconstructions by min/max andMLE. c and f The mean squared error comparing min/max and MLE

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Fig. 8 An example of thechannel with multiple capacitivefaults

reconstruction and the original waveform is comparedin Fig. 7c. The bar graph provides us that MLE canreduce the error more rapidly than min/max estimationwith the accumulated samples. During a single iteration,the waveform is reconstructed using the samples over thesampling time and the threshold level (i.e. 5-by-6 = 30samples in Fig. 4). In Fig. 7d-f, a PRBS with 7-bit periodis simulated and reconstructed. The two simulation resultshow that 1) the monobit reconstruction is able to recoverthe signal regardless of the waveform and 2) MLE is morerobust estimator than the min/max estimator. Note that anyperiodic waveform can be reconstructed. We illustrate aclock waveform for the sake of simplicity. MLE gives abetter result because min/max estimation only uses the twomin/max samples which are rarely updated over the timewhile MLE exploits all the samples. Therefore, the sameresult is expected regardless of the shape of the originalwaveform.

4 Adaptive Pre-emphasis by TDR

We consider a specific problem of monitoring multiplefaults in a transmission line using time domain reflectom-etry (TDR) approach and tuning the pre-emphasis of trans-mitter to compensate the degradation of the eye-diagram atthe receiver. TDR is a well-known technique in which aknown signal is launched to propagate down a transmissionline or a wire. Any reflected waveform from a fault is moni-tored to detect the faults in the line. We implement the TDRtechnique launching a step digital waveform, reconstruct thereflected waveform and finally detect the faults.

The faults are categorized as hard faults and soft faults.The hard faults refer to open or short circuits and results inan abrupt changes of the TDR waveform. An open-circuitedline doubles the incident waveform and a short-circuited linecancels the incident waveform. Therefore, detecting hardfaults in a point-to-point line is evident.

On the other hand, any faults other than open or shortcircuits can be classified into soft faults. Soft faults resultfrom a spatially continuous variations of certain parametersof the transmission line or capacitive/inductive impedancediscontinuities due to connectors or vias. In this paper,the considered soft faults correspond to capacitive andinductive impedance discontinuities. When a single faultis assumed, the fault can be diagnosed by a closed form[30–32]. However, locating and measuring multiple faults

in the transmission line is challenging because of multiplereflections and degradation of the incident signal as itpropagates through the multiple faults. To resolve theimpedance profile of a nonuniform transmission line, [33,34] proposed a recursive computation method. This method,however, has stability issues with general incident signalother than step-function. Moreover, these TDR analysisalgorithms require the computational burden that the real-time adaptation is not applicable.

In this section, a new adaptive pre-emphasis self-calibration using TDR waveform is proposed and acomputer simulation is shown to prove its concept. Thepre-emphasis strength is self-calibrated by monitoring thechannel using the monobit signal acquisition in the previoussection. Thus, the calibration is achieved without any extrafeedback line from the receiver.

4.1 Reflection vs Rise-time vs Eye-opening area

The soft faults are assumed to be one or more in the channelas shown in Fig. 8.

A computer simulation by Advanced Design System isperformed for a single capacitive fault. In Fig. 9, the TDRwaveforms (or the waveforms at the transmitter) and thewaveforms at the receiver are shown with different amountof capacitors in the channel. A larger capacitor generatesa stronger reflection at the transmitter and a slower rising-time at the receiver. The lagging effect on the receiver due tothe impedance mismatch degrades the signal integrity suchas eye-diagram. Therefore, monitoring the channel beforetransmitting the data and adapting the pre-emphasis willenhance the transceiver performance. Note that the rising-time at the transmitter also affects the rising-time at thereceiver. In Fig. 9a, the incident step waveform is a rampsignal with 24ps rise-time(20-80%). The incident waveformwith doubled rise-time (48ps) is illustrated in Fig. 9b.

The amount of the reflection can be measured byintegrating the absolute value of the reflected waveform as

α =∫ ∞

0|Vtdr (t) − Vref (t)|dt (13)

where Vref is the TDR waveform without any reflections.The ratio of the rise-time at the receiver (RTr) and therise-time at the transmitter (RTt) is denoted by ρ. Therelation between the ratio (ρ) of the rise-time and theintegral of the reflection is plotted in Fig. 10. It is shownthat the two parameters are approximated in monotonic

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Fig. 9 The TDR waveform (left)and the waveform at the receiver(right) with various soft-faultsfor a 24ps RTt and b 48ps RTt

relationship. As the impedance mismatch is larger, thestronger reflection will occur. The impedance discontinuityresults in degradation of the rise-time at the receiver.In Fig. 11, the relationship is validated in multiple-faultscenario. A combination of two capacitors are chosenrandomly in the range of 0.5pF and 3pF. The figure showsthat the monotonic relationship still holds in the multiple-fault case.

An eye-diagram is an intuitive and easy metric to evaluatethe performance of a digital signal. As the eye-diagram is usu-ally obtained by overlapping the digital signal over one or twobit period (unit interval), a significant amount of sam-ples and computation time are required to determine a fulleye-diagram, which is not suitable for real-time adaptation.

In Fig. 12, the eye-diagram at the receiver and its eye-opening area are shown. In this paper, the eye-opening area

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Fig. 10 The relationship between the integral of the reflectedwaveform and the rise-time ratio (RTr/RTt) with various RTt

is defined by finding the 7 longest vertical lines equallyspaced over the unit interval (UI) and contained in the closedeye area. Then, the sum the area of the rectangulars whoseheights are the vertical lines is the eye-opening area.

The relationship between the rise-time (RTr) and the eye-opening area is shown in Fig. 13. It shows the linear modelfits the data well. The strength of the pre-emphasis can bedetermined depending on the initial condition (eye-openingarea without pre-emphasis) and the required complianceeye-opening.

4.2 Decision on pre-emphasis

The optimal pre-emphasis can be found iteratively bymeasuring the reflected TDR signal and increasing thepre-emphasis strength until the predicted eye-opening areameets the minimum required eye-opening area. We first startwith the minimum pre-emphasis strength and compute thereflection α by measuring the reflected signal (this is doneby the monobit reconstruction in the previous section). Onceα is obtained, one can estimate the rise-time at the receiver(RTr) using the linearity shown in Fig. 10. Notice that the

Fig. 11 Scatter plot of ρ vs α comparing the single-fault scenario andthe multiple-fault scenario

Fig. 12 Defined eye-opening area and rise-time (RTr)

rise-time at the transmitter (RTt) can be measured throughthe reflected TDR signal (See Fig. 9). The next step is usingthe linearity between the RTr and the eye-opening area asshown in Fig. 13. The estimated eye-opening area is thencompared with the required compliance eye-opening area.If the condition does not meet, we increase the pre-emphasisstrength to compensate the signal degradation. Once the eye-opening meets the requirement, we choose the current pre-emphasis. Thus, the output pre-emphasis strength consumesthe minimum power that satisfied the compliance. Thesummary of the algorithm is shown in Algorithm 1.

Fig. 13 The relationship between the RTr and the eye-opening area

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Fig. 14 A test channel board

5 Hardware results

We use a test channel board that emulates transmissionline faults. On a transmission line, a combination of shuntcapacitors or series inductors can be soldered as shownin Fig. 14. In Fig. 15, TDR waveforms obtained bythe proposed method are compared with Agilent 81600Dsampling oscilloscope with a TDR module. In the casewithout fault (top), there are two voltage drops becausethe two SMA connectors act as capacitor. In the casewith two 1pF capacitors (middle), the reflection due to thefirst capacitor appears after the first SMA connector. Thereflection due to the second capacitor overlaps with the onedue to the second SMA connector. In the last case witha single inductor, the reflection waveform reinforces theincidence waveform. One of the reasons all the drops by theproposed TDR is shallower than the Agilent TDR is becausethe rise-time of the TDR signal is slower (45ps) than theAgilent TDR (typically less than 10ps). In addition tothe rise-time, the Agilent TDR generates the step-functionsignal with less over-shoot and oscillation than the proposedTDR can do. Due to the lack of high-transition and thedistortion in the TDR signal by the proposed TDR, thereflected signal that causes the drops will be less sharper.Figure 15, however, shows that the overall trend of theTDR waveform by the proposed TDR and the commercialequipment is fairly close.

As discussed in the previous section, the relationshipbetween the integral of the reflected waveform and the rise-time at the receiver (RTr) (Fig. 10) and the relationshipbetween the RTr and the eye-opening area are bothapproximated in linear model. Therefore, we can expect theintegral of the reflected waveform and the eye-opening areacan be linear, too.

Fig. 15 TDR waveforms by Agilent and by proposed work

In Fig. 16, the measured TDR reflection area andthe eye opening area are plotted together. In this figure,we train three different pre-emphasis; no pre-emphasis,medium pre-emphasis (15% amplitude and 200ps duration),and maximum pre-emphasis (33%, 200ps). The train onthe pre-emphasis is necessary because the characteristicsof the pre-emphasis is dependent on its Tx circuit andevery manufacturer and component has its own response.Although the linearity is distorted by the pre-emphasis andthe measurement errors, the TDR reflected area is still areasonable estimator for the eye-opening area. Assumingan eye-opening compliance is given (33 in this figure),an optimal pre-emphasis can be chosen by measured TDRreflection area. In low impedance mismatch region (pt1and pt2), it is unnecessary to turn-on pre-emphasis becausethe eye-opening is already satisfied the compliance. As theimpedance mismatch increases, the pre-emphasis is neededto compensate the eye closing. However, the pre-emphasisdoes not have to be the maximum strength if any mediumstrength can achieve the compliance (pt3-5). Obviously,the maximum strength may not be even enough to meet

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Fig. 16 Measured TDR refleaction area and eye-opening area

the compliance for the worst case (pt6). Table 3 showsthe power consumption of the three pre-emphasis levels.As described in the example, the optimal pre-emphasis ischosen instead of the maximal strength in pt1-pt5, whichcan save the pre-emphasis power consumption.

6 Conclusion

In this paper, a new high-speed digital transmitter with aself-calibration system is proposed. The TDR waveformof the transmitter is measured by the proposed monobitsignal reconstruction algorithm. A high-resolution of thetime-domain can be achieved by choosing a right samplingclock speed. As the reconstruction algorithm exploits theskew between the sampling clock and the input signal,the sampling clock speed can be a low frequency. Theaccuracy of the reconstruction is enhanced by the MLEestimator for the monobit receiver. As a full TDR waveformis reconstructed in high resolution, multiple soft faults in thechannel can be detected. Consequently, a smart decision onthe strength of the pre-emphasis can be made. The proposedarchitecture is verified by an FPGA prototype board and

Table 3 Power consumption for pre-emphasis of driver at 3.2GBPSPRBS

Disable 15%, 200ps 33%, 200ps

Power 0mW 21mW 34mW

pin electronics modules. The hardware result shows thatthe optimal pre-emphasis saves the power consumptioncompared to the maximal strength.

Acknowledgments The authors wish to thank Te-hui Chen for his helpwith the hardware development in this paper.

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Publisher’s Note Springer Nature remains neutral with regard tojurisdictional claims in published maps and institutional affiliations.

Thomas Moon received the B.S. degree in electrical electronicengineering from Pohang University of Science and Technology(POSTECH), Pohang, Korea, in 2008, and the Ph.D. degree inelectrical and computer engineering from Georgia Institute ofTechnology, Atlanta, in 2015. Between 2015 and 2017, he workedat IBM in Burlington, Vermont where he developed mmWave testequipment as a principle development engineer. He is a post-doctoralresearcher in University of Illinois at Urbana-Champaign. His currentresearch interests include wireless sensing and communication inmmWave.l

Hyun Woo Choi received the B.S. degree in electrical engineeringfrom Korea University, Seoul, Korea, in 2004, and the Ph.D. degreein electrical and computer engineering from the Georgia Institute ofTechnology, Atlanta, GA, USA, in 2010. He is a Senior Engineer atNvidia Corporation, Santa Clara, CA, USA, and an Adjunct FacultyMember with the School of Electrical and Computer Engineering,Georgia Tech. His current research interests include design-for-test,built-in self-test, diagnostics and physical characterization of advancedsilicon and post-silicon devices.

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Professor Keezer was born in Detroit, Michigan and grew up inMichigan, Maryland, New York, and California. He attended theUniversity of California, Berkeley where he completed his BA inPhysics and Applied Mathematics in 1978.He began his graduatestudies at Caltech where he earned his MS degree in Applied Physicsin l979 and continued work towards the Ph.D. In 1980 he movedto Carnegie-Mellon University where he completed the Ph.D. in1983. His studies focused on domain wall dynamics in magneticbubble memory devices. Between 1983 and 1989 he worked at HarrisCorporation in Melbourne, Florida where he developed and appliedelectrical test methods to Very Large Scale Integrated Circuits. Heearned an M.B.A. in 1985 from the Florida Institute of Technology. In1989 he began work at the University of South Florida as an AssociateProfessor of Electrical Engineering. Dr. Keezer joined the GeorgiaTech faculty in l995 and continues to teach classes in Electrical andComputer Engineering and conduct research on the design and testof high performance logic systems. His hobbies include playing thetrumpet and numerous sports activities.

Abhijit Chatterjee is a professor in the School of Electrical andComputer Engineering at Georgia Tech and a Fellow of the IEEE. Hereceived his Ph.D. in electrical and computer engineering from theUniversity of Illinois at Urbana-Champaign in 1990. Dr. Chatterjeereceived the NSF Research Initiation Award in 1993 and the NSFCAREER Award in 1995. He has received six Best Paper Awards andthree Best Paper Award nominations. His work on self-healing chipswas featured as one of General Electrics key technical achievementsin 1992 and was cited by the Wall Street Journal. In 1995, he wasnamed a Collaborating Partner in NASAs New Millennium project. In1996, he received the Outstanding Faculty for Research Award fromthe Georgia Tech Packaging Research Center, and in 2000, he receivedthe Outstanding Faculty for Technology Transfer Award, also givenby the Packaging Research Center. In 2007, his group received theMargarida Jacome Award for work on VIZOR: Virtually Zero MarginAdaptive RF from the Berkeley Gigascale Research Center (GSRC).

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