Effect of Wafer Back Grinding on the Mechanical Behavior of

Copyright © 2008 Year IEEE. Reprinted from IEEE ECTC 2008. 27 - 30 May 2008, Florida USA.. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of Institute of Microelectronics’ products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to [email protected].

Effect of Wafer Back Grinding on the Mechanical Behavior of Multilayered Low-k for 3D-Stack Packaging Applications

V. N. Sekhar*, Lu Shen#, Aditya Kumar, T. C. Chai, Lee Wen Sheng Vincent, Wang Xin Lin Sandy, Xiaowu Zhang , C. S. Premchandran, V. Kripesh, John H. Lau

Institute of Microelectronics 11, Science Park Road, Science Park II, Singapore 117685

#Institute of Materials Research and Engineering 3, Research Link, Singapore 117602

*E-mail: [email protected] , Tel: +65-67705383, Fax: +65-67745747

Abstract To study the effect of back grinding on the mechanical

properties of the active side of the die, low-k stacked wafers were grinded to four different thicknesses of 500 µm, 300 µm, 150 µm, and 75µm by using a commercial grinding process. Nanoindentation and nanoscratch tests were performed using the Nanoindenter XP (MTS Corp. USA) on both the normal (no back grinding) and back grinded samples to analyze the failure loads, modulus, hardness and adhesive/cohesive strength, of the low-k stack. It is found that the back grinding process enhances the mechanical integrity of low-k stack as the back grinded low-k stack exhibited in terms of the higher failure load and cohesive and/or adhesive strength of grinded low-k stack than the normal low-k stack. The TEM cross-section analysis showed that the interfaces in the low-k stack of normal sample are wavy, whereas the interfaces in the low-k stack of back grinded samples are even, especially at the Black Diamond region. Significant densification of BD films is observed in the case of back grinded sample. Based on these results, it is believed that the thermo-mechanical stresses applied and/or generated during wafer back grinding process affect the microstructure and enhance the mechanical strength of the low-k stack.

1. Introduction Wafer back grinding is one of the key technologies which

paving the way to high performance three-dimensional (3D) electronic packages. The, 3D packaging is getting more and more popular because of its innovativeness, high performance and functionality, and smaller in size of the final product. The major applications of the 3-D packaging include digital and mixed-signal electronics, wireless, electro-optical, MEMS and other integration technologies. At this juncture, the key technologies supporting the 3-D packaging, are as: through silicon vias (TSVs), wafer thinning/back grinding, precision alignment of wafer to wafer or chip to wafer, and wafer to wafer or chip to wafer bonding [1]. Among these key technologies, wafer thinning plays vital role in 3D packaging integration, as it allows to accommodates or stack more dies in one package and ultimately results in the reduction of package size. Besides the reduction of package size, the stacking of thinner chips provides many other advantages, such as, more functionality per package and improved heat dissipation. Electronic packaging industry has to put a lot of R&D efforts and spend millions of dollars on the wafer thinning technologies as there is no manufacturing technology

available for directly producing the ultra-thin wafers [2]. That is why in the recent past years, many wafer thinning methods, such as mechanical grinding, chemical mechanical polishing (CMP), wet etching and atmospheric downstream plasma (ADP), dry chemical etching (DCE) have been evolved. Usually all commercially available grinding systems perform thinning action in two stages as 1) coarse grinding using 350-500 grits and 2) subsequent fine grinding using 2000-3000 grits [2]. There are some problems associated with thinned wafers like, thin wafer handling and low die strength and to date no concrete solution has been established to avoid these problems. Poor die strength of the thinned wafers is mainly due to the scratches, crystal defects, and stresses formation during mechanical back grinding [3]. So far many researchers have extensively studied wafer thinning/back grinding processes in terms of die strength by assessing the quality of the grinded surface [4-6]. Besides the degradation of die strength due to small thickness of the thinned wafer, some researchers have found sub-surface damage due to back grinding [7]. Blech et al have studied the effect of backside mechanical grinding on the wafer deformation [10]. Hoh Huey Jiun et al studied the die fracture strength by considering the surface roughness of the thinned surface and the amount of removal thickness by stress relief methods [6]. In addition to surface roughness of the thinned wafer, grinding direction has significant effect on the die strength [11]. Singulation of thinned wafers always pose problem as it induces the chipping and rough edges on the chip during the dicing processes. Chen et al have found dicing before grinding (DBG) method as a good solution for ultra-thin chip applications and it enhanced chip strength around 10-15% [5]. In back grinding processes it is impractical to retain its native die strength, but it can be controlled to some extent by employing the stress relief methods after grinding processes. The commonly used stress relieving methods include wet chemical etching, dry or plasma etching, dry polishing and chemical mechanical polishing (CMP) [8-9].

In the recent years, many researchers have extensively assessed the quality of the back grinding processes via die strength evaluation. Die strength of the thinned wafer can be evaluated by using the different techniques like three point bend test, four point bend test, ball on ring test, ball breaker tests and ring-on-ring tests. And it greatly influenced by several parameters like surface roughness/finish, degree of thinning, stress relief processes, quality of the dicing edge [5-10]. But the literature/studies available related to the effect of the grinding processes on the active side of the die/chip is almost nil/very scarce, and this necessitates a focused study

978-1-4244-2231-9/08/$25.00 ©2008 IEEE 1517 2008 Electronic Components and Technology Conference

on the effect of wafer back grinding on the active side of chip. For the first time we have studied the effect of the back grinding processes on the mechanical behavior of the active side of the low-k stack by using the nanoindentation and nanoscratch techniques combined with TEM (Transmission Electron Microscopy) analysis. Usually active side of the chip is a few microns in thickness, and it can not be studied using those methods which are being used for conventional die strength evaluation. Therefore, we have chosen sophisticated methods like nanoindentation and nanoscratch techniques for the present study. Nanoindentation and nanoscratch tests have been carried out on both normal (no back grinding) and back grinded stacks, to study the failure loads, modulus, hardness and adhesive/cohesive strength. Generally after back grinding process it is observed that the die strength of the thinned chip decreases significantly. However in the present study, we have noticed an improvement in the mechanical behavior of the back grinded low-k stack. Thus, we can believe that the back grinding process lowers the die strength in one way, but on the other hand it improve the mechanical integrity of the low-k stack.

2 Experimental 2.1 Test vehicle fabrication

Test vehicles used in this study is a multilayered low-k stack of 15 different thin films comprising SiN, USG, Blok (SiC), BD (Black Diamond TM, low-k), as shown in Fig. 1. All samples were prepared on 8” Si(100) wafer in a semiconductor processing clean room of class 1000 environment. Test structure employed in this study is exclusively designed to study the BD (low-k) integrity and it resembles the Cu/low-k structure of the three metallizations. So the structure having three BD low-k layers at different levels according to the BEOL (Back End of the Line) interconnect design specifications and it does not have any copper metal lines. The total thickness of the multilayered low-k stack in test vehicle is around 3400 nm. The main intention in preparing the test vehicle without metal line is that in the reality low-k stack regions are more vulnerable than the regions with metal lines. Hence present study gives an outlook about the response of the low-k test structures during back grinding process. 2.2 Backgrinding process

Wafer thinning of the low-k stacked wafers were carried out by using commercial back grinding system (Disco Corp. Japan). In thinning process, first the coarse grinding was done by using grit #300, then fine grinding was done by using #2000 and finally the dry-polishing was carried out to remove the subsurface damages. The dry polishing was a special stress relief process developed by Disco Corp. Japan, by using grit #8000 without using any chemicals. The main objective of employing this method is to offer superlative stability to back grinded wafers [12]. 2.3 Nanoindentation testing

Nanoindentation is a powerful mechanical characterization technique which is similar to conventional hardness testing method, but it is performed on much smaller scale using the special equipment called Nanoindenter. This method involves essentially of indenting the material of

interest whose mechanical properties are unknown with the another material (called as indenter) whose properties are known. The unique advantage of nanoindentation technique over conventional hardness technique is that both hardness and modulus can be easily extracted from the nanoindentation curve [13]. Besides these properties it can also determine residual stresses, elastic-plastic behavior, creep, relaxation properties, fatigue and fracture toughness. In this study, nanoindentation tests were performed on Nano Indenter® XP (MTS Corp. USA) with continuous stiffness measurement (CSM) attachment and Berkovich indenter. This CSM attachment has unique advantage of providing mechanical properties as a function of penetration depth. In nanoindentation experiment it is carried out by applying a harmonic force at relatively high frequency (45 Hz) to increase load without complete separate unloading cycles. The high frequency used in the CSM method allow avoiding obscure effects of the tested samples like creep, viscoelasticity and thermal drift.

Fig. 1 Multilayered (15 layers) low-k stack test vehicle.

In nanoindentation test method load applied on the sample and corresponding indentation depth is continuously monitored and recorded as load-displacement curve. Without imaging the hardness impression on the tested sample, both hardness and elastic modulus can be directly extracted from load-displacement curve by using the Oliver and Pharr method [13]. Three important parameters of the load-displacement curve play vital role in assessing the mechanical properties and they are as; 1) the maximum load, Pmax, 2) the maximum displacement, hmax and 3) contact stiffness from initial loading curve S=dP/dh. The accuracy and repeatability of the properties depend mainly on the how well these values are measured during nanoindentation tests. The hardness (H) and elastic modulus (E) can be determined by using the following equation developed by Oliver and Pharr [13],

~3.4µm

1518 2008 Electronic Components and Technology Conference

dhdP

AE

max2

121π

ν=

− (1)

and

max

max

AP

H = (2)

Where υ = poisson’s ratio, dP/dh = intial slope of the indentation unloading curve, Pmax = maximum load, and Amax =projected contact area at the maximum load. For a perfect Berkovich indenter, projected area A can be

calculated by 256.24 chA = (3)

Where, ch is true contact depth.

2.4 Nanoscratch testing Adhesion strength of film-substrate system is mainly

defined by the interfacial bond strength and solely depends on the interfacial properties. The interactions at the interface of film-substrate system may be chemical, electrostatic or vander waals type. Empirically, adhesion strength is the stress/load required to detach the thin film from the substrate. Till today, numerous techniques have been developed for the measurement of the adhesion of the film-substrate system [14], but among them nanoscratch technique is widely being used technique to determine the adhesion/cohesion strength of the thin film -substrate system [15]. In the present study all nanoscratch tests have been performed on the Nano Indenter® XP by using the nanoscratch attachment. A diamond stylus has been used as the scratch indenter and it has been scratched over the low-k stack system under ramp loading condition until some well defined failure is observed. The load at which system fails is termed as the critical load (Lc) and in the current study adhesion/cohesion strength is reported in terms of the well defined critical load, Lc. For each sample, at least five tests have been conducted and all tests showed good repeatability. For scratch test, conical diamond indenter of 5 µm was used as it has uniform facing to all directions. The main advantage of using the conical diamond indenter is that it is symmetrical at all alignments, which removes directionality effect imposed by the pyramid type tips [17]. The diamond stylus is scratched over the low-k stack for a length of 500 um, under ramp loading condition from 0 to 250 mN. All tests were performed with a constant scratch velocity of 1µm/s. 3. Results and Discussion 3.1 Failure load, Hardness (H) and Elastic modulus (E)

In this study, failure loads, hardness (H) and elastic modulus (E) is computed by analyzing the nanoindentation load-displacement curves. Fig. 2a shows the nanoindentation load-displacement curves of normal (no back grinding) and back grinded low-k stacks (BG-500, 300, 150 &75 µm). A typical deformation pattern of an elastic-plastic sample during and after nanoindentation testing is shown in Fig. 2b, where

‘P’ is the applied load and ‘h’ is the displacement in to sample surface.

Fig.2 (a) Typical load-displacement curves for all samples

(b) schematic of specimen surface geometry in indentation testing (c) Nanoindentation loads at different contact depths

for normal and back grinded stacks

At least ten nanoindentation tests were performed on each sample system and all are exhibiting good repeatability. The Poisson’s ratio of the low-k stack systems is maintained around 0.2. From Fig. 2a, it is obvious that the normal stack showing pop-in event (failure load/fracture strength of the stack) at lower loads and indentation depths, when compared

a

b

c


to the back grinded stacks. These pop-in events in the nanoindentation curve are resulting from the film cracking and delamination of the stack in the form of blisters [16]. Normal stack failed at ~ 456.25 mN load and 2422.41 nm indentation depth, whereas back grinded stacks failed in the range of 482-661mN load and 2405-2979 nm indentation depth. The fracture load and depth values of all types of samples have been summarized in the Table. 1 and Fig. 7. Fig. 3 shows the optical images of the residual nanoindentation impressions of the normal and back grinded stacks. From the nanoindentation curves and optical imaging analysis it is clearly evident that the nanoindentation response of the normal and back grinded stacks is different in terms of failure load and depth. Normal stack and BG-500µm show extensive delamination and chipping, whereas other back grinded stacks (BG 300, 150, 75 µm) show delamination blister and this behavior is in good agreement with the nanoindentation pop-in event. BG-500µm exhibits the mixed response as it shows chipping-off during nanoindentation and moderate pop-in failure load of 482.17 mN and this might due to the moderate degree of back grinding. In case of the other back grinded stacks (BG 300, 150, 75 µm), even higher nanoindentation loads are not able to damage/chip-off the low-k stack and cause interfacial delamination only. Fig. 2c shows the nanoindentation loads at different indentation depths as a function of wafer thickness (normal and back grinded stacks).Indentation loads at different contact depths 200, 500, 1000, 1500 and 2000 nm before the failure of the stack have been compared mainly to understand the deformation behavior of the low-k stack for normal and back grinded samples. No significant difference in nanoindentation loads at different contact depths observed mainly due to that the low-k stack is highly brittle and exhibits huge elastic deformation before failure of the stacks. However from Fig. 2a, significant difference is observed in case of the failure loads (as pop-in events) of the normal and back grinded stacks.

One common feature is observed among the normal and back grinded stacks is that the failure of the stack is occurring in the low-k region. Normal stack and BG-500 µm exhibit failure at the middle low-k region, BD2 (~2400nm) and other back grinded stacks fail at the bottom low-k region, BD1 (2800-2900 nm). No significant difference in fracture strength (pop-in event) is observed among BG-300, 150, and 75 µm back grinded stacks and all these grinded stacks are show higher facture strength than the normal stack and BG-500µm. Accordingly the increase in failure load depends on the degree of the back grinding, but not much difference is observed when the wafers have been grinded to 300, 150 and 75 µm. The main reasons for similar failure load for all the other back grinded stacks could be a) not much change during back grinding processes for BG-300, 150, and 75 µm, b) nanoindentation equipment resolution may not be capable of sensing small differences among the back grinded stacks, c) back grinding process may occur at constant loads for higher degree of back grinding. After back grinding, the strength of the low-k stack is enhanced, mainly in terms of nanoindentation load and indentation depth and this increase is understood mainly due to the application of mechanical

pressure and thermal stresses during back grinding action. These back grinding pressures or loads may improve the adhesion, especially Vander walls forces at the multilayered interfaces and cause the densification of the individual films of the stack. It is being investigated by many researchers in the packaging field that the back grinding processes are deteriorating the die strength, but this is not the same phenomenon with the active side of the chip stack.

Fig. 3 Optical images of residual nanoindentation

impressions of (a) normal and (b), (c), (d), (e) back grinded samples.

Fig. 4 a-b shows the hardness and elastic modulus as a function of the indentation depth for normal and back grinded stacks measured by using the nanoindentation CSM technique. Properties of the all samples are not constant, but strongly depend on the contact depth and this is mainly due to the presence of the different types of thin films with diverse physical properties and 15 interfaces. From Fig. 4, it is clear that initially all samples exhibit high hardness and modulus values due to the presence of the SiN layer on top of the stack. However, back grinded stacks show higher hardness values throughout the indentation depth and this difference is significant till ~1500 nm. Even though BG-500 µm samples shows moderate failure load values when compared to other back grinded stacks, still it shows higher mechanical properties than normal stack. There is no difference in hardness values among the back grinded stacks. In case of the elastic modulus, the overall trend is mixed, in which initially back grinded stacks exhibit high values and from 1000 nm depth, BG-150 µm stack follows the trend of normal stack and BG-75 & 300 µm stacks show lower modulus values. The mixed trend of modulus values of all samples is mainly due to that, the elastic modulus is highly sensitive and intrinsic property. Elastic modulus is greatly influenced by the beneath

a

c

b

d

e


Fig. 4 Hardness and elastic modulus as a function of

displacement for normal and back grinded samples.

layers of the testing films and substrate. In the case of hardness, the difference between normal stack and back grinded stacks is very quite clear when compared with the modulus values. The minima values of the hardness and modulus values from the property plots can represent the low-k (Black Diamond, BD) region as it is known that the Black Diamond TM (low-k) has lower mechanical strength when compared to the other constituents of the stack (viz. SiN, USG, Blok). So minima region for the hardness is around 2000 nm, which is middle of the low-k region and for modulus the minima region is found to be at around 500 nm. The mechanical properties at this minima region (2000nm for H and 500nm for E) are as H= 4.27 GPa and E= 41.81 GPa for the normal stack and in the range of H= 4.94-5.10 GPa and E=49.75-51.55 GPa for the back grinded stacks. These values actually represent the properties of the low-k stack as summarized in Table 1 and compared in Fig.7. In case of modulus physical contact depths can not be followed as it is sensitive and always exerts its effect much before the original contact depth due to continuous stiffness measurements. As a whole, back grinded stacks exhibit the higher hardness and elastic modulus values, and this trend is quite clear in the low-

k region. This might be due to that back grinding loads/pressures influencing the interfaces and causing the densification of the films, especially in the low-k region. In this study the fracture/failure strength, hardness and elastic modulus of the normal and grinded stacks are analyzed and compared at gross level as the nanoindentation analysis is very complicated and not well established for the multilayered stacks.

Fig. 5, (a) Hardness (b) Elastic modulus at different

contact depths (100, 200, 500, 1000, 1500 and 2000 nm) for normal and back grinded stacks

Fig. 5 a-b shows the hardness and modulus at different contact depths (100-2000 nm) as a function of wafer thickness. These plots will be very useful to compare the properties of a particular sample thickness at different contact depths. From Fig. 5a, hardness shows significant difference with respect to contact depth for different thickness samples. Whereas in case of modulus from Fig. 5b, only shallow contact depths (100-500 nm) exhibit trend as the back grinded samples are stronger than the normal sample. Incase of the higher contact depths modulus values are fluctuating, might be due to that modulus is highly sensitive and greatly influenced by the low-k stack failures and substrate effect.

b

a

b

a


This analysis provides the quantitative comparison of the mechanical properties of a samples at different contact depths and will be very useful to study how back grinding forces are influencing the throughout the stack thickness.

3.2 Adhesion/Cohesion strength Adhesion/Cohesion strength of the normal and back

grinded stacks is reported in terms of the critical normal load (Lc), where first abrupt decrease in scratch depth is observed. Fig. 6a shows the nanoscratch profiles as scratch depth vs. normal load for all samples and Fig. 6b shows the scratch loading at different scratch depths as a function of wafer thickness. As in nanoindentation contact depths analysis, in scratch tests also it is noticed that the lower contact depths (200-1500 nm) did not show any variation in scratch loading with respect to wafer thickness. However at the deeper scratch depths (1500-2000 nm) back grinded stacks exhibit higher scratch loads than the normal stacked sample. This is mainly due to the presence of the low-k layer at the deeper dimensions (1800-2850 nm). From Fig. 6a, critical load (Lc) of the normal and back grinded stacks is well defined where the stack fully chipped-off (delaminated) from the substrate and it can be verified from the corresponding optical images (Fig. 7). In Fig. 7a-d, optical images of the both the normal and grinded stacks have been captured at three different locations, beginning, middle and end of the scratch track profile. Before reaching the critical load minor damage to the stacks is observed in terms of crack and it can be seen on scratch profile as a small kink just before reaching the critical load (Lc) point. Arrows over the scratch track of all samples indicate the critical load (Lc) where significant delamination/chip-ff of the stack is started. From that critical load (Lc) point it is observed that the sudden increase of the scratch depth as the indentation tip is abruptly hitting the silicon substrate, which was associated with catastrophic chip-off failure of the whole stack as well as significant plowing of the tip into the silicon substrate. This plowing action associated with the delamination chip-off of whole stack and it is sustained till end of the scratch track. Similar to the nanoindentation tests, in nanoscratch tests also, the back grinded stacks exhibit higher critical loads (100.73-96.30 mN) than the normal stack (72.80 mN). Moreover, no significant difference in critical loads is observed among the back grinded stacks (BG 500=98.65, BG 300=100.73, BG 150=96.00, BG 75µm=96.30 mN), and these results have been summarized in Table 1 and compared in Fig 8. In nanoscratch tests, both normal and back grinded stacks exhibit significant adhesive failure and this failure can be observed in nanoscratch profile at the point where the scratch tip abruptly hits the silicon substrate at the critical load (Lc) point and in the optical images of chipping-off the stack as debris around the scratch track especially after the critical load (Lc). Though the extent of the back grinded effect over the low-k stack may be different for the different back grinding thicknesses, but nanoscratch test was not able to sense this difference as all the grinded stacks showed nearly same results.

Fig. 6 (a) typical nanoscratch depth profiles as a function

of normal load (b) scratch load at different depths, for normal and back grinded samples.

Table 1 Summary of nanomechanical properties of normal and back grinded samples

b

a


(a) Normal Stack

(b) BG 300um

(c) BG 150 um

(d) BG 75um

Fig. 7 Optical micrographs of scratch tracks made on the multilayered low-k stack. Arrows over the image indicate the critical load (Lc) point, where significant delamination and

chip-off started.

Fig. 8 Failure load, Adhesion/Cohesion strength, Elastic modulus (E), and Hardness (H) as a function of wafer

thickness. 3.3 TEM analysis

As discussed before, both nanoindentation and nanoscratch test results indicate that the mechanical integrity of low-k stack is enhanced after the back grinding processes. To ascertain the effect of back grinding process on the low-k stack, TEM cross-section analysis has been conducted on both the normal and back grinded stacks (BG 75 and 150 µm), as shown in Fig. 9 a, b and c. From cross-sectional TEM

analysis of the normal and grinded stacks, it is observed that there are some significant structural changes at the interfaces of the low-k region and the interfaces of other regions look almost the same. Low-k interfaces in the normal stack are wavy (Fig. 9 a), whereas low-k interfaces in the grinded stacks of BG 75 and 150 um (Fig. 9 b and c) are smooth. This suggests that the force employed during back grinding processes influences the low-k interfaces. Moreover, a significant densification in the low-k layers (BD 1, 2, and 3) is observed in the back grinded stacks as compared to the normal stack as shown in the Fig. 8. The densification in the low-k layers of the grinded stacks is in the range of 2-13% as compared to the normal stack and it is expected mainly due to the weaker physical and mechanical strength of the low-k stack.

(a) Normal Sample

(b) BG 75um

(c) BG 150um

Fig. 9 TEM cross-section analysis of (a) normal sample, (b) BG 75 and (c) BG 150 um. Low-k region has been zoomed in

for densification analysis.


4. Conclusions In this work, nanomechanical characterization of the

normal and back grinded low-k stacks were carried out by using nanoindentation and nanoscratch techniques. Effect of the back grinding process is determined by analyzing of the failure load (pop-in event in nanoindentation), hardness, elastic modulus and adhesion/cohesion strength of the low-k stack for both normal and back grinded samples. After back grinding processes, the mechanical integrity of low-k stack is enhanced and thus the back grinded stacks exhibit higher nanomechanical properties than the normal stacks. This can be attributed mainly to the straightening of the low-k interfaces and densification of the BD (low-k) layers during back grinding processes, which was observed in TEM cross-sectional analysis. Based on the results and their detailed analyses it can be concluded that the thermo-mechanical stresses applied and/or generated during wafer back grinding processes affect the interfaces and nanomechanical behavior of the low-k stack, in turn enhances the mechanical integrity of the back grinding stacks. Some important results are summarized as follows,

1. Hardness, elastic modulus, nanoindentation load and scratch load, at various contact depths of the low-k stack have been studied and compared the deformation behavior and properties with respect to wafer thicknesses.

2. Normal stack failed at 456.25 mN load and 2422.41 nm indentation depth, whereas back grinded stacks failed at higher values (482.17-661.20 mN load and 2405.86-2979.79 nm indentation depth).

3. One common feature has been observed among the normal and back grinded stacks is that the failure of the stack is occurring in the low-k region.

4. The mechanical properties of the normal and back grinded stacks have been compared at minima property region which represents the low-k region (BD1 through BD3), (Hardness at 2000nm and Elastic modulus at 500 nm depth). These properties are as H= 4.27 GPa and E= 41.81 GPa for the normal stack and in the range of H= 4.94-5.10 GPa and E=49.75-53.64 GPa for the back grinded stacks. Thus back grinded stacks exhibit higher mechanical properties than the normal stack.

5. Similar to the nanoindentation tests, in nanoscratch tests also, the back grinded stacks exhibit higher critical loads (Lc) (100.73-96.30 mN) than the normal stack (72.80 mN).

6. No significant difference in critical loads has been observed among the back grinded stacks (BG 300=100.73, BG 150=96.00, BG 75=96.30 mN).

7. After back grinding processes, the mechanical integrity of low-k stack is enhanced and thus the back grinded stacks exhibit higher nanomechanical properties than the normal stacks.

Acknowledgments This work is the result of a project initiated by the 8th IME

Electronic Packaging Research Consortium (EPRC VIII), the members of which are Advanced Interconnect Tech (AIT)

Pte. Ltd., Agere Systems Singapore Pte. Ltd., ASM Technology Singapore pte. Ltd., Cookson Semiconductor Packaging Materials, DISCO Hi-Tec Singapore Pte. Ltd., Infineon Technologies Asia Pacific Pte. Ltd., Philips Semiconductor, Sumitomo Bakelite Singapore Pte. Ltd., Institute of Microelectronics (IME), Singapore Institute of Manufacturing Technology, Institute of High Performance Computing and Institute of Materials Research & Engineering. The authors are grateful to members of EPRC VIII Project 3 as well as IME staffs who had contributed and made this work possible.

References 1. www.semiconductor.net 2. Reiche, Manfred & Wagner, Gerald “Wafer thinning:

techniques for Ultra-thin Wafers”, Advanced Packaging, March, 2003.

3. Kenji Takahashi et al. “Current status of research and development for three-dimensional chip stack technology” Jpn. J. Appl. Phys. Vol 40 (2001) pp. 3032-3037.

4. Betty H. yeung et al. “Assessment of Backside Processes Through Die Strength Evaluation” IEEE Transactions on Advanced Packaging, Vol.23, No.3, Aug 2000, pp.582-587.

5. Shoulung Chen et al. “The Evaluation of wafer thinning and Singulating Processes to Enhance Chip” IEEE Elelctronic Components and Technology Conference, 2005, pp. 1526-1530.

6. Hoh Huey Jiun et al, “Effect of wafer thinning methods towards fracture strength and topography of silicon die” Microelectronics Reliability, 46 (2006) 836-845.

7. Chen J, De Wolf I. “ Study of damage and stress induced by backgrind in Si wafers” Semicond Sci Technol 2003; 18: 261-268.

8. Gaulhofer E, Oyer H., “Wafer thinning and strength enhancement to meet emerging packaging requirement” IEMT Europe Symposium 200 pp.1-4.

9. Mc Hatton C, Gumbert CM. “Eliminating backgrind defects with wet chemical etching” Solid-State Technol 1998 (November): 85-90.

10. Blech I and Dang D “Silicon Wafer Deformation After Backside Grinding”, Solid State Tech., 37(8), 1994, pp.74-76.

11. Lee S, Sim S, Chung Y, Jang Y, and Cho H, “Fracture Strength Measurement of Silicon Chips” Jpn. J. Appl. Phys., Vol. 36, 1997, pp. 3374-3380.

12. www.disco.co.jp 13. W. C. Oliver, G. M. Pharr, J. Mater. Res. 7 (1992) 1564. 14. A. A. Volinsky, D. F. Bahr, M. D. Kriese, N. R. Moody, W.

W. Gerberich, 2003, ‘Nanoindentation methods in interfacial fracture testing’ Chap. 13, Vol. 18, Interfacial and nanoscale failure, Elsevier.

15. D. S. Campbell (1970), Handbook of thin film technology, Chap. 12, New York, Mc Graw-Hill.

16. Lugeb Wang et al, “Nanoindentation analysis of mechanical properties of low to ultraz dielectric constant SiOCH films” J. Mater. Res., Vol. 20, No.8, Aug 2005, 2080-2093.

17. N. Tayebi, A. A. Polycarpou and T. F. Cony, J. Mater. Res., Vol. 19, No. 6, (2004).


Effect of Wafer Back Grinding on the Mechanical Behavior of

Documents

Transcript of Effect of Wafer Back Grinding on the Mechanical Behavior of