Effect of parametric variation on the performance of single wall carbonnanotube based field effect transistor

Avshish Kumar a, Mubashshir Husain d, Ayub Khan c, Mushahid Husain a,b,n

a Department of Physics, Jamia Millia Islamia (A Central University), New Delhi 110025, Indiab Centre for Nanoscience and Nanotechnology, Jamia Millia Islamia (A Central University), New Delhi 110025, Indiac Department of Mathematics, Jamia Millia Islamia (A Central University), New Delhi 110025, Indiad Electrical and Computer Engineering Department, King Abdul Aziz University Jeddah, Saudi Arabia

H I G H L I G H T S

� The effects of dielectric constant andgate insulator thickness on the perfor-mance of SWCNT-FETs were studied.

� SWCNT-FET has a considerable advan-tage over conventional MOSFETs.

� As the ION increases on scaling downthe gate oxide thickness, the level ofIOFF is not affected.

� The thickness of thin oxide layercauses drastic increase in gate leakagecurrent.

� Thinner gate oxide and high-k dielec-tric material have improved the per-formance of CNT-FETs.

G R A P H I C A L A B S T R A C T

The effects of dielectric constant and gate insulator thickness on the performance of CNT-FETs have beenanalyzed using a mathematical model based on FETToy simulator and results showed that thinner gateoxide and larger CNT improved the performance of CNT-FETs. Therefore, the performance of thesimulated CNFETs using this model has clear lead over those of conventional MOSFETs. The geometry ofthe FETToy model is shown in figure.

a r t i c l e i n f o

Article history:Received 19 April 2014Received in revised form15 July 2014Accepted 16 July 2014Available online 1 August 2014

Keywords:Carbon nanotubeTransistorGate oxideMOSFET

a b s t r a c t

The effects of dielectric constant and gate insulator thickness on the performance of single wall carbonnanotube field effect transistors (CNTFETs) have been analyzed using a mathematical model based onFETToy simulator. Both the parameters are found to have significant effect on the device performance,particularly the on-current; while the on-current (ION) increases on scaling down the gate oxidethickness, the level of leakage current (IOFF) is not considerably affected. This is an advantage of CNTFETover conventional MOSFETs where the thickness of thin oxide layer causes drastic increase in gateleakage current. Our analysis results show that thinner gate oxide and larger CNT improve theperformance of CNTFETs. Therefore, the performance of our simulated CNTFETs using this model hasclear lead over those of conventional MOSFETs.

& 2014 Elsevier B.V. All rights reserved.

1. Introduction

Modeling is the process of producing a model which representsthe construction and working of some system of interest. It is similar

to but simpler than the system it represents. The operation of anyprepared model of a system is done by simulations to evaluate theperformance of the system under different configurations of interestand over long periods of real time. One purpose of the modeling andsimulation is to facilitate the analyst to predict the effect of changesin the system and its subsystem.

Experimentally, vertically aligned freestanding SWCNTs havebeen successfully grown at low temperatures which are useful forgrowth on temperature sensitive substrates and for selective

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Physica E

http://dx.doi.org/10.1016/j.physe.2014.07.0181386-9477/& 2014 Elsevier B.V. All rights reserved.

n Corresponding author at: Department of Physics, Jamia Millia Islamia (A CentralUniversity), New Delhi 110025, India. Tel.: þ91 11 26988332;fax: þ91 11 26981753.

E-mail address: mush_reslab@rediffmail.com (M. Husain).

Physica E 64 (2014) 178–182

growth. In the growth processes there are several parameterswhich require hundreds of processes to optimize the growth ofSWCNTs with the highest order of purity and control to synthesizerepetitive SWCNTs on desired substrates, preferably silicon, atdesired location and orientations. However it might not be feasibleto experiment a dozen or a hundred processes to make SWCNTssuitable for various applications especially for semiconductingapplications. In this connection, a theoretical/computationalmodel needs to be developed so that theoretical results can besimulated experimentally and best optimization for the synthesisof SWCNTs can be achieved for a choice of applications [1].

From the theoretical point of view, various researchers havealready described a wide-variety of theoretical/computationalstudies to explain the atomistic information of the initial stageof the growth which includes ab-initio molecular dynamics(MD) [2–11], classical potential based molecular dynamics [12–18], and classical thermodynamics based growth parameters[19–23]. Nucleation pathway for SWCNTs on a metal surfaceusing a series of total energy calculations based on densityfunctional theory (DFT) was verified by Fan et al. [10]. Dinget al. showed a nucleation development indicating that tem-perature gradient in the metal particle might be unnecessaryas a driving force for nucleation of the SWCNT [12]. Raty et al.illustrated the first stages of the nucleation of a fullerene capon a metal particle by ab-initio MD [9]. Amara et al. [23]focused on the carbon chemical potential during SWCNTformation using tight-binding methods coupled to a grandcanonical Monte Carlo (MC) simulation and showed thatsolubility of carbon in the outermost nickel layer is dominantin controlling the nucleation of SWNTs. All these studies arebased on certain models to make SWCNTs better for variousapplications. Particularly, SWCNTs have grown up as the mostlikely candidates for miniaturizing electronics beyond currenttechnology. They reveal exceptional electrical and mechanicalproperties. The most fundamental application of SWCNTs is infield effect transistors (FETs); n-type carbon nanotube fieldeffect transistors and p-type carbon nanotube field effecttransistors have been made which show behavior similar toMOSFETs [24].

In this study the model used for the FETToy software is veryuseful, assuming ballistic transport which produces near-idealresults. These results are based on a limited set of parameters,which controls the software's usefulness for predicting the exactcharacteristics of a fabricated device. Starting with the dimensionsof a fabricated device, it can be useful in analyzing the effects ofparameter variation on CNTFET performance. These variations canthen be used as a guide for further development and to pointtoward areas where improvements will yield the best results, whichcan save fabrication cycles and speed up CNTFET development.

The theoretical basis for CNT-FETToy is a model by Natori forballistic FETs [25] which has been expanded upon by Rahman[26]. Numerical simulations such as the ballistic Boltzmannequation and the non-equilibrium Green's function (NEGF) pro-vide detailed information about nanoscale devices, but are verycomplex. The goal of the expanded model is to develop a simpleanalytical model for determining the current–voltage character-istics that can produce accurate results without needing tospecifically address all of the complex phenomena that takeplace within the device.

The work presented in this article will focus on modeling andsimulation of SWCNT based field effect transistors (CNTFETs) bychanging the device's structure and includes various effects on deviceperformance of variations in the transistor's structural parameterssuch as CNT diameter, gate dielectric thickness, and gate dielectricconstant. Using these parameters, current–voltage (I–V) characteristicshave been simulated under different parametric variations.

2. Model

The simulations in this work are conducted by FETToy 2.0 softwarewhich is a product of nanoHUB, an internet-based website funded bythe National Science Foundation's (NSF) Network for ComputationalNanotechnology (NCN) and Purdue University [27]. It is a numericalsimulator which uses a set of Matlab scripts to calculate ballistic I–Vcharacteristics for conventional single and double gate geometryMOSFETs, nanowire MOSFETs, and carbon nanotube MOSFETs.

FETToy assumes an optimal CNTFET geometry comprising asingle, semiconducting carbon nanotube channel, completely sur-rounded by an oxide and gate structure, with perfectly contactedends (Fig. 1). It requires a relatively small number of parameters,divided into three categories.

The model for ballistic CNTFET consists of three capacitors,which represents three transistor terminals on potentials at thetop of barrier. As shown in Fig. 2, the shaded region indicatesmobile charge at the top of the barrier. The mobile charge isdetermined by the local density of states at the top of the barrier,location of source and drain levels, EF1 and EF2, and self-consistentpotential at the top of the barrier.

It is common to think of MOSFETs as operating by modulatingthe charge in the channel, but this FETToy model focuses on theheight of the energy barrier in the channel. The two concepts arelinked in that the charge in the channel is controlled by the heightof the barrier, but basing the model on the height of the barrierallows a more concise analytical model. The circuit diagram inFig. 2 shows the simple model that represents the potential at thetop of the barrier when taking into account the effect of the threeterminals (source, drain, and gate). Calculating the potential at thetop of the barrier starts with the terminal biases at zero. This willgive the equilibrium electron density at the top of the barrier as

N0 ¼Z þ1

�1DðEÞf ðE�Ef ÞdE ð1Þ

Fig. 1. The optimal geometry assumed in the FETToy model: (i) device, (ii) modelsand (iii) environment.

Fig. 2. 2D circuit model for a ballistic transistor.

A. Kumar et al. / Physica E 64 (2014) 178–182 179

with D(E) being the local density of states at the top of the barrierand f(E�Ef) as the equilibrium Fermi function. The function D(E) iszero for negative values of its argument, which represents theminimum of the density of states and is specified as E¼0 inequilibrium [26]. In this model, the source terminal is alwaysgrounded, but applying a bias to the gate and drain terminalscauses the self-consistent potential at the top of the barrier tobecome Uscf and populates the states at the top of the barrier bytwo different Fermi levels. The positive velocity states are popu-lated by the source, as described by

N1 ¼12

Z þ1

�1DðE�Uscf Þf ðE�EF1ÞdE ð2Þ

The negative velocity states are populated by the drain, asdescribed by

N2 ¼12

Z þ1

�1DðE�Uscf Þf ðE�EF2ÞdE ð3Þ

where N1 represents positive velocity states filled by source and N2

represents negative velocity states filled by drain, EF1(F2) is thesource (drain) Fermi level, f(E) is the probability that a state withenergy E is occupied (Fermi–Dirac probability), D(E) is the nano-tube density of states (DOS) at the top of the barrier and Uscf isself-consistent potential at the top of the barrier. Assuming sourceFermi level EF1¼EF, we have EF2¼EF�qVDS where q is electroniccharge [26]. It is convenient to simplify Eqs. (2) and (3) by defining

f 1ðEÞ ¼ f ðEþUscf �EF1Þ ð4Þ

f 2ðEÞ ¼ f ðEþUscf �EF2Þ ð5ÞPutting these values of f1 and f2 in Eqs. (2) and (3), we get

N1 ¼12

Z þ1

�1DðEÞf 1ðEÞdE ð6Þ

N2 ¼12

Z þ1

�1DðEÞf 2ðEÞdE ð7Þ

With Eqs. (6) and (7) the total electron density at the top of thebarrier is N¼N1þN2, and can be determined if the arbitrarydensity of states, D(E), the source and drain Fermi levels, and theself-consistent potential, Uscf, are known. All parameters exceptthe Uscf are given and the method for determining the Uscf ispresented below.

The self-consistent potential is determined by solving the two-dimensional Poisson equation as represented by the 2D model inFig. 2 with the common terminal evaluated at the bias inducedcharge, ΔN¼(N1þN2 )–N0. Ignoring mobile charge in the channelin equilibrium state, the Laplace potential at the top of the barrieris then

UL ¼ �qðαGVGþαDVDþαSVSÞ ð8Þwhere

αG ¼ CG

C2; αD ¼ CD

C2; αS ¼

CS

C2

The three αs in Eq. (8) describe the gate, drain and source's controlover the Laplace solution and depend on the two dimensionalstructure of the device [26].

For an optimally constructed MOSFET, the gate controls thepotential in the channel which means that

αG � 1 and αSαD � 0

Next, potential at the top of the barrier due to mobile charge iscomputed as

UP ¼q2

CΣΔN ð9Þ

where CΣ is defined as the parallel combination of the threecapacitors.

When a positive bias is applied to the drain and gate terminalsthe potential energy at the top of the barrier is pushed downaccording to UL, but the charge causes the potential to float upaccording to UP. The entire self-consistent potential Uscf is there-fore the superposition of these two effects, yielding

Uscf ¼ULþUP ¼ �qðαGVGþαDVDþαSVSÞþUC ΔN ð10ÞGiven the charging

UC ¼q2

CΣð11Þ

with Eqs. (2), (3) and (10) the coupled nonlinear equations for Nand Uscf can be iteratively solved to find the carrier density and theself-consistent potential at the top of the barrier. Taking J(E) as the‘current-density-of-states’ [26], the drain current is determined by

ID ¼Z þ1

�1JðEÞ½ f 1ðEÞ� f 2ðEÞ�dE ð12Þ

Simplified down to the critical steps, the procedure for computingID(VG,VDS) requires the following steps:

i) Specify the density of states at the top of the barrier, D(E), andthe current-densities-of-states, J(E);

ii) Specify VG, VD, VS, and Ef;iii) Solve Eqs. (2), (3) and (10) for Uscf and N; and finally,iv) Find the drain current with Eq. (12) with the assumed VG and

VDS.

Using Rahman's model and assuming a CNTFET structure, it ispossible to calculate detailed results with varying oxide thickness,nanotube diameter and gate dielectric constant while keeping thesame temperature and series resistance as inputs. The sourceFermi level, gate control constant and drain control constant areused as fitting factors to ensure that the simulated sub-thresholdslope and drain induced barrier lowering match experimentalresults.

3. Results and discussion

3.1. Effects of varying dielectric thickness of gate insulator

The gate insulator thickness or the ‘dielectric thickness’ is thethickness of the insulator between the gate and the carbonnanotube (CNT) channel. For this portion of the simulation studywe keep all the parameters unchanged i.e. nanotube diame-ter¼1 nm and gate insulator dielectric constant ¼16, except forthe gate insulator thickness. In this the gate and drain controlparameters, αG and αD, were left unchanged. Also, the seriesresistance was kept unchanged, i.e. 0Ω. For the ‘Environmentparameters’, the gate and drain voltage sweeps will be over thesame ranges as the default ones.

For the dielectric thickness, FETToy accepts thicknesses onlybetween 0 nm and 1000 nm. We simulated the drain current–drain voltage characteristics in this range for 2 nm, 4 nm, 6 nm,8 nm, and 10 nm dielectric thicknesses. The resulting current–voltage characteristics (the drain current vs drain voltage) areshown in Fig. 3 and labeled. This is explained through thesimulation modeling current flow through a single nanotube,assuming pure ballistic transport. As described below, thesecurrent–voltage characteristics are useful for extracting the tran-sistor's threshold voltage.

For the CNTFETs examined in this study, the effect of the gateoxide thickness scaling on the transistor performance was

A. Kumar et al. / Physica E 64 (2014) 178–182180

examined as seen in Fig. 3. It can be seen that larger oxidethicknesses cause a lowering of the saturation current andtransconductance, which will impair transistor performance. Thus,thinner oxide (2 nm oxide thickness) will provide better ID. Withconventional silicon MOSFETs, the saturation current would beexpected to scale linearly with the inverse of the oxide thickness.While some devices still rely on easily formed, relatively thickoxide layers, it can be easily seen that a primary goal in transistordesign should be minimizing the oxide thickness while maintain-ing charge in the channel appropriate for transistor operation.

Further, we simulated the drain current vs gate voltage char-acteristics in this range for 2 nm, 4 nm, 6 nm, 8 nm, and 10 nmdielectric thicknesses as shown in Fig. 4.

From the graph of ID vs VG as shown in Fig. 4 it can be observedthat the level of leakage current, IOFF, is not considerably affectedby changing the gate oxide thickness. That is, the leakage currentin CNTFET does not increase significantly when gate oxide is thin.This is an advantage of CNTFET over conventional MOSFETs wherethe thin layer of oxide thickness causes drastic increase in gateleakage current.

Thus while the on-current, ION, increases as the gate oxidethickness decreases, the level of leakage current, IOFF, is notconsiderably affected by gate oxide thickness. Therefore, we candeduce that the ION/IOFF ratio will increase as the gate oxidethickness is reduced. Hence, we can conclude that thinner gateinsulator thickness will give better performance of CNFET.

3.2. Effects of varying dielectric constant

The effects of variation in the gate insulator's dielectric con-stant were similarly studied using the FETToy software. Here, allthe parameters were kept unchanged except for the gate insula-tor's dielectric constant (Fig. 4). As previously the gate and draincontrol parameters, αG and αD, were left unchanged since noexperimental measurements were reported. Also, the series resis-tance was left unchanged. For the ‘Environment tab’, the gate anddrain voltage sweeps will be over the same ranges as thedefault ones.

For the gate insulator dielectric constant, FETToy accepts valuesonly between 0 and 50. Thus, we have simulated the draincurrent–gate voltage characteristics in this range for dielectric

constants of silicon dioxide SiO2 (3.9), hafnium oxide HfO2 (16),zirconium oxide ZrO2 (25), and titanium oxide TiO2 (40), and justto see the effects at the maximum range, we selected a gateinsulator dielectric constant of 50. The resulting current–voltagecharacteristics (drain current vs gate voltage) are shown in Fig. 5.

The effect of the dielectric constant on the current–voltagesubthreshold characteristics obtained from the FETToy devicesimulation of the CNTFET is shown in Fig. 6.

According to the simulation, as the dielectric constantincreases, the subthreshold slope decreases. This is the expectedtrend since a larger dielectric constant gives the gate more controlover the charge in the channel. A smaller subthreshold slope isbetter and, thus, the dielectric constant of 50 of the hypotheticalgate insulator material is the optimal selection.

Fig. 3. Drain current vs drain voltage characteristics for gate insulator thicknesses(a) 2 nm, (b) 4 nm, (c) 6 nm, (d) 8 nm and (e) 10 nm.The CNT diameter ¼1 nm andgate insulator dielectric constant ¼16.

Fig. 4. Drain current vs gate voltage characteristics for gate insulator thicknesses2 nm, 4 nm, 6 nm, 8 nm and 10 nm. The CNT diameter ¼1 nm and gate insulatordielectric constant ¼16.

Fig. 5. Drain current vs gate voltage characteristics for dielectric constant at 3.9, 16,25, 40 and 50. The CNT diameter ¼1 nm and gate insulator thickness ¼1.5 nm.

A. Kumar et al. / Physica E 64 (2014) 178–182 181

From the plot in Fig. 7, it appears that as the dielectric constantgets larger, the drain current and transconductance increase. Thus,the CNTFET having a high-k gate insulator will give betterperformance due to its low threshold voltage and high saturationcurrent, Ids.

The capacitance of the gate is a critical issue for future highperformance transistors. A high-k dielectric is, therefore, unavoid-able since the thickness of a silicon oxide or an oxy-nitride gatedielectric cannot be reduced below a certain value without causingan intolerable increase in the gate leakage by direct tunneling. Theapplication of high-k dielectrics to silicon transistors is stillcumbersome due to severe mobility degradation of the Si channel.A unique benefit of carbon nanotubes is their compatibility withhigh-k dielectrics. The lack of dangling bonds at the nanotube/

high-k interface and the weak non-covalent bonding interactionsbetween the two materials prevent any perturbation of electrontransport in carbon nanotubes. Thus, by using HfO2 (k�16), orTiO2 (k�40), we can replace a 1 nm SiO2 film with a 5 nm HfO2 ora 10 nm TiO2 film, thereby reducing tunneling leakage currentsignificantly. HfO2 provides a much thicker barrier considerablyreducing the effect of tunneling and in turn the problem of leakagecurrent. Therefore, it will be able to provide a good interface withthe silicon substrate.

4. Conclusions

On the basis of the observations using modeling and simulationof SWCNT based FETs, we conclude that the performance ofsimulated CNT-FETs using FETToy model has clear advantage overconventional MOSFETs. We also found that both the parameters(dielectric constant and gate insulator thickness) are found to havesignificant effect on the device performance, particularly the oncurrent ION. Analyses results reveal that thinner gate oxide andhigh-k dielectric material have improved the device performance.

Acknowledgments

We are thankful to Department of Electronics and InformationTechnology (DeitY) for the financial support in the form of a majorresearch project.

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Fig. 6. Drain current vs drain voltage characteristics for dielectric constant (a) 3.9,(b) 16, (c) 25, (d) 40 and (e) 50. The CNT diameter ¼1 nm and gate insulatorthickness ¼1.5 nm.

Fig. 7. k–Id plot for a cylindrical CNTFET.

A. Kumar et al. / Physica E 64 (2014) 178–182182