平面型元件統合式服務平台 - TSRIPurpose • This document is intended to help users who...
Transcript of 平面型元件統合式服務平台 - TSRIPurpose • This document is intended to help users who...
平面型元件統合式服務平台
90 nm CMOS Process
CONFIDENTIAL 1
2014/06/04
DisclaimerNDL SHALL NOT BE LIABLE FOR TECHNICAL OR EDITORIAL
ERRORS OR OMISSIONS CONTAINED HEREIN; NOR FORINCIDENTAL OR CONSEQUENTIAL DAMAGES RESULTING FROMTHE FURNISHING, PERFORMANCE, OR USE OF THIS MATERIAL.THE INFORMATION IN THIS MANUAL IS SUBJECT TO CHANGEWITHOUT ANY PRIOR NOTICE FOR THE PURPOSES OF IMPROVINGTHE PERFORMANCE AND FUNCTIONALITY OF ITS PRODUCTS.
No one is allowed to copy or distribute the whole or a part of this document without prior written permission of NDL.
NDL here means National Nano device Laboratories.
CONFIDENTIAL 2
Purpose
• This document is intended to help users who want toapply NDL 6” CMOS baseline process to do fabrication.
• Please be notified that users should follow the processguideline in this document to do fabrication without anyviolation.
Contact information : [email protected] (賴東彥 工程師)
CONFIDENTIAL 3
CONTENTS
CONFIDENTIAL 4
Disclaimer ..………………………………………………………………... 02Purpose …..…………………………………………………………………. 03Process Flow Chart …………………………………………….......... 05
Mask layout and design rules ….……………………………….... 09Platform performance ………………………………................... 12
製程服務申請相關事項 ………….…………......................... 16Equipment layout ……………………………….......................... 25
* 薄膜移除,沉積與曝光(Film strip;film deposition and Lithography)
矽基板清潔(Wafer clean)
薄膜沉積與曝光(Film deposition and Lithography)
薄膜蝕刻(Film etch)
離子佈植與氧化(Ion implantation and Oxidation)
*薄膜蝕刻(Film etch)
*離子佈植(Ion implantation)
*薄膜沉積與蝕刻(Film deposition and Etch)
*離子佈植與熱退火(Ion implantation and Thermal annealing)
金屬薄膜沉績 (Option)(Metal film deposition )
熱退火與薄膜去除(Thermal annealing and Metal film strip )
薄膜沉積與化學機械研磨(Film deposition and CMP)
曝光(Lithography)
薄膜沉績與金屬薄膜沉積(Film etch and Metal film deposition )
金屬薄膜蝕刻(Metal film etch)
紅字說明為 90nm元件之關鍵製程, 下run前請與工程師討論.
Process Flow Chart
CONFIDENTIAL 5
Active area patterning
LOCOS formation
P-well implant
N-well implant
Re-Oxidation
N Halo+LDD shallow junction
SiN MSW
N+ S/D
P+S/D
Spike RTA
Low-T annealing NiSi
TEOS ILD
Contact patterning (I-line )
Ti/TiN/AlCuSi/TiN deposition
P Halo+LDD shallow junction
M1 patterning
Sintering
• 總共 150 道製程, 製程時間約 4 個月
P-Vt/APT implant
N-Vt-/APT implant
Gox 25A+Poly+TEOS HM
Gate patterning PVD Ni
CONFIDENTIAL 6
Process Flow Chart
CONFIDENTIAL 7
90 nm CMOS device– 光罩流程
Mask Name NMOS PMOS
90nmCMOS‐Active Active, LOCOS Active, LOCOS,
90nmCMOS‐NWellN‐well implant, Vt implant,APT implant, PKT implant, SD‐extension, SD implant
90nmCMOS‐PWellP‐well implant, Vt implant,APT implant, PKT implant, SD‐extension, SD implant
90nmCMOS‐Gate_V2 Poly gate Poly gate
90nmCMOS‐Contact Contact Contact
90nmCMOS‐Metal Metal pad Metal pad
CONFIDENTIAL 8
NMOS PMOSVt implant BF2,90K 1E13 As, 80K 8E12
APT implant B,100K 7E12 P,120K 4E12
Gate oxide Gox20A Gox20A
Poly gate Poly(Undoped)1200A Poly(Undoped)1200A
PolyReoxidation
reox 50A reox 50A
PKT NPKT1:BF2,50keV,5E12,Tilt45D,Twist27D,Rotation:4
PPKT2:As,50keV,2E12,Tilt45D,Twist27D,Rotation:4
SD-extension As,7keV,1E15 BF2,7keV,5E14
MSW spacer SiN MSW 1200A (780C) SiN MSW 1200A (780C)
SD implant NMOS SD AS 20K 5E15 PMOS SD BF2 15K 5E15
RTA SD RTA 1050C, 10SEC SD RTA 1050C, 10SEC
Contact AlSiCu AlSiCu
Metal AlSiCu AlSiCu
90 nm CMOS device ‐ V0.1 Baseline
(1)Gate length : 0.3um 以上
(2)Gate width : 10 um以下
(3)Tail length : 2 um以上
(4)Tail width : 2.5 um以上
(5)Gate & Active overlay: 0.5 um以上
(1)
(2)
(3)
(4)
(5)
CONFIDENTIAL 9
90 nm CMOS device ‐ Poly 閘極層設計法則
CONFIDENTIAL 10
90 nm CMOS device ‐ Poly 閘極層設計法則
Gate
2um
3um
4um
2um4um20um
20um
AAPOCOMetal
implant
5um
2um
10um
substrate
一般層設計法則
(依據 0.35um 設計法則 ):
AA (Line/Space):0.35/0.35um
PO (Line/Space):0.30/0.35um
Co (Line/Space):4/4um (Al plug)
Metal (Line/Space):0.35/0.35um
CONFIDENTIAL 11
90 nm CMOS device ‐ Mask Layout
• ndl-90nmCMOS-fv3 Mask Layout
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.51E-141E-131E-121E-111E-101E-91E-81E-71E-61E-51E-41E-30.01
Vd=1.5VLg=90nmW=10mTox=25A
I ds(A
/m
)
Vg(V)-1.2 -0.8 -0.4 0.0 0.4 0.8 1.2
0.0
1.0x10-4
2.0x10-4
3.0x10-4
4.0x10-4
5.0x10-4
1.0V
1.5V
0.6V
I ds(
A/
m)
Vd (V)
Lg=90nmW=10mVg step=0.5V 1.5V
1.2V
0.9V
CONFIDENTIAL 12
Platform performance• Single Device TEM and electrical characteristics
PMOS NMOS
L/W 90nm/10um 90nm/10um
Vt 0.08V 0.4V
Gmax 4.59E-4 1E-3
On/off ratio 107 107
S.S. ~89mV ~82mV -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.010-1310-1210-1110-1010-910-810-710-610-510-410-3
PMOS
ID(A
/m
)
VG(V)
lVDl=0.1V lVDl=1.5V
NMOS
-2 -1 0 1 20.0
1.0x10-4
2.0x10-4
3.0x10-4
4.0x10-4
5.0x10-4
6.0x10-4
7.0x10-4
8.0x10-4
ID(A
/m
)
VG(V)
lVGl=0.3V lVGl=0.6V lVGl=0.9V lVGl=1.2V lVGl=1.5V
CONFIDENTIAL 13
Platform performance• CMOS electrical characteristics
0 100 200 300 40010-14
10-13
10-12
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
NMOS 0980236-Gox20A SiN(MSW) NMOS 0980236-Gox25A SiN(MSW) NMOS 0980236-Gox20A TEOS(MSW) NMOS 0980384-LDDimplant 7KeV MSW1300 NMOS 0980217-As SDimplant MSW1000 NMOS 0980217-As+P SDimplant MSW1000 NMOS 0980217-As+P SDimplant MSW850
Ioff(
A/u
m)
Ion(uA/um)0 20 40 60 80 100 120 140 160 180
10-14
10-13
10-12
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
Ioff(
A/u
m)
Ion(uA/um)0 20 40 60 80 100 120 140 160 180
10-14
10-13
10-12
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
PMOS 980236 Gox25A PMOS 980236 Gox20A SiNspacer PMOS 980236 Gox20A TEOSspacer
Ioff(
A/u
m)
Ion(uA/um)0 20 40 60 80 100 120 140 160 180
10-14
10-13
10-12
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
PMOS 980236 Gox25A PMOS 980236 Gox20A SiNspacer PMOS 980236 Gox20A TEOSspacer PMOS 980384 MSW1300 SDimplant BF2 15KeV
Ioff(
A/u
m)
Ion(uA/um)0 20 40 60 80 100 120 140 160 180
10-14
10-13
10-12
10-11
10-10
10-9
10-8
10-7
10-6
10-5
10-4
PMOS 980236 Gox25A PMOS 980236 Gox20A SiNspacer PMOS 980236 Gox20A TEOSspacer PMOS 980384 MSW1300 SDimplant BF2 15KeV PMOS 980238 MSW1000 SDimplant BF2 PMOS 980238 MSW1000 SDimplant BF2+B
Ioff(
A/u
m)
Ion(uA/um)
CMOS-NMOS 1
CMOS-PMOS 1
CMOS-PMOS 2CMOS-NMOS 2
NMOS PMOS
General Idsat performance:
NFET/PFET ~200/100 uA/um at 1.5V
CONFIDENTIAL 14
Platform performance• 90nm Single MOS/CMOS Ion‐Ioff status
• 201 stages CMOS‐Ring oscillator
• Vp-p=1.24 V• T=169 ps/stage
(Ref:25 ps/stage from Chartered 0.13um LP)
• Suggest gate density: 380 gates/mm2
(Ref:220K gates/mm2 from Chartered 0.13um LP)
201 stages inverter 85 stages buffer
Platform performance
CONFIDENTIAL 15
MES線上申請MES線上申請
對外服務處
(簡秀芳,7610)
對外服務處
(簡秀芳,7610)
1. 資料註冊 2.結案
3.通知取貨
1. 資料註冊 2.結案
3.通知取貨
製程服務組(賴東彥,7515)製程服務組(賴東彥,7515)
1.接單 2.審核
3.下線 4.完工
1.接單 2.審核
3.下線 4.完工
光罩製作
(洪鶯玲,7746)
光罩製作
(洪鶯玲,7746)
1.接單 2.審核
3.製作 4.交件
1.接單 2.審核
3.製作 4.交件
CONFIDENTIAL 16
NDL 90 nm CMOS device ‐連續製程委託送件流程
•Mask manufacture•Lithography
•PR Trimming•Etch
•Customer management•Job arrangement•Manufacture
•ADI•ATI•AEI
委託者製程服務組
微影光罩組
蝕刻薄膜組
CONFIDENTIAL 17
NDL 90 nm CMOS device ‐相關事務
Lithography Testing
ADI(I)
Lithography
ADI(II)
Trimming Testing
ATI(I)
Trimming
ATI(II)
Etch O/P
AEI
Rework(II)
Rework(I)
Section 1(Lithography Process)
Section 2(Etch Process)
CONFIDENTIAL 18
NDL 90 nm CMOS device ‐ Poly Gate Definition Flow
Lithography Testing
黃光技術員
Dose Matrix
ADI(I)
User
1.Check CD2. Chose Dose
Rework(I)
黃光技術員
(MES 拉站)
蝕刻技術員
(PR remove)
Lithography
黃光技術員
I‐line Exposure
ADI(I)
User
Check CD
Section 1 ( Lithography Process )
* 閘極曝光量測試(Gate Exposure Dose Testing)
* 第一次閘極曝光量測試檢測(1 st After Develop Inspection )
•光阻去除(PR Remove)
* 閘極曝光(Gate Exposure )
* 第二次閘極曝光檢測(2 nd After Develop Inspection )
CONFIDENTIAL 19
NDL 90 nm CMOS device ‐ Gate Lithography Process
Trimming Testing
蝕刻技術員
Trim PR
ATI(I)
User
Check CD
Rework(II)
蝕刻技術員
1.MES 拉站
2.PR remove
Trimming
蝕刻技術員
Trim PR
ATI(II)
User
Check CD
Etch O/P
蝕刻技術員
Etch TEOS/Poly
AEI
User
Check CD
Section 2 ( Etch Process )
•第一次閘極光阻削薄檢測(1 st After Trimming Inspection )
•第二次閘極光阻削薄檢測(2nd After Trimming Inspection )
•光阻去除(PR Remove)
* 閘極蝕刻(Gate TEOS/Poly Etch)
•閘極蝕刻後檢測(After Etch Inspection )
•閘極光阻削薄測試(PR Trimming Testing )
•閘極光阻削薄(PR Trimming )
CONFIDENTIAL 20
NDL 90 nm CMOS device ‐ Gate Etch Process
Coordinator Assistant(Co-work)
Question Answer
ADIATIAEI
User 黃光技術員,蝕刻技術員
1. ADI Deviation(Range)
2. ATI Deviation(Range)
3. Machine Time(In-line SEM)
1. 使用者必須具備 In-line SEM qualification。
2. 若User需要ADI,ATI,AEI協助,可由技術員幫忙完成操作,但技術員僅提供協助,ADI/ATI/AEI仍須由User親自確認並簽名,才可過站。
3. 由微影組同仁提供公版ADI,ATI,SEI rule (Die number, CD coordinate) 。
4. ADI Deviation (0.27um <0.3um< 0.33um) 。
5. ATI Deviation(100nm <110m <120nm ) 。
6. Check 5Die /per wafer. If 3dies CD Ok, pass。
7. Per run < 10 Wafers。
CONFIDENTIAL 21
NDL 90 nm CMOS device ‐Q&A
Coordinator Assistant(Co-work)
Question Answer
Lithography 黃光技術員 User,黃光工程師(許進財)
1. 請問何時安排90nm lithography?
2. 如何配合90nm ADI,預約In-line SEM時段?
1. 初期以每星期一批run為主
2. 配合90nm製程,I-line機台使用時間為每星期二上午時段
3. 同時搭配In-line SEM時段
4. 光阻為厚光阻
Trimming 蝕刻技術員 User,蝕刻工程師(許倬倫)
1. 請問何時安排90nm trimming?
2. 如何配合90nm ATI,預約In-line SEM時段?
1. 初期以每新星期一批run
2. 配合90nm製程,機台使用時間為每星期三上午時段
3. 同時搭配In-line SEM時段
CONFIDENTIAL 22
NDL 90 nm CMOS device ‐Q&A
CONFIDENTIAL 23
NDL 90 nm CMOS device ‐Q&ACoordinator Assistant
(Co-work)Question Answer
委託接單 製程整合工程師(賴東彥)
User,製程整合工程師(賴東彥)
1. 如何送件?
2. 如何聯絡?
1. 請上NDL網頁註冊帳號,並使用MES系統申請90nm連續製程委託代工服務,請特別標註90nm製程委託
2. 對於90nm連續製程委託代工服務有任何疑問,請與工程師賴東彥先生(分機7515)聯絡,或E-mail至[email protected]信箱聯絡
MASK 光罩工程師(洪鶯玲)
User 1. NDL是否提供公版90nm光罩?
2. 請問90nm光罩設計需要注意什麼?(Test key, Mark…etc.)
1. NDL Release public Mask(ndl-90nmCMOS-fv3),layout請上網dowland
2. Mask design rule 由微影組同仁提供
1. 所有90nm標準元件委託送件皆須符合NDL一般送件流程與應遵守之相關規定,委託者須充分了解並同意後,始得送件;如有任何問題,請於申請委託前與各相關負責人連絡。
2. NDL所提供之90nmMOS 元件公版光罩,需搭配 v1.0 Baseline 條件製作,僅提供驗證功能;如需使用可於申請單上註明光罩名稱即可,亦可抽換或搭配委託者自己的光罩使用,NDL不保證抽換或搭配委託者自己的光罩之結果。
3. 委託者可於NDL MES系統上自行查看委託件之進度,並依照技術員指定之時間,配合 ADI / ATI / AEI 等檢測,如有任何問題可與技術員或工程師連絡。
CONFIDENTIAL 24
NDL 90 nm CMOS device ‐注意事項
NDL fab Equipment Layout
CONFIDENTIAL 25