EEWeb Pulse - Issue 1, 2011

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In Memory of

Bob PeaseAnalog Designer

1940 - 2011

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TABLE OF C ONTENTS

Remembering Bob Pease 4Memories of Bob Pease from his friends, colleagues, and associates.

Bob Pease 7ANALOG DESIGNERTribute interview with Bob Pease - analog designer for National Semiconductor for 34 years.

Putting the R in RTL 10BY RAY SALEMI

Selecting Passive Components with 13a Buck ConverterBY TAMARA SCHMITZ WITH INTERSIL

RTZ - Return to Zero Comic 17

Make the right choice the first time. Choosing the right passive components can save you a lot of time.

Coding registers in Verilog and VHDL - learn how to code the four basic styles of flip-flops.



MEMORIES

“I first met Bob when I was interviewing for an applicationengineer position about 28 years ago. I did not interview

with him, but when lunch time came around, I went toeat with him and my hiring manager, Al Kelsch. AlthoughI had just met them both, I could tell right away thatthese two individuals had very different styles. I couldtell that Bob was a rather rambunctious, outgoing guy,and Al was a very straight-laced, conservative guy. For a

company to have these two completely different people working together that seemed to get along so well, Ifigured this would be a good place to come. So whenI was given the offer to join, I jumped at it because Ithought it was going to be good, and I was going to getthe chance to work with both Al and Bob.

When we went out, Bob was going to drive in his Volkswagen. The first thing he did was open up thedoor and clear out a spot in the back seat for Al to sit. Ipiled into the front seat, and as we were getting ready to leave, Bob said, “Hey, do you like to bake bread?”

And I said, “Sure.” So out from under his driver’s seathe pulled the recipe for bread. I thought that was kindof cool.”

“There were sort of two aspects of Bob’s style as adesigner. One aspect was that he emphasized firstthinking about the problem and figuring out what theanswer should kind of look like, so he could recognizeit when he saw it. This also allowed him the ability to

detect when he was wrong. As an example, he and I dida joint paper a number of years ago for a power supply conference. The topic was related to the tools that

we offered to go along with our SIMPLE SWITCHERregulators. I was talking about the tools, and he wastalking about the use of the tools and how to get goodresults. He was emphasizing thinking, understandingthe design, and doing bench validation so that users

don’t get fooled by possible mistakes. More simply, he would kind of make an assumption, and test it to see if he was correct. But it was necessary for him to kind of know the magnitude of the answer he was aiming for sohe could interpret whether he was looking at the rightanswer or not.

He had another approach also, which was to be very collaborative. If he was working on a problem, or hehad a design that he wanted to make sure was sound,he would call together a bunch of people. This includedreviewers, friends, and anyone else that he figured

would have a helpful opinion. Sometimes he wouldcall a “beer check.” In other words, if someone foundan error, he or she earned a beer. If he was writing anarticle, he would distribute it to a panel of reviewers,and we would all get a chance to chime in and say what

we thought was right, wrong, good, or bad. His panelprobably had 30 or 40 reviewers for most of his columnsand books.”

Wanda Garrett, National Semiconductor

Bob Pease was killed in a tragic car accident on June 18 after leaving a memorial for Jim Williams, acolleague and fellow analog circuit designer. Bob devoted so much of his life to helping his fellow engineer, and his untimely death deeply affected the electrical engineering community.

We had the privilege to speak with some of Bob’s friends, colleagues, and associates who kindly took a moment to share their memories of Bob.

Remembering

Bob PeaseAnalog Designer, 1940-2011



MEMORIES

“If Bob felt someone deserved his respect, he made hisrespect evident. He didn’t just respect anyone becauseof his or her job title, which probably annoyed some of

the supervisors. If he saw that a person was sensible,that he or she could think and contribute, then thatperson got his respect. What mattered to him was theability to think and analyze.”

“One thing that most people might not know about Bobis his interest in music. He really enjoyed a lot of obscuremusic from the 40s, 50s, and 60s. He had a very nice,high tenor singing voice; he really enjoyed singing.One of the reasons he was so excited to move to SanFrancisco was that he could sing in a large cathedralthere.

He was also part of the singing club at National, andone of the songs that he had a lot of fun with was kindof a novelty song called “The Green-Eyed Dragon withthe Thirteen Tails.” He and I worked that one up andthat was one of his signature songs. He sang it while Iplayed the piano.”

“He used to stash a variety of signs under his driver’sseat. This was so when he would see another driver

with, for example, a broken tail light, he would beable to communicate the issue to that person using a

designated sign.”

“I had been corresponding with Bob in emails regarding various applications before I met him. When I was finally introduced to him, I shook his hand and said, “Bob, youknow I’ve been corresponding with you over the pastcouple of years, and now that I’ve met you, I like you inspite of yourself.” He threw back his head and started to

laugh. And he said, “You know Ken, I like you too.” And we were friends from there on in whenever I would visitthe west coast to meet with him. “

“Bob and I used to just go to lunch, chew the fat aboutthings in general like Analog Devices, National, histrips, and of course his clunky old Volkswagen.”

“Bob had one of the desks like mine—piles of junkall over the place! But he still knew where everything

was. That’s how Bob was; what looked like chaos to anoutsider was Bob’s own special form of organization.”

“We used to talk about SPICE and how we hated it,because some engineers lived with SPICE. And he toldthem, “Solder up the circuit and run it that way. That’sthe real way because SPICE is just an emulation. AndI used to tell Bob, “Tell them to solder their fingerstogether.”

“Back in 1990 I was going to the College of San Mateo,and I was recruited to come and interview with Bob

for a job at National. I came into the interview kind of reluctantly because I was actually sick that day. I camein, went through the interview process, and talked toBob, who was very reassuring, telling me, “Don’t worry,don’t worry.” Days later I came home and my momsaid, “This really strange guy stopped by to drop off this letter. He was driving a Volkswagen that looked likea dinosaur.” In the letter was an offer to work as Bob’stechnician. The fact that he was willing to personally deliver the job offer meant a lot to me, and is a testamentto the type of person he was.”

“He had an office, a couple lab benches, and at onepoint, before he retired, he had basically an entireroom because the mess was getting too large, andencroaching on others’ benches. On his bench werea Kepco power supply, a Tektronix 475 oscilloscope,usually a Wavetek 176 function generator, and piles of Fluke DMMs.”

“Bob would have many ideas for me. He would comeup with a concept, scribble out a circuit, and give it tome to build. I would either do an air-wire circuit like he

would do, or I would actually do a neat one. I wouldthen tweak it, and he would come by while I was doingthe measurements. Bob couldn’t do this because, whilehe was talking on the phone he couldn’t build circuits.So I was doing his leg-work at the time.”

“He was a master with a soldering iron. On the cover of his troubleshooting book, there is a board with all of the

wires floating up in the air. It’s for the LM331 voltage-to-

Continued: Wanda Garrett

Ken Baker, Analog Devices

Paul Grohe, National Semiconducto r



MEMORIES

frequency converter. That is how he did it. Every trace was a resistor, and between traces was a capacitor, builtup in the air like that. Everything was built on copper-

clad and wire-wrap sockets.”

“Bob loved LF411s. They were his favorite part. Healso loved 2N3904s and 2N3906s. He would go throughbuckets of those parts. He always kept it very simple asfar as his parts selection; he always knew how to pushthe parts.”

“There is no way to dissect the way he would think. He was just so intimate with the knowledge of the circuits,and had seen and done it all. You could draw a circuit inany direction and Bob could figure it out.”

“My favorite expression of his was, Show me where it

says I can’t do it.”

Continued: Paul Grohe

Bob loved LF411s. They were hisfavorite part. He also loved 2N3904sand 2N3906s. He would go throughbuckets of those parts.

Image: One of Bob Pease’s circuits, courtesy National Semiconductor.



MEMORIES

Robert PeaseAnalog Designer How did you get intoelectronics/engineering andwhen did you start?

I was 17 years old when I started.I built a Knight-kit 10-watt audioamplifier. When I was a kid I wasnot into car radios or things like

that. I was not one of those kids who took apart my father’s carradio and put it back together anddid it ten more times. I never didthat. It is very simple. I came in late.

I was good at physics and math.In my senior year at MIT, I wastaking some physics courses, Ithink it was course #8.721 andI said, “This stuff isn’t physicalanymore.” You know, quantum

theory and eigen vectors. Andthen I thought maybe I should get

into electronics, and I did, andit was fun! I had a good piece of luck. I think it was my sophomore

year at MIT, with Len Kleinrock, who has recently been properly hailed, 50 years late, as one of theinventors of the internet. He was

one of the better teachers I’vehad and I really enjoyed learningabout electronics design.

Well, I am still doing design withPiecewise Linear ElectronicCircuits and transistors. So that’show I snuck up on electronics.

After MIT, where did you rstgo to work?

Even before I left MIT, I went

over to Philbrick Researchesand I helped do some technical

writing. I may not have beenthe best engineer at that timebecause I would have beenas green as you can get, but Ihelped them produce some datasheets, which then got into moreelectronics and transistor design.

Before you got into designingICs, what were you doing?

I was doing board-level circuitdesign, and that was a lot of funbecause we could make money outof it. One of my buddies inventedthe P2, which was about 3” x 1.5”

x 1”. We were selling that thing

that used about enough partsto make a seven-transistor AMradio, for $220. That was a lot of money back in 1961. So we figuredout how to do things that otherpeople were not able to do. Wepackaged them nicely, wrote goodapplication notes and there youare. That was the Philbrick legacy.

You can still find the Philbrick

Applications Manual. AnalogDevices was nice enoughto publish it as a service topeople who are trying toremember the “good old days”of engineering design.

Generally, I do not do muchdigital. I know how to use a D-flipflop and gates, but I just do notdo that much digital design. Thatis its own specialty. I have never

made a mistake writing software,because I do not write software.

Do you have any favoritecircuits?

For many years one of my favoritecircuits was the Philbrick 4701

voltage-to-frequency converter andit was 0.1 percent linear with a nice

Photos taken by Jason Doiy, Professional Photographer

This interview was taken on April 26th of this year.



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in RTL:RPutting the

Ray Salemi Application Engineer

Many years ago, when I was a young man and the Boston RedSox had just lost the 1986 worldseries, controversy stalked the landof hardward development. A new technology called Register TransferLanguage or RTL threatened toreplace the time honored traditionof placing gates on schematicsand connecting them by hand.(This technology had replaceddrawing gates on paper andconnecting them by hand.)

Those who advocated RTLpredicted a new day, in which it

would be easy to generate designsof 50,000 gates or more, whilethose who wanted to remain with

schematics claimed that they couldeasily design more efficiently andkeep up with the RTL designers.But soon, as ASICs toppedhundreds of thousands of gates andthen a million gates, the schematicdesigners were left in the dust.

Fifteen years later the schematic

vs RTL controversy flared again inthe world of FPGA. As I listenedto engineers argue the meritsof RTL vs schematic capture,I could swear that I had beensucked into a wormhole anddropped back into the 1980s. Of course, I knew how the RTL vs.schematic argument would endhaving seen it all before. RTL

won before and has won again.

This column is devoted to RTLdesign. Each month, it will discussanother wrinkle in the seemingly simple design cycle of writingRTL, simulating it, and runningit through a synthesis tool. We’lllook at how synthesis tools react

to RTL and how to write testbenches to make sure the RTLis doing what you want it to do.

This month we are going to kick off our set of columns by discussiongthe most basic of Register TransferLanguage actions: transferingdata into a register. We’re going

to look at the coding styles youuse in order to get your EDA toolssuch as synthesis and simulation torecognize what you are trying to do.

One might think that EDA toolsshould be able to take any formof RTL code and figure out how

to make logic that will implementit. For the most part, one wouldbe right, because as long as you

write something that can, in some way, be construed as describinghardware, you will get results outof an EDA tool. However, if yourcode doesn’t follow the industry’sstandard RTL coding styles, youmay get different kind of hardwaredepending upon the synthesis

tool you use. What’s worse, yoursimulation tool may interpret thehardware differently than thesynthesis tool, and the you’ll havesimulation/synthesis mismatches.

We’re going to look at how youcode four basic styles of flip-flops,and we’ll use this coding style

Ray Salemi is a veteran of the EDA industry and has been working withHardware Description Languages sincehe joined Gateway Design Automation—the company that invented Verilog. Overthe course of his career he has worked atCadence, Sun Microsystems, and MentorGraphics. Ray is currently an ApplicationsEngineer Consultant with Mentor Graphics.



FEATURED ARTICL E

as the basis for future articleson synthesis and simulation.

The Basic Flip FlipThe basic flip flop is a flip flop

with clock, an input, and an output. When we see a positive edge onthe clock, the input signal getsflopped into the output. We can seehow to code this flip flip in Figure 1.

The code at the top of thisexample is a VHDL process thatdescribes this flip flop, and thecode at the bottom is a completeSystemVerilog module that doesthe same thing (SystemVerilog hasreplaced Verilog in the industry).

Both code snippets contain a

process which is sensitive tothe clock. The VHDL process issensitive to all changes on theclock, and we check for the risingedge on line 17. The Verilogalways block is only sensitive tothe rising edge of the clock.

In both cases, when the code sees

a rising edge it places the value of d into q and we have a flop. We cansee what this flop looks like in thepicture in the middle. This picture

was generated using MentorGraphic’s synthesis tool, Precision.It shows clk, d, and q. The setand reset signals are grounded.

The Basic Flop with aSynchronous ResetOf course, you would never wantto use a flop such as the one inFigure 1 because the lack of a reset

will create problems when you try to simulate your design. Withoutthe reset, you’ll have X’s in yoursimulation. These may go away, butthey will cause mismatches if youtry to make your RTL simulationmatch your gate level simulation.

18

19

20

21

22

23

24

25

26

27

ff_proc: process (clk)begin

if (clk = '1' and clk'event) thenif (rst_n = '0') then

q <= '0';else

q <= d;end if;

end if;end process ff_proc;

4

5

6

7

8

always @(posedge clk)if (!rst_n)q <= 0;

elseq <= d;

d

qclk

rst_nin out

ix3

reg_q

DFFRSE

CE

D

Q

R

S

We can write code so that thesynthesis tool will take advantageof the reset pin that exists onall flip flop models (see Figure2). In Figure 2, we’ve addeda reset signal to the inputsof the flop called rst_n.

Once our process is activated by the positive edge of the clock, wecheck rst_n and if it is 0, we storea zero in the q output. Notice that

we do not attach the rst_n signalto q. While this may work properly

with some synthesis tools, others will get confused to see a resetsignal being used for data.

Notice that type of flop that wasinstantiated by the synthsis tool:DFFRSE. This is a flop with asynchronous reset signal.

The Basic Flop with an

Asynchronous ResetIf we want our flop to resetimmediately when rst_n goesto 0, we need to implement anasychronous reset. We do thisby adding the rst_n signal to thesensitivity list of our process. Now the process will execute whenthe reset signal changes valueand we can check for the reset.

We can see the asynchronous

reset implemented in figure 3.

17

18

19

20

21

22

23

24

ff_proc: process (clk, rst_n)begin

if (rst_n = '0') thenq <= '0';

elsif (clk = '1' and clk'event) thenq <= d;


1

2

3

4

5

6

7

8

9

10

module ff (output reg q, input d,input rst_n, input clk);

always @(posedge clk or negedge rst_n)if (!rst_n)q <= 0;

elseq <=d;

end module

d

qclk

rst_nin out

ix1

reg_q

DFF

D

Q

R

S

Figure 1

Figure 2

Figure 3

15

16

17

18

19

20

ff_proc: process (clk)begin

if (clk = '1' and clk'event) thenq <= d;


1

2

3

4

5

6

7

module ff (output reg q, input d,input clk);

always @(posedge clk)q <=d;

end module

d

qclk

reg_q

DFF

D

Q

R

S



Notice that the VHDL is sensitiveto any change to rst_n and checksto see if the rst_n signal is 0before it transfer the data. The

Verilog code is only sensitiveto the negative edge of reset.If we allowed it to be sensitiveto both edges of rst_n, then thereset could act like a clock on itspositive edge. We don’t want that.

The Basic Flop with

Asynchronous Reset anda Clock EnableThe final pattern we’ll examineis a flop with a clock enable. Wecan see the implementation inFigure 4. We’ve added anothersignal to the input ports, and wecheck the clock enable just before

we transfer the data from d to q.

18

19

20

21

22

23

24

25

26

27

ff_proc: process (clk, rst_n)begin

if (rst_n = '0') then

q <= '0';elsif (clk = '1' and clk'event) thenif (ce = '1') then

q <= d;end if;


1

2

3

4

5

6

7

8

9

10

11

module ff (output reg q, input d,

input rst_n, input ce,input clk);

always @(posedge clk or negedge rst_n)if (!rst_n)q <= 0;

elseif (ce) q <=d;

end module

d

qclk

ce

rst_nin out

ix1

reg_q

DFFE

CE

D

Q

R

S

Notice that Precision recognizedthe pattern for the clock enableand attached the signal to thepreviously unused CE port onthe flop model. Now we’ll use

whatever clock enable schemeour FPGA technology implementsto have a clock enable.

SummaryIn this article, we discussedthe fact that synthesis andsimualtion tools are happiest

when we use recognized codingpatterns. Then we looked atthe coding patterns that definefour common flip flops. In nextmonth’s article we’ll examine

ways of creating combinatoriallogic in RTL and some of the

ways that our combinatorial codecan create unexpected latches.

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Passive Components

Buck Converter

Selecting

with a

Often, power design is thelast consideration in asystem. Then, most users

want a box that just works—takingin one DC voltage and producinganother. This box can take variousforms. It can be a step-down togenerate a lower voltage or step-up to generate a higher voltage.There are also plenty of specialoptions, like step-up/down, flybackand single-ended primary inductorconverter (sepic), which is aDC-DC converter that allows theoutput voltage to be greater than,less than, or equal to the input

voltage. For a system that will runon AC power, the first AC-to-DCblock will probably create thehighest DC voltage level needed

by the system. Therefore, themost widely used devices arestep-down converters, also calledbuck converters. Here we will start

with a basic step-down voltageconverter selected to help lightload efficiency and then discussthe consideration for selectingthe surrounding components.

The two main types of step-down converters are Low Drop-Out (LDOs) and switchingregulators. LDOs give clear andstable voltages while switchingregulators are optimizing formore efficient operation. Highefficiency means less energy islost in the conversion, simplifyingthermal management. The morecurrent that needs to be produced

means a bigger system whichgenerates more heat. Sinceswitching regulators have higherefficiency and are the mostprevalent solution, we are focusingon them here. Furthermore, tosimplify the discussion, we’ll limitourselves to buck (step-down)converters for simplicity. Figure1 shows the basics of a type of step-down switching regulator, asynchronous buck converter. Theterm synchronous buck indicatesthat a MOSFET is used as thelower switch (labeled in Figure1 with Ilower going through it.)Comparatively, a standard buckregulator has a Schottky diode asa lower switch. The main benefitof a synchronous buck regulator

Tamara Schmitz Intersil Corporation



TECHNICAL ARTICLE

compared with a standard buckregulator is better efficiency due to a lower voltage drop of the MOSFET versus a diode.

The timing information for thelower and upper MOSFETsis provided by a pulse-widthmodulation (PWM) controller.There is only 1 input shown inFigure 1 to the PWM while in many schematics there are two inputsto the PWM. The second input

voltage to the circuit is the supply voltage of the PWM. The drawninput to the controller is a voltage

fed back from the output. This

loop allows the buck converter

to regulate its output in responseto load changes. The outputof the PWM block is a digitalsignal toggling up and down atthe switching frequency. It turnson only one MOSFET at a time.

Allowing both MOSFETs to beon simultaneously would causea short from Vin to GND, which

would destroy efficiency and isnot advised. The duty cycle of thissignal determines the percentageof the time that the input is directly connected to the output. Thus, theoutput voltage is the product of input voltage and this duty cycle.

Choosing the ICThe control loop noted aboveallows the buck converter tomaintain a steady output voltage.That loop can be implementedin a number of ways. Thesimplest converters use either

voltage or current feedback.

These converters are rugged,

straightforward and cost-effective. As buck converters began to beused in a variety of applications,a weakness was found. Considerthe power circuitry for a graphicscard. As the video contentchanges, so does the load on thebuck converter. The system canhandle a wide range of changes,but the efficiency rapidly degrades

for light load conditions (whenonly a little current is needed.) If efficiency is a concern, it’s time fora better buck converter solution.

One such improvement is calledhysteretic control. An example isthe Intersil ISL62871. The efficiency

versus load is presented in Figure2. These converters are designedfor worst-case conditions, so lightload is not a permanent situation.These DC:DC converters arebetter at coping with changes inload variations without drastically affecting system efficiency. Figure

2 shows the efficiency of theISL62871 measured with differentoutput currents. This variancein output current shows theperformance for different loads.

Choosing the SwitchingFrequency

Although switching frequency issometimes fixed for a device, itis still worth discussing it. The

chief trade-off is efficiency. In thesimplest terms, the MOSFETshave a certain turn-on and turn-off time. As the frequency increases,the transitional time increases asa percentage of the total period.The result—the efficiency isreduced. So if efficiency is themost important design goal,consider lowering the switchingfrequency. If the efficiency of the system is adequate, then

you might be able to allow ahigher switching frequency. Thehigher frequency will allow theuse of smaller external passivecomponents, namely the outputinductor and capacitors, toreduce your system size.

Figure 1: Basics of a Synchronous Buck Converter

+PWM -VL

VOUT

IOUT

COUT

ILO

L

IUPPER

ILOWER

VIN

CI

VPHASE



TECHNICAL ARTICLE

External Components While you could be ambitiousand try to design a fully discretesolution of about 40 components –

that requires significant additionaleffort. Alternatively, let’s examinethe external components in Figure1 and the parasitics they play inthe performance of the system.

The five additional components we must select are the inputcapacitance, the outputcapacitance, the output inductor,and the upper and lowerMOSFETs. The output inductor is

selected to meet the output ripplerequirements and to minimizethe PWM’s response time to achanging load. The lower boundof possible inductor values isset by the ripple requirement.Before running out to find thesmallest (and possibly cheapest)inductor that will work for you,remember that they are not ideal.Real inductors have a saturation

level. That saturation level mustbe higher than the peak current inthe system to create a successfuldesign. Experienced designersalso know that the inductanceisn’t constant versus current.In fact, the value of inductancedrops as you pull more currentthrough the component. Checkthe inductor datasheet to ensurethat your chosen value canhandle the peak current in yoursystem. It seems that erring onthe larger side might be the bestinductance choice. There is abalance, though. Larger valuesof inductance do reduce outputripple, but they will also limit theslew rate. Too large an inductance

value will limit response time to

a load transient. So, in selectingthe inductor, there is a clear trade-off between a quieter output dueto lower peak-to-peak ripple orneeding the system to respond

quickly to a load change.

The input capacitance, C1, isresponsible for sourcing the ACcomponent of the input currentflowing into the upper MOSFET.Therefore, the RMS currentcapacity must be sufficient tohandle the AC component of the current drawn by that upperMOSFET. It is common to use amix of input bypass capacitors

in parallel point. For quality andlow temperature coefficient,ceramic capacitors can decouplethe high frequency components.Bulk capacitors supply the lowerfrequency RMS current, whichis tied to the duty cycle. (Thereis more RMS current whenthe system is operating further

from 50% duty cycle.) The bulkcapacitance can be severalmulti-layer ceramic capacitors inparallel. In lower cost applications,however, several electrolytic

capacitors are typically used.In surface mount designs, solidtantalum capacitors may be chosenfor C1, but be careful to note thecapacitor’s surge current rating.(Surge currents are common atstart-up.) When choosing any capacitor in the buck convertersystem, look for small equivalentseries inductance (ESL) andsmall equivalent series resistance(ESR) in addition to the totalcapacitance required. One finalhint in regard to capacitor voltageratings: To minimize hard-to-findfailures, choose capacitors withratings 1.2 to 1.3 times greaterthan the input voltage, that is,the voltage across them.

The output capacitor COUT must

Figure 2: Efficiency versus Load for the Intersil ISL62817 with Vout=1.1V

100

95

90

85

80

75

70

65

60

55

50

E F F I C I E N C Y ( % )

IOUT (A)

0 2 4 6 8 10 12 14 16 18 20

VIN =12.6V

VIN =19V

VIN =8V



RETURN TO ZERO



RETURN TO ZERO

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