EELE 367 – Logic Design

Module 2 – Modern Digital Design Flow

• Agenda

1. History of Digital Design Approach

2. HDLs

3. Design Abstraction

4. Modern Design Steps

5. Implementation Options (FPGAs)

Module 2: Modern Digital Design Flow 2

History

• In the beginning…

1970's - designers used Paper/Pencil & Boolean Equations to create schematics - the drawback : - each flop required a Boolean equation - impractical in large designs

1980's - schematic based designs using electronic editors - this enabled Copy/Past & Hierarchy - Design-reuse was enabled which increased design sizes

mid 80's - HDL's became more common (created mid 80's) - Text-based Compilers (C, PASCAL) could be adapted to perform digital simulation - Larger Designs could be described using text

SimulationPhysical

Implementation

Design

Still separate

Module 2: Modern Digital Design Flow 3

History

• More recently

1990's - Synthesis became practical due to increase in computational power of computers

Synthesis - the creation of circuitry from a functional description

ex) "Functional Description of MUX"

if (Sel = 0) Out = A else Out = B

SynthesisA

BOut

Sel

Module 2: Modern Digital Design Flow 4

HDL

• Real Power

1990's - Now engineers had a power combination

"Synthesis"

A

BOut

Sel

"HDL"

if (Sel = 0) Out = A else Out = B

"Simulation"

Module 2: Modern Digital Design Flow 5

HDL

• Abstraction

Engineers could now stay at a higher level of abstraction and rely on the tools to

1) Simulation 2) Synthesize the circuitry

- This allows larger systems to be described/designed in the same time

- Since HW is expensive to build, using the tools to reduce prototyping was the next step

Module 2: Modern Digital Design Flow 6

HDL

• Timing Verification

- Let the tool "Verify" timing

- Less time spent prepping design for a prototyping run

FunctionalSimulation

Synthesis

HDL

TechnologyMapping

Place/Route(extract RC's)

Post ImplementationSimulationMatch?

Fab

Module 2: Modern Digital Design Flow 7

Design Abstraction

• At What level can we design?

Module 2: Modern Digital Design Flow 8

Design Abstraction

• What does abstraction give us?

- The higher in abstraction we go, the more complex & larger the system becomes

- But, we let go over the details of how it performs (speed, fine tuning)

- There are engineering jobs at each level

- Guru's can span multiple levels

• What does VHDL model?

- System : Chip : Register : Gate

- VHDL let's us describe systems in two ways:

1) Structural (text netlist) 2) Behavioral (requires synthesis)

Module 2: Modern Digital Design Flow 9

Modern Digital Design Flow

• Designing Large Digital Circuits

- this is the ideal process

Module 2: Modern Digital Design Flow 10

Digital Design Flow

• Designing Large Digital Circuits

- this is reality

Module 2: Modern Digital Design Flow 11

Digital Design Flow

• A More Detailed Breakdown Relation to our class

HW or Lab Assignment

Write VHDL, Simulate with ModelSim

Synthesize in Quartus, Run Timing Simuluation

Place/Route on FPGA, Download, Test

Take idea, create custom HW to reduce coststart your own companysell and become rich

Module 2: Modern Digital Design Flow 12

Digital Implementation

• What options do we have for hardware implementation?

- Discrete Devices (i.e., go to the stock room and buy NAND gates & Flip-flops)

- ASICs (Application Specific Integrated Circuits (custom silicon)

- Programmable Logic (CPLDs, FPGAs)

• FPGAs have become one of the most popular technologies recently

- We’ll use an FPGA in this class to test our designs

- We’ll use the ModelSim simulator for functional simulation

- We’ll use the Altera Quartus II design software for synthesis, place/route, and post-synthesis verification.

- We’ll use an Altera Cyclone II FPGA on a DE2 evaluation board to test our designs in hardware.

Module 2: Modern Digital Design Flow 13

FPGA's

• What is an FPGA

Field Programmable Gate Array

• An FPGA uses Re-configurable Logic Blocks

- we set the config bits of this block to set its Boolean logic function

- the configuration is a Truth Table (or Look Up Table) of functionality

OutIn1

In2

config

config Out000 NOT(In1)001 NOT(In2)010 OR011 NOR100 AND101 NAND110 XOR111 XNOR

Module 2: Modern Digital Design Flow 14

FPGA's

• LUTs = Look Up Tables

- we can program the LUTs to be whatever type of gate is needed by the design- there are a finite number of LUTs within a given FPGA (also called "resources")

• The LUTs are configured into an ARRAY on the silicon

- Array of LUT's = Array of Gates = Gate Array

OutIn1

In2

config

OutIn1

In2

config

OutIn1

In2

config

OutIn1

In2

config

OutIn1

In2

config

OutIn1

In2

config

OutIn1

In2

config

OutIn1

In2

config

OutIn1

In2

config

Module 2: Modern Digital Design Flow 15

FPGA's

• Programmable Interconnect

- there are programmable interconnect switches that connect the LUTs

LUT LUT LUT

LUT LUT LUT

LUT LUT LUT

X

X

X

X

X

X

X

X

X

X

X

X

X X X

XX

Module 2: Modern Digital Design Flow 16

FPGA's

• Configuration

- We start with a Gate Level Schematic of our design (from synthesis)- The FPGA LUTs are configured to implement Gates

LUT LUT LUT

LUT LUT LUT

LUT LUT LUT

X

X

X

X

X

X

X

X

X

X

X

X

X X X

XX

Module 2: Modern Digital Design Flow 17

FPGA's

• Configuration

- The interconnect switches are then programmed to implement the net connections

LUT LUT LUT

INV OR LUT

INV AND LUT

X

X

X

X

X

X

X

X

X

X

X

X

X X X

XX

A

B

C

Out

Module 2: Modern Digital Design Flow 18

FPGA's

• Configuration

- The LUT and Interconnect configuration is volatile (i.e., it goes away when power is removed)

- Since the programming is done by the user after fabrication, we call it "Field Programmable”

- We now understand where the name “Field Programmable Gate Array” comes from.

LUT LUT LUT

INV OR LUT

INV AND LUT

X

X

X

X

X

X

X

X

X

X

X

X

X X X

XX

A

B

C

Out

Module 2: Modern Digital Design Flow 19

FPGA's

• Adding More Functionality

- FPGA manufacturer's quickly learned that Flip-Flops would be useful

- They put a DFF next to a 4-Input LUT to form a "Configurable Logic Block" (CLB)

CLB CLB

CLB CLB

X

X

X

X X

Module 2: Modern Digital Design Flow 20

FPGA's

• Adding Even More Functionality

- To Improve performance, common logic functions were "hard coded" on the silicon

- Block RAM - Adders / Multipliers - Global Clock Buffers - even Microprocessors!

Module 2: Modern Digital Design Flow 21

FPGA's

• What else can we program?

- Which Pins to use on the package

- What logic levels

- CMOS_33, CMOS25 - SSTL, SSTL2, etc…