EEE5 Lec14 IC Fab Scaling ITRS
Transcript of EEE5 Lec14 IC Fab Scaling ITRS
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EEE 5
Lecture 14: IC Fabrication,
Scaling and the ITRS
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Integrated Circuit TechnologyPlanar fabrication process:
Simultaneous fabrication of many chips on a wafer, each
comprising an integrated circuit (e.g. a microprocessor or
memory chip) containing millions or billions of transistors
Method:Sequentially lay down and pattern thin films of
semiconductors, metals and insulators.
Materials used in a basic CMOS integrated circuit: Si substrateselectively doped in various regions
SiO2 insulator
Polycrystalline silicon used for the gate electrodes
Metal contacts and wiring
300mm Si wafer
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Formation of Insulating Films
The favored insulator is pure silicon dioxide (SiO2). A SiO2 film can be formed by one of two methods:
1. Oxidation of Si at high temperature in O2 or steam ambient
2. Deposition of a silicon dioxide film
ASM A412
batchoxidation
furnace
Applied Materials low-
pressure chemical-vapor
deposition (CVD) chamber
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Patterning the Layers
Li thographyrefers to the process of transferring a patternto the surface of the wafer
Equipment, materials, and processes needed:
A mask (for each layer to be patterned) with the desired pattern
A light-sensitive material (called photores is t) covering the wafer so asto receive the pattern
A light source and method of projecting the image of the mask onto thephotoresist (printer or projection stepper or projection scanner)
A method of developing the photoresist, that is selectively removing it
from the regions where it was exposed
Planar processing consists of a sequence of
additive and subtractive steps with lateral patterning
oxidation
deposition
ion implantation
etching lithography
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Pattern Transfer by EtchingIn order to transfer the photoresist pattern to an underlying film, we need a
subtractive process that removes the film, ideally with minimal change inthe pattern and with minimal removal of the underlying material(s)
Selective etch processes (using plasma or aqueous chemistry)have been developed for most IC materials
Jargon for this entire sequence of process steps: pattern using XX mask
photoresist
SiO2
First: patternphotoresist
Si
We have exposed mask pattern,and developed the resist
etch stops on silicon(selective etchant)
oxide etchant
photoresist is resistant.Next: Etch oxide
only resist is attackedLast: strip
resist
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The Photo-Lithographic ProcessOxidation or thin-film deposition
opticalmask
optionaladditional
process
step(s)
photoresist coatingphotoresistremoval (ashing)
spin, rinse, dry etch
photoresist
exposure
photoresist
develop
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Adding Dopants into SiSuppose we have a wafer of Si which is p-type and we want to
change the surface to n-type. The way in which this is done is by
ion implantat ion. Dopant ions are shot out of an ion gun called
an ion implanter, into the surface of the wafer.
Typical implant energies are in the range 1-200 keV. After the ion
implantation, the wafers are heated to a high temperature (>1000oC).
This annealing step heals the damage and causes the implanted
dopant atoms to move into substitutional lattice sites.
Eaton HE3
High-EnergyImplanter,
showing the
ion beam
hitting the
end-station x
SiO2
Si
+ + + +++
As+ or P+ or B+ ions
x
SiO2
Si
++ ++ ++ ++++++
As+ or P+ or B+ ions
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N-channel MOSFETSchematic Cross-Sectional View
Layout (Top View)4 lithography steps
are required:
1. active area2. gate electrode
3. contacts
4. metal interconnectschannel
width, W
gate length, Lg
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CMOS Technology
Both n-channel and p-channel MOSFETs arefabricated on the same chip (VTp = -VTn )
Primary advantage:
Lower average power dissipation Ideally, in steady state either the NMOS or PMOS device is
off, so there is no DC current path between VDD & GND
Disadvantages:
More complex (expensive) process Latch-up problem
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p-substrate
ND
n-well
NDn-well
NAp-well
Single-well technology
n-well must be deep enoughto avoid vertical punch-through
Need p-regions (for NMOS) and n-regions (for PMOS)on the wafer surface, e.g.:
NA
Twin-well technology Wells must be deep enough
to avoid vertical punch-through p- or n-substrate(lightly doped)
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Modern CMOS Fabrication
Process
A series of lithography, etch,and fill steps are used to create
silicon mesas isolated by
silicon-dioxide
Lithography and implant stepsare used to form the NMOS
and PMOS wells and to set the
channel doping levels
p-type Silicon Substrate
p-type Silicon Substrate
Shallow Trench Isolation (STI) - oxide
p-type Silicon Substrate
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The thin gate dielectric layer
is formed
Poly-Si is deposited andpatterned to form gate
electrodes
Lithography and implantation
are used to form NLDD and
PLDD regions
p-type Silicon Substrate
p-type Silicon Substrate
p-type Silicon Substrate
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A series of steps is used to
form the deep source / drain
regions as well as body
contacts
A series of steps is used to
encapsulate the devices and
form metal interconnections
between them.
p-type Silicon Substrate
p-type Silicon Substrate
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Intels 65 nm CMOS Technology
Lg = 35 nm
Tox = 1.2 nm
Strained Si channel
NMOS: tensile capping layer
PMOS: epitaxial Si1-xGex embedded in S/D
NMOSFET
PMOSFET
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CMOS Inverter
n+ p+ p+ n+ n+ p+
n-well p-Si
Vin
Vout
VDD
Vin Vout
VDD
Equivalent circuit:
VSS
SiO2
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CMOS LatchupCoupled parasitic npn and pnp bipolar transistors:
If either BJT enters the active mode,
the SCR will enter into the forward
conducting mode (large currentflowing between VDD and GND) if
bnpnbpnp> 1
=> circuit burnout!
Latch-up is triggered by a transient increase in current, caused by
transient currents (ionizing radiation, impact ionization, etc.)
voltage transientse.g. negative voltage spikes which forward-bias the pn junction momentarily
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How to Prevent CMOS Latchup
(a) n-well p epitaxial layer
p+-substrate
Rsub
npn
nn+ p-sub R
we
ll
pnpretrograde well
(b)
b
b
1. Reduce minority-carrier lifetimes in well/substrate
2. Use highly doped substrate or wells:
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IC Technology Trends
Continued scaling of MOSFETs toward 10 nm Lg: CMOSFETs with gate lengths below 20 nm have already been
demonstrated by leading semiconductor manufacturers.
The most advanced transistor designs are based on UC-Berkeley
research (Profs Hu, King Liu, Bokor).
Increasing # of levels of wiring (Cu interconnects)
Up to 8 levels of metal are used in ICs today.
Photo from IBM Microelectronics Gallery:
Colorized scanning-electron micrograph of
the copper interconnect layers, after removal
of the insulating layers by a chemical etch
Increasing variety of materials
high-k gate dielectric, metal gate, low-k intermetal dielectrics, etc.
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MOSFET Scaling
MOSFETs have scaled in size over time 1970s: ~ 10 mm Today: ~32 nm
Reasons:Speed (improves with L reduction)
Density (reduce chip per function lower cost per function)
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Benefit of Transistor Scaling
IDS as L (decreased effective R)
Gate area as L (decreased load C)
Therefore, RC (implies faster switch)
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Constant-Field Scaling
Circuit speedimproves by k
Power dissipation
per function
is reduced by k2
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The ITRS
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A Typical Technology Production Curve
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ITRS Technology Node Definition
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Technology Trends
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