EECS240_Advanced Analog IC Boser

EECS240

Advanced Analog IC Design

Bernhard E. Boser

Contents 1. L01_Introduction 2. L02_CMOS Technology 3. L03_MOSFET Models for Design 4. L04_Electronic Noise 5. L05_Bias Current Sources 6. L06_References 7. L07_Operational Trans-conductance Amplifiers 8. L08_Folded Cascode 9. L09_Feedback 10. L10_Feedback (Cont.) 11. L11_Common-Mode Feedback 12. L12_OTA Realizations 13. L13_Output Stages 14. L14_Comparator 15. L15_Coupling Mechanisms 16. L16_Device Matching Mechanisms 17. L17_MOS Sample & Hold 18. L18_Offset Cancellation Overview

EECS 240 Lecture 1: Introduction © 2004 B. Boser 1

EECS 240

Analog Integrated Circuits

© 2004Bernhard E. Boser

Department of Electrical Engineering and Computer Sciences


Administrative• Course web page:

http://www.eecs.berkeley.edu/~boser(link to EECS 240)

• Overview– Scope of course– Reference texts (no textbook)– Grading and homework policy

• Office hours (519 Cory Hall)– Tuesday 2:15 to 3pm– Thursday 4-5pm


Analog ICs in a “digital” World?

• Digital circuitry:– Cost/function decreases by 29% each year– That’s 30X in 10 years

• Analog circuitry:– Cost/function is constant– Dropping supply voltages threaten feasibility

• Transition to DSP is inevitable!

Ref: International Technology Roadmap for Semiconductors, http://public.itrs.net


Why Analog Processing?

• The “real” or “physical” world is analog– Analog is an interface technology– In many applications, it’s in the critical path

• Examples:– MEMS sensors and actuators– RF receiver– Wireline communications


MEMS Accelerometer

DSP

A/D Conversion

Amplification

C/V conversion

MEMS sensor

Acceleration

Digital Output

M. Lemkin and B. E. Boser, “A Three-Axis Micromachined Accelerometer with a CMOS Position-Sense Interface and Digital Offset-Trim Electronics,” IEEE J. Solid-State Circuits, vol. SC-34, pp. 456-468, April 1999. pdf


Example: RF Receiver• Goals

– Wireless communication– Minimizing use of bandwidth– Immunity to interference

• Circuit functions:– Preprocessing

• Filtering• Amplification• Frequency translation

– A/D Conversion– DSP

• Demodulation• Decoding

– D/A Conversion– Postprocessing

• Reconstruction filter• Amplification

Analog Postprocessing

D/AConversion

DSP

A/D Conversion

Analog Preprocessing

Analog Input

Analog Output


Syllabus• Devices

– Models– Simulation– Passive devices– Matching

• Support functions– Biasing– References– MOS Sample & Hold– Comparators

• Amplifiers– “Gate” of analog circuits– Critical element in virtually

all analog building blocks– Illustrates fundamental

analog design issues• Device characteristics• Electronic noise• Frequency & step response• Feedback & Stability

– Focus is design: from specifications to topology to layout


EECS 240 versus 247• EECS 240

– Transistor level building blocks– Device and circuit fundamentals– Little abstraction– SPICE

• EECS 247– Macro-models, behavioral simulation, large systems– Signal processing fundamentals– High level of abstraction– Matlab

EECS 240 Lecture 2: CMOS - passive devices © 2004 B. Boser 1

CMOS Technology• Why look at it (again)?• Key issues:

1. Perspective– Device dimensions– Device performance metrics, e.g.:

– Current efficiency– Speed– Gain– Noise

2. “Short-channel characteristics”– Square-law model– Models for circuit simulation– Design


Today’s Lecture

• CMOS cross-section

• Passive devices– Resistors– Capacitors

• Next time: MOS transistor


CMOS Process• EECS240 0.35µm 2P4M CMOS

– Minimum channel length: 0.35µm– 2 levels of polysilicon (for capacitors)– 4 levels of metal (aluminum)– 3.3V supply

• Other choices– Shorter channel length (0.12µm / 1.2V)– Bipolar, SiGe HBT– SOI


Supply Voltage

0

1

2

3

4

5

1 0.8 0.5 0.35 0.25 0.18 0.12 0.08 0.06

Feature Size [µm]

Sup

ply

Vol

tage

[V]


CMOS Cross Section

Metal

Poly

p- substrate

n- well

p+ diffusion

n+ diffusion


Dimensions

700mµ

6.5nm≥ 0.35µm

1.2mµ

200nm

Drawing is not to scale!


Devices

• Active– NMOS, PMOS– NPN, PNP– Diodes

• Passive– Resistors– Capacitors– Inductors


Resistors• No provisions in standard CMOS• Resistors are bad for digital circuits

– Minimized in standard CMOS• Sheet resistance of available layers:

• Example: 100kΩ poly resistor 1µm wide by 20,000µm long

60 mΩ/5 Ω/5 Ω/

1 kΩ/

AluminumPolysiliconN+/P+ diffusionN-well

Sheet resistanceLayer


Process Options

• Available for many processes• Add features to “baseline process”• E.g.

– Capacitor option (2 level poly, channel implant)– Low VTH devices– “High voltage” devices (3.3V)– EEPROM– Silicide stop option– …


Silicide Block Option

• Non-silicided layers have significantly larger sheet resistance

• Resistor nonidealities:– Temperature coefficient: R = f(T)– Voltage coefficient: R = f(V)

5050

-500-500

30,000

5050

500500

20,000

-800200

15001600

-1500

10018050

1001000

N+ polyP+ polyN+ diffusionP+ diffusionN-well

BC [ppm/V]VC [ppm/V]TC [ppm/oC]@ T = 25 oC

R/ [Ω/ ]Layer


Resistor ExampleGoal: R = 100 kΩ, TC = 1/R x dR/dT = 0

Solution: combination of N+ and P+ poly resistors in series

( ) ( )( )

squares 4.444kΩ801

1

squares 200kΩ201

1

11

0

==−

=

==−

=

⇒∆+++=∆++∆+=

CN

CPP

CP

CNN

CPPCNN

R

PN

CPPCNN

TTRR

TTRR

TTRTRRRTTRTTRR

44 344 2143421


Voltage CoefficientExample:Diffusion resistor

Applied voltage modulates depletion width(cross-section of conductive channel)

Well acts as a shield

p- substrate

n- well

p+ diffusion

n+ diffusion

R

V1 V2 VB

( ) ( )

−

++−+−+≈

−=

BCCo

Co VVVBVVVTTR

IVVR

2251 21

21

21


Resistor Matching• Types of mismatch

– Systematic (e.g. contacts)– Run-to-run variations– Random variations between devices

• Absolute resistor value– E.g. filter time constant, bias current (BG reference)– ~ 15 percent variations (or more)

• Resistor ratios– E.g. opamp feedback network– Insensitive to absolute resistor value– “unit-element” approach rejects systematic variations

(large area for non-integer ratios)– Process gradients– 0.1 … 1 percent matching possible with careful layout


Resistor LayoutExample: R1 : R2 = 1 : 2

gradient

R1

0.5 * R2 - ∆R

0.5 * R2 + ∆R

Dummy

Dummy


Resistor Layout (cont.)Serpentine layout for large values:

Better layout (mitigates offset due to thermoelectric effects):

See Hastings, “The art of analog layout,” Prentice Hall, 2001.


MOSFETs as Resistors• Triode region (“square law”):

• Small signal resistance:

• Voltage coefficient:

DSTHGSDSC VVVdV

dRR

V−−

==11

DSTHGSDSDS

THGSoxD VVVVVVVLWCI >−

−−= for

2µ

( )

( )DSTHGS

THGSox

DSTHGSoxDS

D

VVVVV

LWC

R

VVVLWC

dVdI

R

>>−−

≈

−−==

for 1

1

µ

µ


MOS ResistorsExample: R = 1 MΩ • Large R-values realizable in small area

• Very large voltage coefficient

• Applications:– MOSFET-C filters: (linearization)

Ref: Tsividis et al, “Continuous-Time MOSFET-C Filters in VLSI,” JSSC, pp. 15-30, Feb. 1986.

– Biasing: (>1GΩ)Ref: Geen et al, “Single-Chip Surface-Micromachined Integrated Gyroscope with 50o/hour Root Allen Variance,” ISSCC, pp. 426-7, Feb. 2002.

( )

( )

1

0

2

V5.0V21

1

2001

V2MΩ1VµA100

1

1

1

−

=

==

−=

=××

=

−=

−≈

THGSVVC

THGSox

THGSox

VVV

VVRCLW

VVLWC

R

DS

µ

µ


Resistor Summary• No or limited support in standard CMOS

– Costly: large area (compared to FETs)– Nonidealities:

• Large run-to-run variations• Temperature coefficient• Voltage coefficients (nonlinear)

• Avoid them when you can– Especially in critical areas, e.g.

• Amplifier feedback networks• Electronic filters• A/D converters

– We will get back to this point


Capacitor Applications

• Large value– Bypass capacitors– Frequency compensation

• High accuracy, linearity– Feedback & sampling networks– Filters


Capacitor Options

BigBig~ 1000Junction capacitors

120Poly-substrate

50Metal-poly

30Metal-substrate

302050Metal-metal

25101000Poly-poly (option)

BigHuge5300Gate

TC [ppm/oC]VC [ppm/V]C [aF/µm2]Type


MOS Capacitor• High capacitance in inversion:

– Linear region– Strong inversion

• SPICE:

M120 / 10

Vtac = 1VVtac = 1VVtac = 1V

VmosfetVmosfet

C11pF

VcapVcapVcapVcap

NetlistAC1 ac start=0 stop=3 freq=0.159 dev=Vt lin=50

IC

VVVIC

=→

=

=

=

πω

ω

211


MOS Capacitor

• High non-linearity, temperature coefficient

• Useful only for non-critical applications, e.g.

– (Miller) compensation capacitor– Bypass capacitor (supply, bias)


Poly-Poly Capacitor

• Applications:– Feedback networks– Filters (SC and continuous time)– Charge redistribution DACs & ADCs

• Cross-section• Bottom- and top-plate parasitics• Shields


Capacitor Layout

• Unit elements• Shields:

• Etching• Fringing fields

• “Common-centroid”• Wiring and interconnect parasitics

Ref.: Y. Tsividis, “Mixed Analog-Digital VLSI Design and Technology,” McGraw-Hill, 1996.


Metal Capacitors

• Available in all processes(with at least 2 levels of metalization)

• Large bottom plate parasitic– Often loads amplifier

increased load adds power dissipation

EECS 240 Lecture 3: MOSFET Models © 2004 B. Boser 1

MOSFET Models for Design• SPICE

– For verification– BSIM– Device variations

• Hand analysis– Square law model– Small-signal model– Design criteria

• Challenge– Complexity / accuracy tradeoff– How can we accurately design when large signal models suitable

for hand analysis are off by 50% and more?


Models for Designers• Perspective

– Physics– Simulator: accuracy & efficiency– Design:

• relate device characteristics to circuit specifications• E.g. speed, gain, power dissipation

• “Short-channel effects”– Square-law model– BSIM-X– Models for design must be simple & accurate


BSIM 3v3 Model

• Supported by most simulators• Accurate down to L=0.25µm and below• BSIM 4 for even smaller devices• 100 parameters per device• 16 pages of equations• Download 0.35µm libraries from web• Good for verification (and optimization?)• Bad for design


Device Variations• Run-to-run parameter variations:

– E.g. implant doses, layer thickness– Affect VTH, µ, Cox, R , …– How model in SPICE?

• Nominal / slow / fast parameters– E.g. fast: low VTH, high µ, high Cox, low R– Combine with supply extremes– Pessimistic but numerically tractable

improves chances for working Silicon


Square-Law Model• Large signal model

– Predicts device current as a function of terminal voltages

• Accurate for devices with– Long channel L > 5µm– Thick oxide tox > 50nm

• Qualitative correct predictions– Regions of operation

• Small signal parameters more important for analog design


Regions of Operation – Square Law Model

saturation

Linear / triode region

strong inversionweak inversionTHGS VV <

( ) DSV

THGSLW

oxD VVVCI DS2−−= µ

THGS VV ≥

THGSDS VVV −<

THGSDS VVV −≥ ( )221

THGSLW

oxD VVCI −= µ

( )43421tDS

tVDSV

tnVGSV

VVLW

SD eeII>>≈

−

−=for 1

0 1

CTqTkV oB

t 17at mV25 =≈=

region on transitimV100≈


Subthreshold Conduction(weak inversion)

• Like BJT• n > 1: base controlled by capacitive divider

– 0.35µm CMOS: n = 1.5• “slow”:

– “large” CGS for “little” current drive (see later)• Increasingly common:

– Low power– Submicron L means “high speed” even in weak inversion

• Poor matching:– VTH mismatch amplified exponentially– Avoid in mirrors, low-offset differential pairs


“Short Channel” Effects• VTH decreases for small L

– Large offset for diff pairs with small L

• Mobility reduction:– Velocity saturation– Vertical field (small tox=6.5nm)

Reduced ID, gm increase slower than rt-ID


Threshold Voltage VTH

• Strong function of L• Use long channel for

VTH matching

• Process variations– Run-to-run– How characterize?– Slow/nominal/fast– Both worst-case &

optimistic


VTH Design Considerations• Approximate Values (L = 0.5µm)

VTHN = 600mV γn=0.5 rt-VVTHP = -700mV γp=0.4 rt-V

• Back-Gate Bias

e.g. VSB = 400mV ∆VTHN = 110mV

• Variations:– Run-to-run: +/- 50mV (very process dependent)– Device-to-device: σ = 2mV (L > 1µm, common-centroid)– Use insensitive designs

• diff pairs, current mirrors• value of VTH unimportant (if < VDD)

[ ] VVVV sSBsTHTH 6.0 s0 ≈ΦΦ−+Φ+= γ


Device Parameters for Analog Design

• Region: strong inversion / saturation– Most common region of operation in analog circuits– XTR behaves like transconductor: voltage controlled current

source• Key design parameters

– Large signal• Current ID power dissipation• Minimum VDS available signal swing

– Small signal• Transconductance gm speed / voltage gain• Capacitances CGS, CGD, … speed• Output impedance ro voltage gain


Small-Signal DC Model• gm ID(VGS)• ro ID(VDS)• Low frequency small-signal model …


Transconductance

• Square-law model, saturation

( )

( )

THGS

D

DDLW

ox

THGSLW

ox

SBGS

Dm

THGSLW

oxD

VVI

IIC

VVC

constVdVdIg

VVCI

−=

∝=

−=

==

−≈

22

. assume

221

µ

µ

µ

Dt

D

t

LW

S

GS

Dm

LW

SD

InVInVeI

dVdIg

eII

tnVGSV

tnVGSV

∝=

=

=

≈

0

0

Weak inversion Strong inversion


Transconductance

weakinversion

strong inversion

velocity saturation


µCox

• Square law:

• Extracted values strong function of ID

– Low IDweak inversion

– Large IDmobility reduction

• Do not use µCox for design!

LWI

gCD

mox

2

2

=µ


Efficiency gm/ID• High efficiency is good

for low power

• Higher gm/ID at low VGS

• Approaches BJT for VGS < VTH

gm/IC = 1/Vt ~ 40 V-1

• NMOS / PMOS about same


Efficiency gm/ID• Important design parameter … but a little unusual: units 1/V

• Let’s define

• Square-law devices V* = VGS-VTH = Vdsat

e.g. V* = 200mV gm/ID = 10 V-1

*22 :law SquareVI

VVIg D

THGS

Dm =

−=

*2 2*VI

ggIV

D

m

m

D =⇔=


Small-Signal AC Model

rogmvgs

Drain

Source

Bulk = Substrate

Gate


PMOS Small-Signal AC Model

rogmvgs

Drain

Source

Bulk

Gate

Substrate


Small Signal Capacitances

CjDBCjDB + CCB/2CjDBCDB

CjsB + 2/3 CCBCjsB + CCB/2CjSBCSB

00CGC // CCBCGB

ColCGC/2 + ColColCGD

2/3 CGC + ColCGC/2 + ColColCGS

Strong inversionsaturation

Strong inversionlinear

Weak inversion

WLx

C

WLCC

d

SiCB

oxGC

ε=

=

mfF/ 48.0mfF/ 24.0

mfF/ 3.5 2

µµ

µ

===

olP

olN

ox

CCC


MOS Capacitance Example

fF24fF265µmfF3.5

5.0100

22

==

==

==

=

WCCWLCCt

C

LW

olNol

oxgc

ox

SiOoox

εε

fF157fF157

:triode

21

21

=+=

=+=

olgcgd

olgcgs

CCCCCC

fF24fF24

:ldsubthresho

==

==

olgd

olgs

CCCC

fF24fF201

:saturation

32

==

=+=

olgd

olgcgs

CCCCC


SPICE Simulation (W/L = 100/0.5)

• Transition from saturation to linear region is gradual

• Good agreement with hand analysis in strong inversion & saturation (“forward active”)


Layout

HSPICE geo = 0 (default)

HSPICE geo = 3


Extrinsic MOS Capacitances• Source/drain diffusion junction capacitance:

• Example: W/L = 100/0.5, VSB = VDB = 0V, Ldiff = 1µm

( ) ( )

bisube

Sij

j

Sibc

m

b

jswjswm

b

jj

Nqx

xC

VV

CVC

VV

CVC

Φ==

+

≅

+

≅

00

0

00

00

2 with

1

and

1

εεεε39.0

V51.0µmfF49.0

µmfF85.0

20

20

==

=

=

n

bn

jswn

jn

mV

C

C

48.0V93.0µmfF48.0

µmfF1.1

20

20

==

=

=

n

bn

jswn

jn

mV

C

C

AS = AD = 100µm2, PS = PD = 102µmCjn = 85fF Cjswn = 50fF Cbc = 58fF

Strong Inversion –Saturation: Csb = 173fF Cdb = 135fFLinear region: Csb = 164fF Cdb = 164fF


Summary NMOS 100/0.5 CapsHand calculation

135164135CDB

173164135CSB

0048CGB

2415724CGD

20115724CGS

Strong inversionsaturation

Strong inversionlinear

Weak inversion


SPICE Charge Model• Charge conservation

• MOSFET:– 4 terminals: S, G, D, B– 4 charges: QS + QG + QD + QB = 0 (3 free variables)– 3 independent voltages: VGS, VDS, VSB

– 9 derivatives: Cij = dQi / dVj, e.g. CG,GS ~ CGS

– Cij != Cji

Ref: HSPICE manual, “Introduction to Transcapacitance”, pp. 15:42, Metasoft, 1996.


High Frequency Figures of Merit

• Unity current-gain bandwidth

• Unity power-gain bandwidth

Ref: T. Lee, “The design of CMOS radio-frequency integrated circuits,” Cambridge, 1998, pp. 70.

gdg

T

Crωω

21

max ≈

model)law -(square 2dsat

LV

CCg

gdgs

mT

µ

ω

≈

+=


Efficiency gm/ID versus fT

Speed-Efficiency Tradeoff

NMOS faster than PMOS


Device Scaling

0

10

20

30

40

50

60

-0.1 0.0 0.1 0.2 0.3 0.4 0.5VGS-VTH [V]

f T [G

Hz]

0.18µm

0.25µm

0.35µm

0.5µm

Short channel devices are significantly faster!


Device Figure-of-Merit

Peak performance for low VGS-VTH (V*)

0

50

100

150

200

250

300

350

400

-0.1 0.0 0.1 0.2 0.3 0.4 0.5

VGS-VTH [V]

f T⋅g

m/I D

[GH

z/V]

0.18µm

0.25µm

0.35µm

0.5µm


Output Resistance ro

Hopeless to model this with a simple equation(e.g. gds = λ ID)


Process Variations for ro

L = 0.35µm


Open-loop Gain av0

More useful than ro


Gain, av0 = gm ro (gm/ID = 10/V)

• Strong tradeoff:av0 versus VDS range

• Create such plots for several device length’for design reference

L = 0.35µm


Gain, av0 = gm ro (gm/ID = 10/V)L = 0. 5µm

L av0

like long channel device


Technology Trend

0

10

20

30

40

50

60

70

80

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

VDS [V]

g m⋅r o

0.18µm

0.25µm

0.35µm

0.5µm

Short channel devices suffer from reduced per transistor gain


Transistor Gain Detail

For practical VDS the effect the “short-channel” gain penalty is less severe(remember: worst case VDS is what matters!)

0

5

10

15

20

25

30

35

40

45

0.0 0.1 0.2 0.3 0.4

VDS [V]

gm⋅r

o

0.18µm

0.25µm

0.35µm

0.5µm


Saturation Voltage versus V*• Saturation voltage

– Minimum VDS for “high” output resistance– Poorly defined: transition is smooth in practical devices

• “Long channel” (square law) devices:– VGS – VTH = Vdsat = Vov = V*– Significance:

• Channel pinch-off• ID ~ V*2

• Boundary between triode and saturation• ro “large” for VDS > V*• CGS, CGD change• V* = 2 ID / gm

• “Short channel” devices:– All interpretations of V* are approximations– Except V* = 2 ID / gm (but V* ≠ Vdsat)


Design ExampleExample: Common-source amp av0 > 100, fu = 100MHz for CL = 5pF

• av0 > 100 L =0.5µm

•

• High fT (small CGS): V* = 250mV

•

mS14.32 =≈ Lum Cfg π

µA3932

*==

VgI mD

M138 / 0.5 Vgs

dc = 820mVac = 1V

I1dc = 393uA

Vi

Vo

DC Analysis

sweep from 800m to 900m (1001 steps)Device Vgs

DC1

AC Analysislog sweep from 1k to 10G (101 steps)

AC1

C15pF


Device Sizing• Pick L 0.5µm• Pick V* 250mV• Determine gm 3.14mS

• ID = 0.5 gm V* 393µA

• W from graph (generate with SPICE)

W = 10µm (393µA /103µA)= 38µm

• Create such graphs for several device length’ for design reference

NMOSW / L = 10 / 0.5


Common Source Example

Dead on!


Small Signal Design Summary• Determine gm (from design objectives)

• Pick L– Short channel high fT– Long channel high ro, av0

• Pick V* = 2ID/gm– Small V* large signal swing– High V* high fT– Since V* is approximately the saturation voltage– Also affects noise (see later)

• Determine ID (from gm and V*)

• Determine W (SPICE / plot)

• Accurate for short channel devices key for design


Device Sizing ChartW = 10µm for all devicesVDS = VGS VSB = 0V


Device Sizing Chart

W = 10µm for all devicesVDS = VGS VSB = 0V

EECS 240 Lecture 4: Noise © 2004 B. Boser 1

Electronic Noise• Why is this important?

• Signal-to-noise ratio– Signal Power Psig ~ (VDD)2

– Noise Power Pnoise ~ kBT/C– SNR = Psig / Pnoise

• Technology Scaling– VDD goes down SNR down– Or C up Power up

• Low Power means understanding noise


Outline• Noise phenomena

– Random– Well-defined statistics– Statistics sufficient for design

• Device noise models• Representation of noise (2-ports):

– Motivation– Output spectral density– Input equivalent spectral density– Noise figure– Sampling noise (“kT/C noise”)

• SNR versus Bits• Noise versus Power Dissipation

– Dynamic range– Minimum detectable signal


Types of “Noise”• Interference

– Signal coupling (capacitive, inductive, …)– Supply noise– …

Use shielding, PSRR, etc …

• Device noise– Caused by discreteness of charge– “fundamental” – thermal noise– “manufacturing process related” – flicker noise


Thermal Noise of a Resistor• Origin: Brownian Motion

– Thermally agitated particles– E.g. ink in water, electrons in a conductor

• Random use statistics to describe

• Available noise power:

– Noise power in bandwidth B delivered to a matched load– Example: B = 1Hz PN = 4 x 10-21W = 174 dBm– Reference: T. Lee, “The design of CMOS Radio-Frequency

Integrated Circuits,” Cambridge University Press, 1998, pp. 244.

TBkP BN =


Resistor Noise ModelR

Rvn

Noisy resistormodel

PN

RvTBkP n

BN 4

2

==

TRBkv Bn 42 =

Mean square noise voltage:


Thermal Noise• Dissipative elements (resistors)• Random fluctuations of v(t) or i(t)• Independent of current flow

• Characterization:– Zero mean– Gaussian distribution (pdf)– Power spectral density (“white” up to about 80THz)– kBT = 4 x 10-21 J (T = 290K = 16.9oC)

• Example:R = 1kΩ, B = 1MHz 4µV rms or 4nA rms or 4nV/rt-Hz

RTBki

TRBkv

Bn

Bn

44

2

2

=

=


Noise of Passive Networks• Capacitors, Inductors

• Noise calculations– Instantaneous voltages add– Power spectral densities add– RMS voltages do NOT add

• Example: R1+R2 in series

• Generalization to arbitrary RLC networks


Noise in Diodes• Shot noise

– Zero mean– Gaussian pdf– Power spectral density– Proportional to current– Independent of temperature

• Example: ID = 1mA, B = 1MHz 17nA rms

• Shot noise versus thermal noise (rd = Vt/ID)Thermal equilibrium

BqIi Dn 22 =


MOS Noise Model• Thermal noise (strong inversion)

– Drain currentγ = 2/3 for small fields (long L)can be 2 … 3 or even larger for NMOS

– Gate current– No noise from ro

– Extrinsic noise sources

• Flicker noise– Kf,NMOS = 2.0 x 10-29 AF

Kf,PMOS = 3.5 x 10-30 AF– Strongly process dependent (also model)

– Example: ID = 10µA, L = 1µm, Cox = 5.3fF/µm2, fhi = 1MHz

flo = 1Hz 722pA rmsflo = 1/year 1082pA rms

fgggTki dsmbmBd ∆++= )(42 γ

lo

hi22

21/f,Total

221/f

ln

)(

hi

loff

CLIK

fdf

CLIK

i

ff

CLIK

fi

ox

Dff

f ox

Df

ox

Df

==

∆=

∫


BJT Noise

fqIi

ffIKfqIi

fTrkv

Cc

BBb

bBb

∆=

∆+∆=

∆=

2

2

4

2

12

2

α


1/f Noise Corner Frequency• Definition (MOS)

• Example:– V* = 200mV, γ = 1

NMOS PMOSL = 0.35µm 192kHz 34kHzL = 1.00µm 24kHz 4kHz

2

*

2

2

2

8

114

41

4

LV

CTkK

LCTkK

gTkCLIK

f

fgTkff

CLIK

oxrB

f

Ig

oxrB

f

mrBox

Dfco

mrBcoox

Df

Dm

γ

γ

γ

γ

=

=

=

∆=∆


SPICE Noise Analysis

Slope …


Noise Calculations

• Output spectral noise density• Method:

1) Small-signal model2) All inputs = 0 (linear superposition)3) Pick output vo or io4) For each noise source vx, ix

Calculate Hx(s) = vo(s) / vx(s) (… io, ix)5) Total noise at output is

• Tedious but simple …

( ) ( )∑ ==

xxjfsxTon fvsHfv 22

22

, )(π

( ) ( )fSfv nTon =2, :notationsimpler


Example 1: Common Source


Simulation Result


Representation of Noise in 2-Ports

• Output spectral density• Input equivalent spectral density• Signal-to-noise ratio• Noise figure• Sampling noise (“kT/C noise”)


Input Equivalent Noise

• Two-port representation• Fictitious noise sources• Effect of source resistance• Correlation• Minimum detectable signal• Bandwidth


Simulation Result(same circuit as previous example)


Example 2: Input Referred Noise


Simulation Result


Effect of Rs

• Input referred noise depends on Rs

• Solution: voltage and current noise source• Beware: correlation


Minimum Detectable Signal

• Bandwidth• Noise power = signal power


Sampling Noise

• “kT/C” noise• Application: ADC, SC circuits, …• Aliasing• Variance of noise sample• Spectral density of sampled noise


Example 3: MOS S&H• Sampling noise:

• Noise bandwidth:

( )

( )

CTk

dffvv

sRCTRkfv

B

onoT

Bon

=

=

+=

∫∞

0

22

22

114

RCff

RCB

CTkTRBk

oo

BB

ππ

21 ith w

241

4

===

=


SPICE Verification


Useful Integrals

41

41

1

411

2

02

2

2

02

2

2

0

Qdfs

Qs

s

Qdfs

Qs

df

o

oo

o

o

oo

oso

ω

ωω

ω

ω

ωω

ω

ω

=++

=++

=+

∫

∫

∫

∞

∞

∞


Example 4: CS Amplifier( )

FL

B

voL

B

LmL

B

LLLm

LB

LLLm

LBoT

LL

Lm

LBon

nCTk

ACTk

RgCTk

CRRg

RTk

dfCsR

RgR

Tkv

CsRRg

RTkfv

=

+=

+=

+=

+

+=

+

+=

∫∞

321

321

41

3214

11

3214

13214

2

0

222

22


SPICE Circuit

rms 98164

1

221100

10

34

322

1

VV

ACTkv

AkRmSg

AI

VIg

voL

BoT

vo

L

m

D

D

m

µ

µ

µ

=

+×=

+=

−=Ω=

==

= −


SPICE Result


SC Resistor Noise Spectrum

Sy(f)

C

Rsw

4kBTRsw

fs

( )

CTkdffS

fT

CRTa

fTee

fCTkfS

rBy

ssw

a

a

s

rBy

sf

∫ =

===

−+−

= −

−

2

0

2

2

)(

1 and T

2cos1112)(

τ

π0 0.1 0.2 0.3 0.4 0.5

-4

-3

-2

-1

0

1

2

3

4

Normalized Frequency f/fs

Nor

mal

ized

Noi

se D

ensi

ty S

(f)/(

2kT/

C)

T/τ = 1T/τ = 3

• Noise essentially white for T/τ > 3• Settling constraints ensure that this condition

is usually met in practice• Note: This is the noise density of an SC

resistor only. The noise density from an SC filter is usually not white.


Periodic Noise Analysis

PSS pss period=100n maxacfreq=1.5G errpreset=conservativePNOISE ( Vrc_hold 0 ) pnoise start=0 stop=20M lin=500 maxsideband=10

ZOH1T = 100ns

ZOH1T = 100ns

S1R100kOhm

R100kOhm

C1pFC1pF

PNOISE Analysissweep from 0 to 20.01M (1037 steps)

PNOISE1

Netlistahdl_include "zoh.def"ahdl_include "zoh.def"

Vclk100ns

Vrc Vrc_hold

Sampling Noise from SC S/H

C11pFC11pFC11pFC11pF

R1100kOhm

R1100kOhm

R1100kOhm

R1100kOhm

Voltage NOISEVNOISE1

NetlistsimOptions options reltol=10u vabstol=1n iabstol=1psimOptions options reltol=10u vabstol=1n iabstol=1psimOptions options reltol=10u vabstol=1n iabstol=1psimOptions options reltol=10u vabstol=1n iabstol=1p

SpectreRF PNOISE: checknoisetype=timedomainnoisetimepoints=[…]

as alternative to ZOH.noiseskipcount=large

might speed up things in this case.


Sampled Noise Spectrum

Density of sampled noise with sinc distortion.

Normalized density of sampled noise, corrected for sinc distortion.


Total NoiseSampled noise in 0 … fs/2: 62.2µV rms

(expect 64µV for 1pF)


Signal-To-Noise Ratio• SNR

• Signal Powersinusoidal source

• Noise Powerassuming thermal noise dominates

• SNR = f(C)

noise

sig

PP

SNR =

221

peakzerosig VP −=

fB

noise nCTkP =

25.0 VPsig =

( )264 VPnoise µ=

( )dBSNR 9.8010122

645.0 6

2 =×==µ

4 ×↑C dBSNR 6 +↑


dB versus Bits• Quantization “noise”

– Quantizer step size:– Box-car pdf– Variance:

• SNR of N-Bit sinusoidal signal– Signal power

– SNR

– 6.02 dB per Bit

12

2∆=QS

∆

2

22

21

∆

= NsigP

[ ] dB 02.676.1

25.1 2

NSP

SNR N

Q

sig

+=

×==

146249816508dBN


SNR versus Power• 1 Bit 6dB 4x SNR• 4x SNR 4x C• Circuit bandwidth ~gm/C 4x gm• Keeping V* constant 4x ID, 4x W

• Thermal noise limited circuit:Each additional Bit QUADRUPLES power dissipation.E.g. 15 Bit noise-limited ADC dissipates 100mW

16 Bit redesign dissipates 400mW !

• Overdesign is very costly. We need design procedures that get us very close to the specifications.


Analog Circuit Dynamic Range• The biggest signal we can ever expect at the output of a circuit

is limited by the supply voltage, VDD. Hence (for sinusoids)

• The noise is

• So the dynamic range in dB is:

221)(max

DDVrmsV =

CTknrmsV B

fn =)(

[pF] in C with[dB] 7520log

[V/V] 8)(

)(

10

max

+

=

==

fDD

Bf

DD

n

nCV

TknCV

rmsVrmsVDR


Analog Circuit Dynamic Range

• For integrated circuits built in modern CMOS processes, VDD < 3V and C < 1nF (nf = 1)

– DR < 110dB (18 Bits)

• For PC board circuits built with “old-fashioned” 30V opamps and discrete capacitors of < 100nF

– DR < 140dB (23 Bits)– A 30dB (5 Bit) advantage!

• Note: oversampling ADCs break this barrier (cost: speed penalty)


Noise and Feedback• Ideal feedback:

– No increase of input referred noise– No decrease of SNR at output

• Practical feedback: increased noise– Noise from feedback network– Noise gain from elements outside feedback loop

• System level: feedback can mitigate noise problems– E.g. under-damped accelerometer

Ref: M. Lemkin and B. E. Boser, “A Three-Axis Micromachined Accelerometer with a CMOS Position-Sense Interface and Digital Offset-Trim Electronics,” IEEE J. Solid-State Circuits, vol. SC-34, pp. 456-468, April 1999.


Ideal Feedback

Order of summation irrelevant:

Circuits are identical

Σ -a

f

Vi Vo

vn

Σ -a

f

Vi Vo

vn


Noise from Feedback NetworkExample:

• Decreasing Ro reduces noise but increases feedback current

• High closed-loop gain Av0results in increased noise from feedback network

a = inf

R1

R2

in1

in2

vn

ViVo

vx = vi - vn

( )

( )( )

444 3444 212

0

202

2

21

2122

21

22

1212

1

212

1

14

1

nfbv

v

voBn

nnnieq

nnx

xnnx

o

AAfTRkv

RRRRiivv

RiiRRv

viiRvRv

−∆+=

+

++=

−−

+=

+

+−=

( )

22

0

2

01

HznV114

10100kΩ

1

=

∆

===

−=

fv

ARRARR

nfb

v

o

vo


Inverting Amplifier

inf

R2

inVois

Feedback has no impact on noise!

Noise from R2 ignored.

( )22

2

nieq

nso

ii

Riiv

=

+=


Inverting Amplifier

inf

R2

R1vn

ViVo

2

0

2

2

2

212

2

2

1

1

2122

1

21

1

2

11

0

+=

+=

+=

++−=

−

vn

n

nieq

n

A

io

Av

RRRv

RR

RRRvv

RRRv

RRvv

v

Example:

11 :1.0

1.1 :10

2 :1

2

2

0

2

2

0

2

2

0

=−=

=−=

=−=

n

ieqv

n

ieqv

n

ieqv

v

vA

v

vA

v

vA

Noise from R1, R2 ignored.

Note: R1 is outside feedback loop signal and noise have different gains to output.

22nieq vv ≠


“Big” Noise Example

• Cascoded common-source stage: what are the noise contributions from M1, M2?

• Simplified model for conclusive results:

– Lump parasitic capacitors– Feedback sets gain,

neglect ro

M1

M2

Cx CL

Vo

Vx

VBias

Vi

VG

CP

CF

CS


Example (cont.)

M1

M2

Cx CL

Vo

Vx

VBias

Vi

VG

CP

CF

CS

( )

PSF

F

ogg

nnxmgmxxx

nxmgFoFLo

CCCCF

FvvviivgvgvsCv

ivgvsCvCCsv

++=

=

=−+++

=+−−+

with

:0 :

0 :

2121

22

Calculate noise transfer functions to amplifier output:


Example (cont.)

M1

M2

Cx CL

Vo

Vx

VBias

Vi

VG

CP

CF

CS

( )

x

mp

FL

m

Leff

mu

uo

puo

oo

pnn

mo

Cg

FCCgF

CgF

Q

sQs

siiFg

v

2

11

2

2

2211

1

with

1

11

=

−+==

=

=

++

+=

ω

ω

ωω

ωωω

ωωω

After some algebra …


Example (cont.)

M1

M2

Cx CL

Vo

Vx

VBias

Vi

VG

CP

CF

CS

2

2

2

2

2

1

2

112

2

1

114

ooM

pm

m

Mm

bon

sQs

sgg

gFTk

fv

ωωω ++

+=∆

43421

Spectral noise density at amplifier output:

• Noise from M2:• Circular current at low frequency does

not reach amplifier output• At high frequency Cx short

• Cascode contribute little noise at low frequency

• At high frequency the noise contribution can be significant


Example (cont.)

M1

M2

Cx CL

Vo

Vx

VBias

Vi

VG

CP

CF

CS

( )

+=

+=

+=

++

+=∆

=

=

∞∞

∫∫

2

1

1

2

2

1

2

12

2

22

2

2

2

21

2

1012

0

2

1

1

14

4

1

114

M

Leff

x

MLeff

b

p

u

m

m

Leff

b

p

o

m

mo

m

b

jfsooM

jfspm

m

Mm

bon

CC

FCTk

gg

FCTk

ggQ

gFTk

sQs

sggdf

gFTkdf

ffv

γ

ωωγ

ωωωγ

ωωω

γ

π

π4434421

Total noise at amplifier output:

• Total noise depends only on C!• M1 always contributes noise• Significant noise from M2 for “large” Cx

make Cx small (compared to CLeff)


Design Example• Track & Hold amplifier for 16-Bit ADC (B=16)• fs = 100MHz ωu ~ 2π fsN

N = B x ln(2) … based on settling, see later• Amplifier based on cascoded common-source, Av = -1• Choose

– L = 0.35µm– M1 and M2 same size (not necessarily ideal)– CF = CS = CGS (reasonable tradeoff)

F = 1/3– Maximum signal amplitude Vs (peak-to-peak)


Design Equations( )

( )

1

32

1

B

2

2

2*

2lnN 2

1

221

2

m

D

oxGS

Leff

m

su

Leff

GSx

Leff

s

B

gIV

WLCCCgNf

CCC

FCkT

V

DR

=

=

=

≅=

≈+

=

=

πωsolve

( )s

s

Bsm

s

rBB

L

fVTk

FBg

VTk

FC

π22ln8

28

2

2

2

≅

×≅


Design Examples

13.4pF0.84pFCGS

10800µm675µmW167mA10mAID

1300mS81mSgm

413pF26pFCL

0.1µm/µA0.1µm/µAW/ID

200mV200mVV*1V1VVs

100MHz100MHzfs

1614B16-Bit T&H14-Bit T&HParameter

EECS 240 Lecture 5: Biasing © 2004 B. Boser 1

Bias Current Sources• Applications• Design objectives

– Output resistance (& capacitance)– Voltage range (Vmin)– Accuracy– Noise

• Cascoding• High-Swing Biasing


Current Mirror• Bias• Noise• Cascoding


Noise

• M2 (and Iref!) can add noise– Choose small M (power penalty), or– Filter at gate of M1

• Current source FOMs– Output resistance Ro– Noise resistance RN– Active sources boost Ro, not RN

( )( )

oov

o

mN

NB

mB

mmB

ddon

rRMa

r

MgR

fR

Tk

fMgTkfgMgTk

iMii

=<<+

=

+=

∆=

∆+=∆+=

+=

−

−

1

11

14

144

1

0

1

1

1

22

1

22

221

2

γ

γ

γγ


Vmin versus Noise

MKIV

MgR

kVkV

D

mN

+=

+=

=×=

−

−

12

11

2...1 typ.*

1min

1

1

min

γ

γ

• Voltage required for large Ro (saturation): Vmin ~ V* (based on intuition from square-law model)

• Minimizing noise (for given ID):large RNlarge Vmin (k >> 1)

• At odds with signal swing(to maximize the dynamic range)


Bipolar’s, GaAs, …

• BJT and RE contribute noise• Increasing RE lowers overall noise• BJT and MOS exhibit essentially

same noise / Vmin tradeoff• Lowest possible noise source is a

resistor (and large Vmin, VDD)

Q1Q2

RERE

io

Iref

Cbig

fRgRgi

Rgii

Em

EmRn

Emcnon ∆

++

+=

44344214434421ER

22

BJT

222

111

0 a) =EmRg

1 b) >>EmRg

fTgki mBon ∆= 22

fR

TkiE

Bon ∆=142

CC

t

mN I

IV

gR by set 22

==

min

minmin

VVV

IVRR

satce

CEN

−==

KIVRD

MOSN 2 compare

1min

,

−

=γ

( )02 =bi


Cascoding


Output Resistance


Bias

V* = 196.9mV

Vds1 = 616mV

Vgs2 = 884mV


Rout = f(k)

*11 kVVDS =

How choose k? Issues:

• Swing versus Ro• Large k useful only for large

Vmin simultaneously• Note: small or no penalty for

large k and small Vmin• typically choose k>1


High-Swing Cascode Biasing• Need circuit for generating Vbias2

• Goal: Set Vbias such that VDS1 ≈ kV*– k > 1 (typical: 1 … 2)– Important for high Rout

– No penalty for moderate Rout

• Design for insensitivity to – Process variations (µ, Cox, VTH, γ, …)– Reference current Iref


High-Swing Bias 1• M4 quarter size or less

– M=1/5 for high Rout– Note: M ≠ k

• M5 sets VDS3 = VDS1:improves matching

• Sensitive to body-effect

• Lcurrent-source = Lcascode

• Simple


Rout


High-Swing Bias 2• M5 … M10 replace

quarter size device

• All devices same size

• Less sensitive to body-effect



High-Swing Bias 3• M5 in triode & smaller

• All other devices same size

• Sensitive to body-effect



Device SizingExamples:

m5 = 1/3, ∆VTH=0VR = 1

m5 = 1/4, ∆VTH=0VR = 1.55

( )( )

( ) ( )

( )

( )555

555

5

215

21556

56552

6

16666

565

65

2662

16

525555

1DS5

111

11

:solve22

substitute with

with

:law-SquareV

:bjective O

DS

TH

DS

TH

DS

VV

mm

VV

mmDSsatd

DSTHsatdDS

satd

satd

satd

satdTHGS

DSGSGS

DD

THGSLW

oxD

DSV

THGSLW

oxD

satd

mR

VmV

VVVVmV

VVVVV

VVVII

VVCI

VVVmCI

VR

∆

∆

+++=

+++=

∆++=

=+=

+==

−=

−−=

×=

µ

µ


Different Device Length

M110 / 1

M2

10 / 0.35

M310 / 1

M410 / 0.35

M610 / 0.35

dc = 30uA

I1

dc = 30uAI2

V1

DC Analysis

sweep from 0 to 3 (51 steps)Device V1

DC1High Swing Cascode Bias 3: Current Source and Cascode have different Channel Length

3 V 3 V

M=250m10 / 1M7

M8

10 / 1

I3dc = 30uA

3 V

Vout

VSS

Vss

Vds1


High-Swing Bias 4

• M6 in triode• Insensitive to body effect• Current source and cascode device length may differ• Need 3 reference sources (increased power dissipation)• Large device ratios

( ) ( )( ) ( )

[ ] ( )( )

( )( )

satd

satdDS

satd

satd

satdDS

DSDSsatdL

WoxD

satdL

WoxD

VVV

mLWVVLW

LWLWmmVV

VVVCI

VCI

176

6

177

6

776

6621

766

2772

17

2.13.0then

5.0 1/8 4 for 16/1

:e.g.

with11

:solve

==

==

==

=−−=

−=

=

µ

µ


Gain Boosting• Use feedback to further increase Rout

– No increase of Vmin(unlike double cascode)

• Local feedback potential instability

• Beware of doublets (slow settling)

• Noise enhancement


Gain Boosting Analysis

Note: C2 would not be present in an actual circuit (or smaller). It is added here to separate pole frequencies.


Zout

• Ztotal = Zboost // ZCL

• Doublets slow settling

• Booster bandwidth tradeoff:

- push doubled above closed-loop bandwidth

- ensure stability (nondominantpole at source of M2)


Noise Analysis


Noise Summary


Noise Detail

Booster amplifier and cascode contribute noise at high frequency.

Actual boosters have more transistors additional noise.

Some noise might be filtered out by sampling switch.


Cascode Noise

Noise from cascode often insignificant.

Can contribute substantially at high frequency with lots of (capacitive) degeneration at the source of the cascode transistor (poor layout).


Matching

• Systematic mismatch– ∆VDS– source resistance– gradients

• Random mismatch– ∆ (W/L)– ∆VTH


Random Mismatch• Model:

(we need an equationwith W/L in it … resort to square-law)

• Mismatch: ∆ID, ∆(W/L), ∆VTH

• Substitute:

• choose large VGS-VTH (V*)

( )

( )222

21

2

21

121

1

THGSoxD

THGSoxD

VVLWCI

VVLWCI

−

=

−

=

µ

µ

21

21

21

THTHTH

DDD

VVV

LW

LW

LW

III

−=∆

−

=

∆

−=∆ ( )

( )21

21

21

5.0

5.0

5.0

THTHTH

DDD

VVV

LW

LW

LW

III

+=

+

=

+=

THGS

TH

D

D

VVV

LWLW

II

−∆

−

∆

=∆ 2


Mismatch Example

( )

( ) ( )

( )2

62

2

2

222

%4.1

10100100300

3201.0

4

mV300

mV3

%1

=

×+=

×

+=

−+=

=−

=

=

−

∆

∆

∆

∆

∆

THGS

V

LW

LW

II

THGS

V

LW

LW

VV

VV

TH

D

D

TH

σσσ

σ

σ• Represent mismatch as

random quantities

• Variances (squares!) add … like noise

• Use large V* (or degeneration) for good current mirror matching


Yield• Yield = fraction of good dies

• E.g. need ±2.8% matchingσ = 1.4%, k = 2.8 / 1.4 = 2

yield = 0.954 = 95.4%

• Typical design goal:± 3σ (“6σ”), i.e. k=3

0.9973.0

0.9952.8

0.9912.6

0.9842.4

0.9722.2

0.9542.0

0.9281.8

0.8901.6

0.8381.4

0.7661.2

0.6831.0

0.5760.8

0.4510.6

0.3110.4

0.1590.2

Yieldk

EECS 240 Lecture 6: References © 2003 B. Boser 1

Outline

• Objectives• CMOS implementations• Startup circuits• Typical performance• Constant XXX references


References• Applications

– Bias current– ADC / DAC references

• Solutions– Voltage references:

• PTAT (Vt = kT/q)• Bandgap• Threshold voltage, VTH,

∆VTH

– Special purpose:• Constant gm

– No “direct” current reference

• Specifications– Accuracy: σ of ∆Vout/Vout– Temperature coefficient, TCF– Power rejection ratio, PSRR– Trimming– Supply voltage– Power dissipation


Widlar Reference

0 200 400 600 800 1000 1200 1400 1600 1800 20000

0.5

1

1.5

2

2.5

3

3.53.2

0.05

I C2

1.926 103×0.055 I ref I C2( )

Q1

Q2

R110kOhm

VoutIref

3 V

DC Analysis

sweep from 0 to 300u (200 steps)Device Iref

DC1

212

2

1

2121

lnln Cs

Ct

s

reft

CBEBE

IRIIV

II

V

IRVV

+

=

+=

• IC2 is “relatively” insensitive to Iref• first order supply independence


PTAT Reference

Issues:• Cascoding• Self-biasing• Temperature Coefficient• Vertical BJT• Startup

TIIMV

II

IIVV

C

Ct

C

C

s

stBE

∝

=

=∆

2

1

2

1

1

2

ln

ln

Q1

Q1

Q1

Q1

Q2Q2Q2Q2M = 8

R110kOhmR110kOhmR110kOhmR110kOhm

M110 / 1

M210 / 1

VDD

DC Analysis

sweep from 10m to 3 (199 steps)Device VDD

DC1

delta_Vbe

VSS


Temperature Coefficient

resistordiffusionnfor ppm/K 1800ppm/K1500ppm/K3300

11

1

)K(300 re temperaturoomat ppm/K 3300

1

1

1

1

1

1

o

+=−=

−∆

∆=

=

∆=

≅

=

∆∆

=

∆∆

=

dTdR

RdTVd

V

dTdI

ITC

RVI

T

TV

V

dTVd

VTC

BE

BE

out

outF

BEout

BE

BE

BE

BEFTC of Reference Voltage:

TC of Reference Current:


CMOS PTAT Reference

p- substrate

n- well

p+ diffusion

n+ diffusion

C E B

Vertical PNPM4M3

M2M1

Q11

R

Q2n


Startup Circuit

M4M3

M2M1

Q11

R

Q2n

M9

M5

M7M8

M6

Widlar Source

Mirror

IQ1

IQ2

A

B

Parasitic operating point A:• Positive feedback unstable• Noise drives circuit away from A (and to B)• Problem: gain at A too small (IQ = 0)


Bandgap Reference• Supply and temperature insensitive• VBG,Si = 1.205V• Curvature correction

• References:– R. Widlar, JSSC 2/1971, pp. 2

first report– G. Nicollini, JSSC 1/1991, pp. 41

offset compensated amplifier– K. Tham, JSSC 5/1995, pp. 586

self-regulated supply for improved PSRR– A. Boni, JSSC 10/2002, pp. 1339

bandgap reference for VDD < VBG– P. Malcovati, JSSC 7/2001, pp. 1076

curvature corrected CMOS bandgap reference


Bandgap Performance

92µW1mW4.8mWPower dissipation

212ppm/V at DC80dB @ 10kHz40dB @ 500kHz

86dBPSRR7.5ppm/oC85ppm/oC15ppm/oCTCF

0.54V1.24V6.2VOutput voltage20mV24mVAccuracy (σ)

1V3V+/- 5VSupply

[Malcovati][Tham][Nicollini]


Constant gm Reference• Motivation:

L

mu C

g∝ω M4M3

M2M1

R

Rgm

11 =


Reference Distribution Network• Single shared reference

• Current distribution:– Many wires– Increase power dissipation

• Voltage distribution:– Susceptible to mismatch – use large VGS in distribution

network– Careful supply routing to avoid

poor PSRR– Avoid loops in analog supply

EECS 240 Lecture 7: OTA © 2003 B. Boser 1

Operational Transconductance Amplifiers

• OTA versus OpAmp, Applications• Differential versus Single-Ended Output• Characteristics

– Frequency response, settling time, stability– Open-loop gain– Noise, dynamic range– PSRR, CMRR– Common-mode feedback circuit

• Topologies– Single-stage (telescopic, folded cascode, …)– Multi-stage, Miller compensation– Class A, A/B

• Design


OpAmp versus OTAOpAmp

• Voltage source output (low impedance)

• Essential to drive resistive loads

• Essentially OTA + buffer• Buffer increases power

dissipation, noise

OTA

• Current source output (high impedance)

• Cannot drive resistive loads• Use capacitive (SC)

feedback• Transistors are

transconductors


Resistive FeedbackOpAmp

• Gain independent of feedback network

• Feedback network adds noise

OTA

• Resistive feedback network lowers loop gain

• Large feedback resistors?– Large area– Parasitic poles stability?

• Solution: capacitive feedback– Needs initialization– Needs clock

Linear, time-variant circuit

• kT/C noise


OpAmp versus OTA Noise

Opamp and switch noise add OTA contributes no excess noise(actual designs can increase noise)

+=

switch

noise2

R1 R

CkTvoT C

kTvoT =2

Rswitch

C

4kT / Gm 4kT Rswitch Rswitch

CC

Gm

Rswitch

CCCCCCCC

4kT (1/Gm + Rswitch)1/Gm + Rswitch

CCCCCCCCCCCCCCCC

1Gm


SC Gain Stage

• Phase 1:– sample Vi onto Cs: Qs = Vi * Cs– Null charge on Cf

• Phase 2:– Amplifier “moves” charge from Cs to

Cf: Qf = Qs = Vi * Cs– Vout = Qf / Cf = Vi * Cs / Cf

• Implement switches with MOSFETs• Drive with “2-phase non-overlapping

clock”• Gain set by capacitor ratio (precise)• Output valid only at end of phase 2

and during phase 1• Cannot drive resistive load

Cs

Cf

Ci


SC Gain Stage


SC Gain Stage


Noise

isf

ff

Lefff

f

s

f

fLff

sCon

fC

fs

C

CCCC

FnFC

kTnCC

CkT

nFC

kTCkT

CCvv

CkTv

nCkTv

s

F

s

++=+

+=

++

=

=

=

with1 1

1

C onto noise OTA and noise 1 Phase:2 Phase

:1 Phase

OTA

2

networkfeedback

1

amplifier this offactor noise

2

factor feedback OTA stage-singlefor

2

22

L

2

V drivingamplifier offactor noise

12

i

4342144 344 21


Differential Output“Fully differential amplifier”

• Differential versus common-mode signals

• Balun

• Common-mode feedback CMFB

( )

idici

idici

iiic

iiid

vvv

vvv

vvv

vvv

21

21

21

−=

+=

+=

−=

−

+

−+

−+


PSRR & CMRR• Any terminal is an input• Important “undesired”

inputs:– Supply– (Input) common-mode

• Figure-of-merit:– Desired gain over

undesired gain >> 1– E.g. PSRR, CMRR

∞→=

∞→=

∞→=

→=

→=

→=

→=

∞→=

VSS

dmVSS

VDD

dmVDD

cdm

dm

SS

odVSS

DD

odVDD

ic

odcdm

ic

occm

id

oddm

AAPSRR

AAPSRR

AACMRR

vvA

vvA

vvA

vvA

vvA

0

0

0

0


PSRR Example


PSRRFully differential circuit has excellent PSRR limited only by matching


Common-Source Stage

• Openloop gain, Avo, avo• Output range, ∆Vo• Bandwidth, fu, f3dB• Noise


Operation


Gain, Output Range

in

outvo

oinin

ooutoutvo

dVdVa

VVVV

A

=

−

−=

_

_

Note: plot is for Vout_o = 0V and Vin_o = 0V (unrealistic).


Frequency Response

MHzfFS

Cg

rgsCg

s

Csrrg

vv

rsCvgv

L

mu

omL

m

gC

rg

Lo

om

i

o

oLomi

m

L

om

6902100433

)negligible is r roughcurrent th (when

1for

11

10

o

1

×==

≈

>>−≈

+−=

+−=

++=

πµ

ω


Noise

Total noise is noise from M1multiplied by V1

*/V2*

V2* >> V1

* for low noise

Tradeoff with output range ∆Vout.

( )

43421fn

mB

m

m

mB

mmm

Bieq

VV

gTk

gg

gTk

ggg

Tkfv

+=

+=

+=∆

*2

*1

1

1

2

1

2121

2

114

114

14

γ

γ

γ

3.165.538.7

3.12551781

=

=+mVmV


Differential Input• Differential input:

eliminates systematic offset

• Tail current source:provides CMRR


Differential Pair – CMRR

M110.05 / 1

9.95 / 1M2

10.05 / 1M3

M49.95 / 1

dc = 50uAI1

I2

dc = 50uA

Supply

VDD = 3VVSS = 0V

VSS

Vi_diffac = 1V

Vi_cmxdc = 691mV

VDD

DC AnalysisDevice Vi_cm

sweep from -1m to 1m (51 steps)

DC_cm DC AnalysisDevice Vi_diff

DC_diff

sweep from -1 to 1 (51 steps)

20kOhm

R3R1

20kOhm

R2

20kOhm20kOhm

R4

M5

35.175 / 1

M6

34.825 / 1

R520kOhm 20kOhm

R6

Vi_cmzdc = 2V

Vi_cmac = 1V

Vi_cmydc = 1V

CMRR

Cwell100fF

R7

1MOhm

R81MOhm


Simulation ResultFor all cases:

gm = 290 µS

V* = 180 mV

Avo = 5.5


CMRR Analysis

• Ignoring ∆Gm, ∆ro(use superposition)

• E.g. 10/0.01 = 1000 = 60dB

• E.g. 2 x 1mS * 1MΩ / 0.01= 200,000 = 106dB

• E.g. 1/0.01 = 100 = 40dB

Tail / With Body EffectTail / No Body EffectNo tail current source

o

o

m

m

o

o

m

mom

omomcdm

omcm

omdm

RR

GGCMRR

RR

GGRG

RGRGARGARGA

∆+

∆=

∆+

∆=

∆+∆===

1

o

o

m

m

SSm

o

o

m

m

SS

ocdm

icsbSS

ocm

omdm

RR

GG

RGCMRR

RR

GG

RRA

vvRRA

RGA

∆+

∆=

∆+

∆=

≈≈

=

22

for 2

mb

mb

mb

m

mb

m

icsbombcdm

omdm

ggg

ggGCMRR

vvRgARGA

∆=

∆=

≈∆==

for


CMRR Summary

• Eliminates gmbmatching constraint

• CMRR limited by IDmodulation; cascode helps

• Cwell sets high frequency CMRR

• Cwell < CSB in some deep sub-micron processes (with high S/D doping)

• CMRR improved by …

• High frequency CMRR limited by capacitance at common-source node (CSB)

• CMRR limited by matching

• Bias current is a strong function of input common-mode

• Impractical in most situations

Well tied to sourceWith tail current sourceNo tail current source

EECS 240 Lecture 8: Folded Cascode B. Boser 1

Folded Cascode

• Good general purpose single-stage OTA• Analysis

– Bias– Gain– Input capacitance– Frequency response– Feedback, stability– Settling time– Noise– Common-Mode Feedback

• Design– Specifications– Circuit parameters


Schematic

Many more transistors, but overall characteristics very similar to common-source stage.


Bias Subcircuit

Vbias2

Vbias1

VDD

M=250m

M6100 / 1 100 / 1

M7

M8100 / 0.5

M9100 / 0.5 100 / 0.5

M10

dc = 200uAI1

dc = 200uAI2

dc = 200uA

I3

For device sizes on page 7.


DC Gain, Bias


Bias … Differential Inputs


Low Frequency Gain, Adm

• Gain / Output Range tradeoff– Adm=120 ∆Vod = 4.3V– Adm=200 ∆Vod = 3.6V

(nominal parameter)

• Increasing Adm:– Moderate:

• Increase L• Affects V*, phase margin

– Substantial:• Double Cascode• Gain boosting• Multi-stage amplifier


Increased Adm


Output Resistance

Beware of imbalance between NMOS and PMOS current source


Gm, Cod Test Circuit


Transconductance


Differential Output Capacitance


Differential Input Capacitance

CGS1

= 2/3 Cox W L = 117 fF

Miller effect significantly increases Cid at low frequency

Cascoding M1, M2 helps (at the expense of reduced input common-mode range)


Frequency Response (Adm)

• Bandwidth– Strong function of CL

– Increasing fu?

• Feedback– Stability– Phase margin– Increasing φm

– Increasing CLincreases φm in single-stage amplifier (costly)

φm

EECS 240 Lecture 9: Feedback B. Boser 1

Feedback• Benefits

– Reduced sensitivity to• Gain variations• Nonlinearity

– Increased bandwidth

• Caveat: potential instability

• Stability test– Bounded input, bounded output: no general test available– Linear system:

• Poles in LHP (“left half-plane”)• Nyquist criterion• Bode criterion

– Hand-analysis– SPICE


Generic Feedback Circuit

1 for 11

111

:gain loop-closed :gain loop :factorfeedback :gain loop-open

1

>>≈

+=

+=

=

=

Tf

f

TaVVA

faTfa

T

i

o

v

v


Electronic Feedback Circuit

f

TRR

RR

TRRR

RVVA

faT

RRRf

a

i

o

v

v

1

1 for

11

1

:gain loop-closed :gain loop

isolate) todifficult (sometimes

:factorfeedback

:gain loop-open

1

2

1

2

2

11

2

21

1

≠

>>−≈

+−=

=

=

+=


Stability Analysis

• Depends on T(s)– NOT a(s)

• Finding T(s):– Hand analysis:

• Break loop at controlled source (e.g. gm)• T = - sr / st

– SPICE:• Controlled sources not accessible

a) Break loop, model load (approximation), orb) Determine T from Tv and Ti (exact)


Simple Circuit Example

freq, Hertz

C1

roCGSVi

C2Vo

C1

C2

gm⋅vgs

vi vovgs

Small Signal Equivalent

Loop Gain = ?

Feedback Amplifier(Biasing for Vgs not shown)


Return Ratio Analysis [HLGM 01]

freq, Hertz

roCGS

C2

gm⋅vgs

vgsC1

itest

ireturn

1. Set all independent sources to zero (vi=0)2. Disconnect (ideal) controlled source from circuit3. Replace with test source4. Find ratio return signal/test signal = “Return Ratio“ = Loop Gain

GS

GSo

GS

m

CCCCCCr

p

CCCCF

psrgFsT

+++

⋅−=

++=

+⋅⋅⋅=

12

121

21

2

1

0

)(1

1

1)(

Easy! Why not do the same thing in SPICE?


MOSFET AC Simulation Model

freq, Hertz

Small-signal model not accessible in SPICE!


Popular Simulation Approach

freq, Hertz

An ideal loop gain test circuit would:- not alter node impedances- not affect the DC bias point

Vo

1Gig∞

vreturn

vtestMockLoad

C1

C2

test

return

vvsT ≅)(

• Inaccurate• Cumbersome• Different results for

different breakpoints


Problem Generalization

freq, Hertz

Breakpoint at ideal source is not available.But there is a breakpoint “between finite impedances“

Any “single loop“ feedback circuit can be represented as:

gm⋅vx

vxZ1 Z2

available breakpoint

21

21)(ZZZZgsT m +⋅

=


Middlebrook Double Injection[Middlebrook 75]

freq, Hertz

Z1 Z2

iy

vxZ1 Z2 vy

vtest(ac)

itest(ac)

ix

1

22 ZZZgT

vv

mvx

y +⋅=≡

2

11 ZZZgT

ii

mix

y +⋅=≡

21

21

ZZZZgT m +

⋅=True Loop Gain:

Solving yields:

21++−

=iv

iv

TTTTT

• No “DC“ break in the loop, all loading effects covered.• Measure Tv and Ti, then calculate actual T


Potential Accuracy Problem of Middlebrook Method

21++−

=iv

iv

TTTTT

• For small |T|, evaluation of the above expression becomes sensitive toerrors in the individual Ti and Tv measurements

• Sensitivity analysis:in x change fractional

yin change fractional=yxS

• For small |T|, it can be shown that:T

ST TT iv

1, ≅

• E.g. at |T| =0.01 simulation accuracy decreases by a factor of 100• Not a problem in a typical circuit simulation/application• Alternative approach for the “purist“: Rosenstark method

[Rosenstark 84,Hurst 94]


Same Idea: Double Injection

freq, Hertz

Z1 Z2

iy

Z1 Z2 vyvtest(ac)

itest(ac)

2ZgTvv

mvtest

y ⋅=≡

1ZgTii

mitest

y ⋅=≡

21

21

ZZZZgT m +

⋅=True Loop Gain:

Solving yields:

iv

iv

TTTTT+

=

• Final loop gain calculation has no accuracy problems!• Problem: Broken loop, no DC path to establish bias point


Solution to DC problem

freq, Hertz

Circuit

VDC

IDC

Circuit

vtest(ac)

VDC IDC

vy

Circuit

itest(ac)

VDC

IDC

iy

• Replicate DC conditions using a closed loop dummy circuit• Looks complicated, but all sources can be conveniently combined in

a subcircuit.

Closed loop DC replica Tv measurement Ti measurement


Multiple Loops ?• All practical feedback circuits have multiple loops:- Fully differential circuits have two feedback loops- Intrinsic device feedback through Cgd, Rsource- Compensation capacitors- ...

• Solutions:- Decompose fully differential circuit into common/diff. mode loops - If a local feedback loop can be modeled as a combination of a

stable controlled source and passive impedances, the multi-loop circuit reduces to a single loop [Hurst 94].

- If there is a common breakpoint that breaks all feedback loops simultaneosly, stability can be checked by finding the return ratio at the single breakpoint [Hurst 94].


Last Resort: General Nyquist Criterion

[Bode 45]:

“If a circuit is stable when all its tubes have their nominal gains, the total number of clockwise and counterclockwise encirclements of the critical point must be equal to each other in the series of Nyquist diagrams for the individual tubes obtained by beginning with all tubes dead and restoring the tubes successively in any order to their nominal gains“

Suggestion: take a controls class if you need this!


Comments and Observations

• Problem: Simulating the “Nyquist diagrams for the individual tubes“ (return ratios) in principle requires access to the ideal breakpoints of controlled sources

• Single loop case is special in that the return ratio for the active device(s) can be found by breaking the loop anywhere in the circuit

• It is not clear how to apply the general Nyquist criterion without having ideal source breakpoints available. Best bet: Break all loops at “near ideal“ breakpoints (voltage/current drive)? Time for a good publication on this topic!

• If there is a “single tube“ that breaks all feedback, this “tube“ can be put back last in the Nyquist plot sequence and therefore establishes stability


Conclusion• Presented two methods for loop gain simulation in single loop

amplifiers• Most circuits with (parasitic) multi-loops can be reduced to a

single loop problem• Assessment of stability in a general multi-loop circuit requires

Nyquist stability check• Loop gain simulations would greatly simplify if AC transistor

models had a built-in ideal “break and inject“ capability• Stability analysis (as discussed here) assumes a linear system

• Last but not least:


Always run a transient analysis for a true stability check!

[Bode 45]:

“... thus the circuit may sing when the tubes begin to lose their gain because of age, and it may also sing, instead of behaving as it should, when the gain increases from zero as power is supplied to the circuit ...“


References

[Bode 45] H.W. Bode, Network Analysis and Feedback Amplifier Design, Van Nostrand, New York, 1945.

[Middlebrook 75] R.D. Middlebrook, “Measurement of Loop Gain in Feedback Systems,“ Int. J. Electronics, Vol. 38, No.4, .pp. 485-512, 1975.

[Rosenstark 84] S. Rosenstark, “Loop Gain Measurement in Feedback Amplifiers,“ Int. J. Electronics, Vol. 57, No.3., pp. 415-421, 1984.

[Hurst 91] P.J. Hurst, “Exact Simulation of Feedback Circuit Parameters,“ Trans. on Circuits and Systems, pp.1382-1389, Nov. 1991.

[Hurst 94] P.J. Hurst, S.H. Lewis, “Simulation of Return Ratio in Fully Differential Feedback Circuits,“ Proc. CICC 1994, pp.29-32.

[HLGM 01] P.Gray, P.Hurst, S.Lewis, R. Meyer, Analysis and Design of Analog Integrated Circuits, 4th ed., Wiley & Sons, 2001.


Example

CL

2pF

1pF

Cs

200fF

Cf

Vi

Vo

I1dc = 300uA

3 VV1dc = 700mVac = 1V

10GOhm

Rs

50GOhm

Rf

Vg

DC AnalysisDevice V1

sweep from 0 to 3 (51 steps)

DC1

1MOhmR1

Loop-GainT1Vd

AC Analysis AC1log sweep from 1k to 10G (101 steps)

Loop-Gain Analysis

M150 / 1


Loop-Gain from SPICEloopgain_examplesimulator lang=spectreoutput_options options save=all

CL ( Vo 0 ) capacitor c=2pCs ( Vi Vg ) capacitor c=1pCf ( Vg Vo ) capacitor c=200fI1 ( p Vd ) isource type=dc dc=300uVDD ( p 0 ) vsource type=dc dc=3V1 ( Vi 0 ) vsource type=dc dc=700m mag=1 xfmag=1 pacmag=1Rs ( Vi Vg ) resistor r=10GRf ( Vg Vo ) resistor r=50GR1 ( p Vd ) resistor r=1MT1 ( Vd Vo ) tech_misc_loopgain_log start=10k stop=100G points=101M1 ( Vd Vg 0 0 ) tech_cmos35_nmos w=50u l=1u ad=37.5p pd=51u

DC1 dc start=0 stop=3 lin=51 dev=V1AC1 ac start=1k stop=10G log=101


SPICE (cont.)subckt tech_misc_loopgain_log (vx vy)

parameters start=1k stop=10G points=100VX (v vx) vsourceVY (v vy) vsourceI (0 v) isourcestart_ti alter dev=I param=mag value=1

loopgain_ix xf probe=VX start=start stop=stop log=pointsloopgain_iy xf probe=VY start=start stop=stop log=points

end_ti alter dev=I param=mag value=0start_tv alter dev=VX param=mag value=1

loopgain_vx (vx 0) xf start=start stop=stop log=pointsloopgain_vy (vy 0) xf start=start stop=stop log=points

end_tv alter dev=VX param=mag value=0ends tech_misc_loopgain_log

model tech_cmos35_nmos bsim3v3 type=n …


SPICE (cont.)Vy = T1.loopgain_vy/T1.VX; // analysis / traceVx = T1.loopgain_vx/T1.VX;Iy = T1.loopgain_iy/T1.I;Ix = T1.loopgain_ix/T1.I;freq = T1.loopgain_ix/freq;

Tv = Vx / Vy; // compute resultTi = -Ix / Iy;

T = (Tv * Ti - 1) / (Tv + Ti + 2);

plot(freq, -T, "T");plot(freq, -Tv, "Tv");plot(freq, -Ti, "Ti");


SPICE Result

Stable, φm = 88 degrees(Bode criterion)


Loop-Gain by Hand

( )

( )

26MHz85.6pF2

mS2.221

121

11

1

85.61

1701000200200

=×

≅

−+=

=−+

=

=++

≅

++=

π

π FCCFgf

CFg

sFCCFg

sT

CCCC

F

fL

mu

Leff

m

fL

m

isf

f

Stable, φm = 90 degrees(single-pole system—trivial example)


Closed-Loop Gain

( )

( ) 11for

1

11

1

z

<<−−≈

−+−=

+=

−=−=

−++

−−=

=

FFFCC

gF

Cg

CCcA

FgFCC

s

gCs

CC

vvA

u

fL

mp

f

m

f

svo

m

fL

m

f

f

s

i

o

ω

ω

ω

( ) ( )∞→=+−+

=−−

omxfxfLo

fosiTx

RgvsCvCCsvCvCvCv

00


Noise

• Noise gain: 1/F• Signal gain: c < 1/F = 1 + c + Ci/Cf• Ci has no effect on c but increases 1/F increases noise gain• Choose Ci/Cf << 1+c to minimize noise enhancement• Cf inceases load lowers noise (depends also on switch resistance)

( )

( ) 11

4

11

2

2

FFCCTkv

fTgki

FgFCC

s

iv

fL

BoT

mBnd

m

fL

ndo

−+=

∆=

−++

=

( ) ( )∞→=+−+

=−

ondmxfxfLo

foTx

RigvsCvCCsvCvCv

0

EECS 240 Lecture 10: Settling © 2004 B. Boser 1

Settling• Speed/accuracy metrics• Continuous time circuits

– Bandwidth– Loop-gain, slew rate

distortion• Switched capacitor circuits

– Step response– Loop-gain

settling accuracy– Loop-bandwidth

settling time

Φ2

CfΦ1 Φ1

Cs Φ2

Φ2

ViVo


Step ResponseΦ2

CfΦ1 Φ1

Cs Φ2

Φ2

ViVo

Vi-Vo/Av

time


Step Response Analysis

Cf

Cs

ViVo

• Static error

• Dynamic error


Static Error

Avo

Cf

Cs

ViVo

Cp

Vx

Vi-Vo/Av

time

static error

oTvo

i

o

FA

cVV

11+−=

KCL

f

s

vox

o

psf

f

CCc

AVV

CCCC

F

=

−=

++=

with


Static Error (cont.)Example:

Closed loop gain: c = -4

Cf = 1pF, Cs = 4pF, Cp = 1pFF = 1/6 Note: Cp hurts!

Error specification: <0.1%

FAvo > 1000Avo > 6000 over output range

Beware: other (dynamic errors) add!

−−≅

+−=

error relative

11

11

vo

vo

i

o

FAc

FA

cVV


Dynamic Errors

• Error sources– Finite bandwidth– Feedforward zero– Non-dominant poles– Doublets– Nonlinear effects: slewing

• Analysis approach– One error at a time!– In particular: treat static and dynamic errors separately– Final result: superposition of all individual errors


Linear SettlingSingle Time Constant

• Note: Ro irrelevant at frequencies of interest (and for To >> 1)

• KCL:

• Solve:

Gm

Cf

Cs

ViVo

Cp

Vx

CL ( ) 00

=+−+

=−−

xmfxLfo

sifoTx

vGsCvCCsvsCvsCvsCv

( )m

fL

m

f

i

o

FGCFC

s

GCs

cVV

−++

−−= 1

1

1


Linear Settling (cont.)

• Loop bandwidth sets pole

• Feedforward through Cfcontributes zero

sets initial response

( )

( ) fL

m

f

m

m

fL

m

f

i

o

CFCFGp

CGz

pszs

c

FGCFC

s

GCs

cVV

−+−=

+=

+

+−=

−++

−−=

1

with

1

1

11

1


Step Response

sV

pszs

c

V

pszs

cV

sV

V

step

stepistepo

stepstepi

+

+−=

+

+−=

=

1

1

1

1

:stepoutput

:stepinput

,,

,

Frequency domain: Time domain:(inverse Laplace transform)

( )

−−−=

4434421

321321

error decayinglly exponentia

rd)(feedforwaerror initial

response ideal

, 11 ptstepstepo e

zpcVtv

Note: For p=z the error is zero and the circuit has infinite bandwidth.Applications?


Step Response (cont.)( )

( ) fLLeff

Leff

f

m

Leff

t

stepstepo

CFCC

CC

Fzp

FGC

ezpcVtv

−+=

−=

=

−−−=

−

1

:with

11response ideal

,

τ

τ

321


Case 1: -p/z << 1

Relative settling error:

mS24ns45.117.0

pF83.5

ns45.16.9

ns10

103.0

pF83.517.0

:Solution

10 ns10

pF5 pF,4 pF,14

:ionSpecificat

3

=×

==

==

<<==

==

==

======

−

τ

τ

ε

FC

G

CC

Fzp

CF

t

CcCCCCc

Leffm

Leff

f

Leff

s

Lfspf

( ) ( )( )

ετ

ε τ

ln−=

=∞→

=−∞→=

−

s

t

o

soo

t

etv

ttvtv

13.810-6

11.510-5

9.210-4

6.90.0014.60.01ts/τε

( )

−−≅

−τt

stepstepo ecVtv 1response ideal

, 321Example:


Case 2: -p/z not negligible

Relative settling error:

( )

52.0

0

3.777.067.01

10ln

pF3.167.0

:Solution

10 ns10

pF1 ,fF250 fF,250 pF,125.0

:ionSpecificat

3

3

==

−==

=

×+

−=

==

==

======

+

−

−

Leff

f

step

o

s

Leff

s

Lpfsf

CC

F

zp

cVtv

t

CF

t

CCcCCCc

τ

ε

( ) ( )( )

+−=

−=

∞→=−∞→

=−

Leff

f

s

t

o

soo

CC

F

t

ezp

tvttvtv

1ln

1

ετ

ε τ

( )

−−−≅

−τt

stepstepo ezpcVtv 11

response ideal

, 321

Example:


Non-Dominant Pole• Ignore feed-forward zero for

simplicity (homework?)

• Model for non-dominant pole

• Step response( )

m

Leffin

o

FGCs

cVVsH

+−==

1

1

( )

( )sTKp

ps

GsG

u

u

mom

of bandwidth gainunity is

1

2

2

ωω−=

−=

( ) ( )

( ) ( ) K=

=

=

− sVLtvs

VsHsV

stepostepo

stepinstepo

,1

,

,,


Non-Dominant Pole (cont.)

0 1 2 3 4 5 6 7 8 9 100

0.5

1

1.2

0

v s t 1,( )

v s t 3,( )

v s t 100,( )

1 e t−−

100 t

( )stepin

stepos cV

tvKtv

,

1, ),( :response Step =−= τ


Non-Dominant Pole (cont.) ),(-1 :error Relative Ktvs=ε

0 1 2 3 4 5 6 7 8 9 100

0.2

0.4

0.6

0.8

11

0

e s t 1,( )

e s t 3,( )

e s t 100,( )

e t−

100 t


Non-Dominant Pole (cont.) 3for K detail :error Relative =

0 1 2 3 4 5 6 7 8 9 100

0.005

0.01

0.012

0

e s t 3,( )

e t−

100 t

Non-dominant pole can speed up settling!


Non-Dominant Pole (cont.)( ) 1 ,10for K : timeSettling 3 == − τεst

• Optimum for K=3.3

• Avoid K < 2

0 1 2 3 4 5 6 7 8 9 102

4

6

8

10

12

1415

3.508

t s ε K,( )

ln ε( )−

100.8 K


Doublets• Doublet = “closely spaced pole/zero pair”• Origins:

– Feedforward path (e.g. Miller capacitor)– Frequency dependent degeneration

(cascode, gain boosting)– etc.

• Concerns:– Ringing (if high-Q)– Slow settling if doublet frequency < ω-3dB of T(s)– Hard to see from SPICE output (esp. ac analysis)


Doublet Analysis• Amplifier model:

• Closed-loop gain (ignore feedforward zero):

p

zmom s

s

GsG

ω

ω

+

+=

1

1)(

( )

1 h wit1

of bandwidth is , 33

<<+=

=

= −−

εεααω

ω

ωβωω

pz

dBdBp sT

with

( )

+

+

+−≅

+−=

− pp

z

dBm

Leffin

o

s

s

sc

sFGC

sc

VV

ω

ω

ω1

1

11

1

3ppp

Leff

modB C

FG

ωω

ω

≅

=−3

with


Doublet Analysis (cont.)• Step response

• Two exponentially decaying errors with time constants

( ) ( )ppdB ttstepstepo BeAecVtv ωω −− ++−= −31,

21

1

ββε−

≅

−≅

B

Awith

ppdB ωτωτ 1 and 12

31 ==

−


Doublet Example

0 1 2 3 4 5 6 7 8 9 10

0

0.5

11.1

0.1−

v s_no_doublet t( )

v s_doublet_term t α, β,( )

v s_doublet t α, β,( )

100 t

9 10 11 12 13 14 15 16

0.005

0

0.005

0.01−

1 v s_no_doublet t( )−

1 v s_doublet t α, β,( )−

169 t

α=1.5β=0.3


Doublet Conclusions• Case A:

– Doublet settles much faster than amplifier– Has no impact on overall settling time

• Case B:– Doublet settles more slowly than amplifier– Determines overall settling time

(unless ε within settling accuracy requirements … only met in “low accuracy” situations, cf. scope probes)

• Avoid “slow” doublets!

1 i.e. 12 ≥≤ βττ

12 ττ >


Slewing

• Transconductor– Differential pair– Class (A)B input stage

• Model for (nonlinear) slewing amplifier– Piecewise linear approximation:

• Slewing with constant current, followed by• Linear settling exponential• ts = tslew + tlin


Slewing Analysis• Circuit model during slewing:

Cs

Cp CL

Cf

VoVxVi ISS


Slewing Analysis (cont.)

time

Vi

Vx

Votslew

Vi,step

Vdsat

tlin

Vx,step

Vo1,step


Slewing Analysis (cont.)• Slewing period:

• Linear settling: reduced step size!– Complete step at output:

– Step during linear settling:

– Scaled accuracy:

Leff

SSoslew

xo

satdstepxx

Lf

Lfp

s

sstepistepx

CISR

SRVt

FVV

VVV

CCCC

CCCC

CVV

=∆

=

∆=∆

−=∆

++=

+=

th wi

ith w

,

22

,,

stepicV ,

FV satd

εεε >= satd

stepilin V

FcV ,

EECS 240 Lecture 11: Common-mode Feedback B. Boser 1

Common-Mode Feedback

• Problem– High gain (~ Adm) from tail current source to Voc amplifies mismatch– Voc rails at either supply

• Solution– Feedback to regulate Voc to desired value Vcmfb0

(usually ~ mid-supply)– Control point: tail or load current source(s)– How do we get Voc?

• Resistive divider• Amplifier• Capacitive divider

EECS 240 Lecture 11: Common-mode Feedback B. Boser 2

Dynamic CMFB

• Stability of CMFB loop• Loop gain• Settling accuracy, speed• Simulation

– Transient– AC

EECS 240 Lecture 12: Two Stage OTA B. Boser 1

OTA RealizationsSingle stage OTA• Single high impedance

(voltage gain) node• Near maximum power efficiency• Limited gain and/or output range• Can be combined with cascodes,

gain boosting• Examples:

– Telescopic OTA• Maximum power efficiency• Limited input common-mode range

– Folded cascode• Large input common-mode range• Slightly improved output range• Folding adds noise and power

penalty

Multi stage OTA• Advantages over single stage OTA

– Reduced interaction between gain and output range

– Somewhat higher drive capability for given Cin

• Disadvantages– Increased power dissipation or

reduced speed– Need for compensation

• Examples:– Miller-compensated 2-stage OTA– OTA with preamp (power efficiency?)– Nested Miller compensation


Multi-Stage OTAs• Advantage

– Higher gain– Improved output voltage swing– Potentially reduced input capacitance– Power dissipation? Noise?

• Challenges– Stability: needs compensation (usually)– Reduced bandwidth (2 … 3 times smaller per added stage)

• Approaches– 2 high-gain stages with Miller compensation– Wide-band preamp (e.g. T. Cho, JSSC 3/95)– Nested Miller compensation (e.g. G&M, 4th ed.)


2-Stage OTA Example

M1a M1b

M4b

M=2

M3b

M6c

M=2

M5c

M=2

M2b

M7b

Vxx

M2a

M7a

Vbias2

Vbias1

M3a

M4a

M=2

Vbias5 Vbias5

VDD

VSS

VobVoaVibVia

M5a

V1bV1a

OTA Core

V5a V5bVcmfb

M6bM6aVbias3

Ibias12Ibias1

Ibias2

2Ibias1

M5bVbias4

RcaCca

V2aRcb

CcbV2b


2-Stage CMFB

OTA CMFB

Mc1a

15/0.5

Mc1b

15/0.5

Mc3

M=1

Mc4

M=1

Vxx

VDD

VSS

Vbias2

Vbias1

Vc

Voa

Vob

Swa,p1p

Swc

VGNDASwb

Ccmfbb100fF

Ccmfba100fF

Ibias1

Ibias1/2Ibias1/2

VGNDA

Mc5b

M=0.5

Mc5a

M=0.5

Vcmfb

Mc6

M=0.5

Vbias3


Compensation Techniques

• Narrowbanding– Very small compensated bandwidth– Lower dominant pole or add new dominant pole– E.g. offset cancellation loop

• Miller compensation– Capacitive feedback splits poles– Zero adds phase lag

• Nulling resistor• Cascode compensation


No Compensation

2 dominant poles poor phase margin if placed into feedback loop

22110

222

2

111

1

1

RgRga

CCCR

p

CRp

mmv

L

=

=−=

−=


Miller Compensation

• RHP zero

• Caused by capacitive feed-forward

• Often adds significant phase lag(see root locus)

( )

( )

22110

2

212

2

2121

22

0

1

1221

,

11

RgRgaCgz

CCCCg

CCCCCCgp

Cag

CRRgp

mmv

c

m

cm

c

cm

cv

m

cm

=

+=

<<−≈

++−≈

−≈+

−≈


Phase Margin Engineering

• Choose K>2 for reasonable phase margin

• Increasing CL=C2 lowers phase margin

• Zero adds significant phase lag unless gm2>>Fgm1, regardless of Cc

c

m

m

u

m

mc

u

uc

mu

CC

pz

gg

Fz

ggKFCC

Kp

sTzpCgF

2

2

(MOS) 10..11

2

1

2

12

2

21

1

choose

)( of ,

≈

=

≥

≥

>>≈

<

ω

ω

ωω


Mitigating Phase Lag from Zero

• Unilateral Feedback – Source Follower

• Limits output swing

– Cascode Compensation• Ahuja, JSSC 12/1983• Ribner, JSSC 12/1984

• Nulling Resistor– Zero to infinity– Zero cancels p2


Cascode Compensation (Ahuja)

• No zero (ideal cascode)

• p2 at higher frequency

• Translates into smaller Ccfor given C2

• Problems:– Current I2– Slewing– Mismatch (in I2) causes

offset

( )

434211usually

12

2*2

12

22

0

1

1221 1

1

>

+=

+−≈

−≈+

−≈

CC

CCCp

CC

CCgp

Cag

CRRgp

c

c

c

c

m

cv

m

cm


Cascode Compensation (Ribner)

• Uses cascode in signal path• No new current path• Avoids slewing and matching problem• 3rd order response

very difficult to design


Nulling Resistor Rz

• Rz limits feedforward current at high frequency

• Zero moves to higher frequency (and ultimately LHP)

• New pole p31

3

21

2

1change no :,

11

CRp

pp

CRg

z

z

cZm

−≈

−

→


Zero to Infinity

• No phase shift from zero

• Phase lag from p3decreases as Cc is increased

• Implementation of Rz?

1

22

2

12

2

usually11

23

321

1

23

2

For

11

,

1

m

mc

m

mc

u

c

m

m

u

uc

mu

m

mz

gg

KFCC

ggKFCC

Kp

CC

gg

Fp

ppCgF

Cgp

zg

R

≤

≥

≥

>>=

>>≈

−≈

∞→

=

ω

ω

ωω


Zero Cancels p2

• Increased bandwidth

• Smaller Cc for given C2

• Doublet not necessarily faster settling

11

22

3

31

13

2

2

For

polet nondominannew theis 1

11

CC

gg

KFCC

Kp

pCgF

CRp

CC

gR

c

m

mc

u

uc

mu

z

cmz

≤

≥

>>≈

−≈

+=

ω

ωω


Noise Analysis

M1

M2

Cc

CL

vo

vi = -Fvo

Simplified schematic: ( )( ) 0

0

22

11

=+++=+−−

ncLoxm

nomoxc

iCCsvvgivFgvvsC

( )

c

mo

Lcc

mmo

m

cnn

oo

mo

CFgQ

CCCgFg

gsCii

sQsFg

v

1

212

221

2

21

with

1

11

=

+=

−

++=

ω

ω

ωω


Total Noise at Output

• Noise from first stage dominates• Noise capacitor: Cc, NOT CL!

++=

<43421

M2)from (noise 1

2 1Lc

c

c

BoT CC

FCFC

Tkv γ


Nested Miller Compensation

• >2 gain stages• Higher order response

presents design challenge• Not (yet?) used much

Ref: R. G. H. Eschauzier and J. H. Huijsing. Frequency Compensation Techniques for Low-Power Operational Amplifiers. Kluwer, 1995.

EECS 240 Lecture 13: Output Stages B. Boser 1

Output Stages

• Driving large (resistive) loads– RC-filters (anti-aliasing)– Off-chip loads– Line driver

• Twisted pair: Ethernet, ISDN, ADSL, HPNA• Coax


OTA

• Transconductance amplifier(common-source)

• Excessive power dissipation

• Only appropriate for modest loads and multi-stage amplifiers

µA100k102

10mV200

mA100k102

000,10mV200

mA20502

10mV200

A20502

000,10mV2002

2

*

*

=Ω××

=Ω×

×

=Ω××

=Ω×

×

≥

==

L

vD

LD

Lmv

RAVI

RVIRgA


Source Follower

• Impractical for VDD < 5V

• Push-pull follower– Class (A)B– Cross-over distortion– Quiescent current control


Class (A)B Common-Source

• Essentially inverter• Very nonlinear

– Need feedback– Local (error amplifiers)– Global

• Biasing– Dynamic– Floating voltage source


Floating Voltage Source

M110 / 0.35M=10

M220 / 0.35M=10

M310 / 0.35

M420 / 0.35

M510 / 0.35

M610 / 0.35

I1dc = 100uA

M720 / 0.35

M820 / 0.35

I2dc = 100uA

I3dc = 100uA

I4dc = 100uA

Vout

VDD

VSS

Vg1

Vg4

Vg3

Vg2


References• D. M. Monticelli, "A quad CMOS single-supply op amp with rail-to-rail output swing," IEEE

Journal of Solid-State Circuits, vol. 21, pp. 1026 - 1034, December 1986. Original idea.

• R. Hogervorst, J. P. Tero, R. G. H. Eschauzier, and J. H. Huijsing, "A compact power-efficient 3 V CMOS rail-to-rail input/output operational amplifier for VLSI cell libraries," IEEE Journal of Solid-State Circuits, vol. 29, pp. 1505 - 1513, December 1994. A CMOS realization.

• K. de Langen and J. H. Huijsing, "Compact low-voltage power-efficient operational amplifier cells for VLSI," IEEE Journal of Solid-State Circuits, vol. 33, pp. 1482 - 1496, October 1998. Alternative implementation of floating voltage source for low VDD operation.

• J. N. Babanezhad, "A low-output-impedance fully differential op amp with large output swing and continuous-time common-mode feedback," IEEE Journal of Solid-State Circuits, vol. 26, pp. 1825 - 1833, December 1991. Combination of CS & CD class AB output stages.


Test Setup

Vg1

Vg2

CCCS1

CCCS2

I1

V1

Supply

VDD = 1.5VVSS = -1.5V

DC Analysis

sweep from -500n to 500n (200 steps)Device I1

DC1

R11MOhm

R21MOhm

Vg1_

Vg2_


Vgs1, Vgs2


ID3, ID4


ID1, ID2 (Vout = 0V)

• Large current capability• Defined quiescent current• M1, M2 never turn off


ID1, ID2 (Vout = 1.3V)

• Reduced current drive capability for outputs close to rail


gm1, gm2 (Vout = 0V)

• Significant variation• Weak inversion?• Circuit not linear!• Stability?


gm1, gm2 (Vout = 1.3V)


FeedbackLocal

K. E. Brehmer and J. B. Wieser, "Large swing CMOS power amplifier," IEEE Journal of Solid-State Circuits,vol. 18, pp. 624 - 629, December 1983.

Global

J. H. Huijsing and D. Linebarger, "Low-voltage operational amplifier with rail-to-rail input and output ranges," IEEE Journal of Solid-State Circuits, vol. 20, pp. 1144 - 1150, December 1985.


Nested Miller Feedback

• Nonlinearities are attenuated by loop-gain with all loops (compensation) opened multistage amps have an advantage in the mid-band over single-stage with same dc gain

• Some implementations combine local with nested Miller feedback

Ref: S. Pernici, G. Nicollini, and R. Castello, "A CMOS low-distortion fully differential power amplifier with double nested Miller compensation," IEEE Journal of Solid-State Circuits, vol. 28, pp. 758 - 763, July 1993.


Implementation Example


Nested Miller Amplifier

gm1 +gm2 -gm3

Cm2

Cm1

C1 C2 CL

Vi Vo

v1 s Cm1⋅( )⋅ gm1 vi⋅− vo s⋅ Cm1⋅− 0

v2 s Cm2⋅( )⋅ gm2 v1⋅− vo s⋅ Cm2⋅− 0

vo s CL⋅ s Cm1⋅+ s Cm2⋅+( )⋅ gm3 v2⋅+ s Cm1⋅ v1⋅− s Cm2⋅ v2⋅− 0

1 ,1 ,1 ,

:sAssumption

32211

2211

>>>>>><<<<

Lmmm

mm

RgRgRgCCCC


Nested Miller OTA Analysisa s( )

v ov i

g m1s C m1⋅

−

1 sC m2g m3⋅− s2 C m1 C m2⋅

g m2 g m3⋅⋅−

1 s C m2⋅1

g m2

1g m3

−

⋅+ s2 C L C m2⋅

g m2 g m3⋅⋅+

2

13

12

223

221

32

2

2

22

,1pole)dominant is ( for

11

11)(

aap

ap

ppp

sasapps

ps

ps

pssD

−≅−≅

>>

++=+−≅

−

−=

Dominant pole approximation:p 1 0

p21

Cm2−

gm2 gm3⋅

gm3 gm2−⋅

gm2Cm2

−

p 3 C m2−g m3 g m2−

g m2 g m3⋅⋅

g m2 g m3⋅

C L C m2⋅⋅

g m3 g m2−

C L−

g m3C L

−

ω ug m1C m1

uppp ω>>>> 223 and :sAssumption

Note: for larger parasitics, p2, p3 can be complex. Faster?


Feedforward Zeros

1 sC m2g m3⋅− s2 C m1 C m2⋅

g m2 g m3⋅⋅− 0

z112

−gm2Cm1⋅ 1 1 4

Cm1 gm3⋅

Cm2 gm2⋅⋅++

⋅ 0< LHP

z212

−gm2Cm1⋅ 1 1 4

Cm1 gm3⋅

Cm2 gm2⋅⋅+−

⋅ 0> RHP, potential problem


Design Example

z2

ωu22.871=

z2

2 π⋅228.714MHz=z2

12

−gm2Cm1⋅ 1 1 4

Cm1 gm3⋅

Cm2 gm2⋅⋅+−

⋅:=

z1

ωu72.871−=

z1

2 π⋅728.714− MHz=z1

12

−gm2Cm1⋅ 1 1 4

Cm1 gm3⋅

Cm2 gm2⋅⋅++

⋅:=

gm1 0.113mS=gm1 Cm1 ωu⋅:=

Cm1 1.8pF=Cm1 3 C1⋅:=

C1 0.6pF=C1gm2

ωT2:=ωT2 2 π⋅ 1.5⋅ GHz:=

gm2 5.655mS=gm2 K2 Cm2⋅ ωu⋅:=

Cm2 30pF=Cm2 3 C2⋅:=

C2 10pF=C2gm3

ωT3:=ωT3 2 π⋅ 1⋅ GHz:=

gm3 62.832mS=gm3 K3 CL⋅ ωu⋅:=

design:

K2 3:=p2 K2 ωu⋅

K3 10:=p3 K3 ωu⋅

ωu 2 π⋅ fu⋅:=fu 10MHz:=CL 100pF:=

given:

Small RL could set additional constraint.


More Conservative Choices

z2

ωu10.635=

z2

2 π⋅106.348MHz=z2

12

−gm2Cm1⋅ 1 1 4

Cm1 gm3⋅

Cm2 gm2⋅⋅+−

⋅:=

z1

ωu29.385−=

z1

2 π⋅293.848− MHz=z1

12

−gm2Cm1⋅ 1 1 4

Cm1 gm3⋅

Cm2 gm2⋅⋅++

⋅:=

gm1 0.113mS=gm1 Cm1 ωu⋅:=

Cm1 15.36pF=Cm1 8 C1⋅:=

C1 1.92pF=C1gm2

ωT2:=ωT2 2 π⋅ 1.5⋅ GHz:=

gm2 18.096mS=gm2 K2 Cm2⋅ ωu⋅:=

Cm2 72pF=Cm2 6 C2⋅:=

C2 12pF=C2gm3

ωT3:=ωT3 2 π⋅ 1⋅ GHz:=

gm3 75.398mS=gm3 K3 CL⋅ ωu⋅:=

design:

K2 4:=p2 K2 ωu⋅

K3 12:=p3 K3 ωu⋅

ωu 2 π⋅ fu⋅:=fu 10MHz:=CL 100pF:=

given:

EECS 240 Lecture 14: Comparators B. Boser 1

Comparator

• Clock rate fs• Offset• Resolution• Overload Recovery• Input capacitance (and linearity!)• Power dissipation• Common-mode rejection• Kickback noise• …

Av LatchVi+

Vi-

Do+

Do-

fs


Flash Converter

• Very fast: only 1 clock cycle per conversion

• High complexity: 2B-1 comparators

• High input capacitance

R/2

R

R

R

R/2

R

Encoder DigitalOutput

VINVREF


Comparator GainExample:

• 12-Bit / 100MS/s ADC• 1V full-scale input

1 LSB = 1V / 212 = 240µVAv > 1V / 120µV = 8000 in 5ns!


Operational Amplifier?

Avo

fuf-3dB

Gain

Freq

THz3.1ns12

80002

21

33

=×

=

=

=→=−

−

π

πτ

πτ

vou

dBvo

udB

Af

fAff


Open-Loop Amplifier Cascade


Cascaded Amplifier

• Step response:

( )

( ) ( )

( ) ( )

M

in

T

od

momo

in

T

od

momo

ind

T

o

minmo

VTCgdttvg

Ctv

VTCgdttvg

Ctv

VTCgdtVg

Ctv

d

d

d

∫

∫

∫

==

==

==

33

12

22

12

1

31

211

211

1( )

N

Ain

outmd

in

Nd

N

moN

vN

T

VVN

CgT

VNT

Cgtv

!

!~

=

=

ω


Gain versus Delayvo N t,( )

1N!

tN⋅:=

0 1 2 3 4 50

5

10

15

20

25

vo 1 tx,( )

vo 2 tx,( )

vo 5 tx,( )

tx


Optimum Number of StagesTd AvN N,( ) AvN N!( )⋅

1N

:= Nx 2 10..:=

2 3 4 5 6 7 8 9 100

10

20

30

40

50

Td 100 Nx,( )Td 1000 Nx,( )Td 10000 Nx,( )

Nx

Shallow minimum!


Optimum

• Shallow optimum!• In practice, limit to 4 … 6 gain stages (area, power, parasitics)• Can get same speed with single latch … but higher offset

2.310 :gain/stage optimum

ln2.1ln2.1

0

,

≅

≅

≅

→=

vNoptd

vNopt

d

ATAN

dNdT

τ


Practical Considerations• Overload recovery:

Vin

time V1

V2

Vout

time

Solutions:• Clamps• Reset


Output Common-Mode


Latchgm

gm

( ) ( )

( ) ( )

vNoptd

v

id

od

md

m

m

id

AT

AVV

gCT

Ctvg

Cti

dtdv

Ctvg

Cti

dtdv

tVt

ln2.1amplifiers of cascade optimal :compare

ln

ln

feedback positive :0 toC initialize :0

,

122

211

τ

τ

≅

=

=

==

==

≥<


CMOS Comparator Example

A. Yukawa, “A CMOS 8-Bit High-Speed A/D Converter IC,” JSSC June 1985, pp. 775-9.


Dynamic Latch

T. B. Cho and P. R. Gray, "A 10 b, 20 Msample/s, 35 mW pipeline A/D converter," IEEE Journal of Solid-State Circuits, vol. 30, pp. 166 - 172, March 1995.


Latch with Preamp

M. Choi and A. A. Abidi, "A 6-b 1.3-Gsample/s A/D converter in 0.35-µm CMOS," IEEE Journal of Solid-State Circuits, vol. 36, pp. 1847 - 1858, December 2001 and many others …


Comparator with Auto-Zero

I. Mehr and L. Singer, “A 500-Msample/s, 6-Bit Nyquist-Rate ADC for Disk-Drive Read-Channel Applications,” JSSC July 1999, pp. 912-20.


Auto-Zero Implementation

I. Mehr and L. Singer, “A 55-mW, 10-bit, 40-Msample/s Nyquist-Rate CMOS ADC,” JSSC March 2000, pp. 318-25.

EECS 240 Lecture 15: Coupling and Isolation B. Boser 1

Coupling Mechanisms

• Interconnects– Mostly capacitive– Distance helps– Isolation in time

• Package (bond wires)• Supply• Substrate


Package

• L, M• dI/dt: beware of fast transients

– Fast corner– Testing: cool chip!

• Differential circuits• Orthogonal bond wires• Isolation with time


Power Supply

• Line / battery• Regulator• PCB Traces, decoupling• IC package• IC supply• Circuit block


Substrate

• Injection mechanisms• Epitaxial vs high resistivity substrate• Substrate contact

– Minority carrier– Majority carrier– Backside contact

• Guard ring– Isolation– Latchup


Common Substrate Types


Epitaxial Substrate

D. K. Su, M. J. Loinaz, S. Masui, and B. A. Wooley, "Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits," IEEE Journal of Solid-State Circuits, vol. 28, pp. 420 - 430, April 1993.

Note:Lack of backside wafer contact substantially increases coupling!


Observed Waveforms


Current Flow in Epi-Substrate

• Majority of current flows in low-resistivity wafer

• Coupling is very weak function of distance


Cross-Talk versus Distance


Effect of Guard RingLarge guard rings increase coupling!

Epi substrate


Model for Guard Ring

Shared guard ring contact reduces isolation!


Backside Contact


Noise vs L4


Current in High Resistivity Substrate


Simulation / AnalysisR. Gharpurey and R. G. Meyer, "Modeling and analysis of substrate coupling in integrated circuits," IEEE Journal of Solid-State Circuits, vol. 31, pp. 344 - 353, March 1996.

Balsha R. Stanisic, Nishath Verghese, Rob A. Rutenbar, L. Richard Carley, David J. Allstot; Addressing substrate coupling in mixed-mode ICs: Simulation and power distribution synthesis, IEEE Journal of Solid-State Circuits, vol. 29, pp. 226 - 238, March 1994.

Kuntal Joardar; A simple approach to modeling cross-talk in integrated circuits, IEEE Journal of Solid-State Circuits, vol. 29, pp. 1212 - 1219, October 1994.

Nishath Verghese, David J. Allstot; Computer-aided design considerations for mixed-signal coupling in RF integrated circuits, IEEE Journal of Solid-State Circuits, vol. 33, pp. 314 - 323, March 1998.

A. Samavedam, A. Sadate, K. Mayaram, and T. S. Fiez, "A scalable substrate noise coupling model for design of mixed-signal IC's," IEEE Journal of Solid-State Circuits, vol. 35, pp. 895 -904, June 2000.


Epi Substrate Coupling

R. Gharpurey and R. G. Meyer, "Modeling and analysis of substrate coupling in integrated circuits," IEEE Journal of Solid-State Circuits, vol. 31, pp. 344 - 353, March 1996.


Low Resistivity Substrate


High Resistivity Substrate


Guard Ring


Guard Ring

High resistivity substrate


Guard Ring Guidelines

• Marginal improvement of isolation on heavily doped substrates– May still be needed to prevent latchup

• Dedicated grounds• Keep guard ground bondwire away from signals• Excessively wide / close guard rings reduce isolation• Place guard ring close to sensitive node• Use in analog and digital regions, analog being more

important


Latchup

Poly

p- substrate

n- well

p+ diffusion

n+ diffusion


Latchup Circuit

• Latchup:– Forward biased junction

minority carrier injection– QN or QP turns on– Supplies IB to QP or QN

– Positive feedback if βN βP > 1– SCR: “silicon controlled rectifier”

• Preventing latchup:– βN βP < 1

QN

QP

Rwell

Rsub

VDD

VSS


Preventing Latchup

• βN βP < 1– Increased layout spacing

increased parasitic base width– Increased doping

increased carrier recombination in base

• Prevent minority carrier injection– no forward biased junctions

• Minority carrier collectors

EECS 240 Lecture 16: Matching and Layout B. Boser 1

Device Matching Mechanisms• Spatial effects

– Wafer-to-wafer– Long range

• Gradients– Short range

• Statistics

• Circuit effects– Differential structures

• Differential pair• Current mirror

– Bias• Layout effects


Mismatch Model

• What is modeled?– Short-range, random processes, e.g.

• Dopant fluctuations• Mobility fluctuations• Oxide trap variations

• What is NOT modeled?– Batch-to-batch or wafer-to-wafer variations– Long-range effects such as gradients– Electrical, lithographic, or timing offsets


References• M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers,

"Matching properties of MOS transistors," IEEE Journal of Solid-State Circuits, vol. 24, pp. 1433 - 1439, October 1989. – Mismatch model– Statistical data for 2.5µm CMOS

• Jeroen A. Croon, Maarten Rosmeulen, Stefaan Decoutere, Willy Sansen, Herman E. Maes; An easy-to-use mismatch model for the MOS transistor, IEEE Journal of Solid-State Circuits, vol. 37, pp. 1056 - 1064, August 2002.– 0.18µm CMOS data– Qualitative analysis of short-channel effects on matching


Mismatch Statistics

• Composed of many single eventsE.g. dopant atoms

• Individual effects are smalllinear superposition applies

• Correlation distance << device dimensions

• Mismatch has Gaussian distribution, zero mean


MOSFET Mismatch Parameter

Experiment:

• Experimental result applies to one particular configuration

• What about:– Device size

• W• L• Area

– Bias• VGS

– Physical proximity– …

• Need parameterized model

M2M1

%1=∆

D

D

II


Geometry Effects

( ) 222

2xP

P DSWLAP +=∆σ

( )

layout centroid-commonfor 0 : parameter, distance measured :

parameterarea measured :centers device between distance :

area gate active : Pof deviation standard :2

≅

∆

P

P

x

SADWLPσ


Example: VTH

( ) 22,

2,

02

0

0xVP

VPTH DS

WLA

VTH

TH +=∆σ

process) CMOS µm5.2(

m mV 35m mV 30

,

,

µµ

≅

≅

PMOSP

NMOSP

AA


Drain Bias, VDS

∆VTH0 virtually independent of VDS


Back-Gate Bias, VSB

• Pair 3 exhibits significant VSBdependence

• Why?– Non-uniform doping

profile (VTH adjust)

[ ]( )( ) ...

...2

2

0

=

=

Φ−−Φ+=

γσ

σ

γ

TH

BBSBTHTH

V

VVV


Current Matching, ∆ID/ID

Strong bias dependence (we knew that already)


Current Factor

LWCoxµβ =


Edge Effects

• Relative Matching?

• Model?


Edge Model

for

this simplifies to

( ) ( ) ( ) ( ) ( )2

2

2

2

2

2

2

2

2

2

n

n

ox

ox

CC

LL

WW

µµσσσσ

ββσ

+++=

( ) ( ) LLWW 1 and 1 22 ∝∝ σσ

( ) 2222

2

2

2

2

2

2

DSWLA

WLA

LWA

WLA oxCWL

βµ

ββσ

++++=


Orientation Effect

• Si and transistors are not (perfectly) isotropic

• keep direction ofcurrent flow same!


Distance Effect


Model Summary


Example: Current Mirror


Example: Bandgap Reference

• σVBG = 25 mV• Dominated by amplifier

offset• Area – offset tradeoff


Process Dependence

Example: ∆VTH vs. tox

• VTH matching appears strongly correlated with tox

• Reason?– tox is not only difference– Doping concentration?


0.18 µm CMOS


0.18 µm CMOS


Example: Current Mirror

( )222

2

*2

1

2β

σβσσ

ββ

∆∆ +

≅

∆+∆=

∆

∆THDI

DI V

THD

m

D

D

V

VIg

II

( )

( ) ( )( )2A

V2

AµmV3

AµmV3

22

2

2226

2

22

34

2

24

1 6.15µm25.0µm100

1091.0µm25.0µm100

101.6

.15mV1µm25.0µm100µmV103.33

=×

×−

××

=+≅

=×

×=≅

∆

−

∆

LWA

WLA

LW

WLA

Wo

oVTH

βσ

σ

( )22

%31.0

2

2

2

%58.0

2 %66.0AV6.15

VµA200

mV200.15mV1

=

×+

≅∆

444 3444 2143421DIDIσ

NMOS µm25.0µm/100


Example: Differential Pair

( )22

2*22

*

12

2

βσβσσ

ββ

∆

+=

∆+∆=

V

VVV

THos VV

THos

( )

( ) ( )( )2A

V2

AµmV3

AµmV3

22

2

2226

2

22

34

2

24

1 6.15µm25.0µm100

1091.0µm25.0µm100

101.6

.15mV1µm25.0µm100µmV103.33

=×

×−

××

=+≅

=×

×=≅

∆

−

∆

LWA

WLA

LW

WLA

Wo

oVTH

βσ

σ

( ) ( )22

mV19.0

2

222 .17mV1

AV6.15

VµA200

2mV120.15mV1 =

××+≅

44444 344444 21osV

σ

NMOS µm25.0µm/100


“Careful” Layout

• Minimize systematic errors– Geometry

• Proximity effects: diffusion, etch rate• Orientation

– Gradients• Process• Temperature• Stress

Ref: A. Hastings, “The art of analog layout,” Prentice Hall, 2001


Layout Tradeoffs• Matching often involves tradeoffs:

– Increased channel length– Increased circuit area– increased power dissipation, reduced speed, …

• Determine required level of matching– Minimal:

• 3σVos > 10mV, 3σ∆ID/ID > 2%• Unit elements, matched orientation, compact layout

– Moderate: • 3σVos > 2mV, 3σ∆ID/ID > 0.1%• Apply most or all layout rules

– Precise:• Trimming or self-calibration


1. Unit elements

• Equal L• Equal W (use M)


2. Large Active Areas

• Reduce random variations• Use statistical analysis as a guide


3. Bias Point

• Voltage matching (differential pair):– Small V*– Long L

• Current matching (mirror):– Large V*– Same VDS


4. Same Orientation

• Transistors “look” symmetrical• Actual devices are not:

– Silicon is not isotropic– Implants are not isotropic

• What about ac?


5. Compact Layout

• Minimize stress and temperature variations & random fluctuations

• Avoid poor MOSFET aspect ratio– E.g. W/L = 1000/0.35– Use fingers: 50/0.35, M=20

~ square layout


6. Common Centroid Layout

• Cancels linear gradients• Required for moderate matching• Common-centroid rules:

– Coincidence– Symmetry– Dispersion– Compactness– Orientation


7. Dummy Segments

• Place dummy segments at ends of arrayed devices

• Protects from processing non-uniformitye.g. etch-rate


8. Stress Gradients

• Global: from package– Place devices in areas of low stress– Generally center of chip– At odds mixed-signal floor plans

• Local: metalization– Do not route metal across active area– If unavoidable: add dummies so that each

device sees same amount of metal


9. Contacts

• Do not place contacts on top of active area– Induce threshold mismatch– God knows why …

• Compromise: minimize the number and make each gate identical

• Beware of proximity effects when connecting multiple gates with poly– Use metal interconnects or– Use poly connectors on either side of transistor


10. Junctions

• Keep all junctions and deep diffusions away from transistors (except S/D)– Extend well boundary at least 2x junction

depth– Just because the layout rule permits it,

minimum spacing is not always the best solution• Not all spaces are critical for overall layout area


11. Oxide thickness

• Devices with thinner oxide usually exhibit better matching– Use minimum tox devices for best matching

if the process offers a choice


12. NMOS vs PMOS

• NMOS usually exhibit better matching than PMOS– Why?– Random matching, 0.18µm data:

• VTH of PMOS has better matching (2x)• β of NMOS matches better (4.5x !)


13. Power Devices

• Power devices create temperature gradients and inject carriers into the substrate– dVTH / dT = -2mV/oC !

• Keep matched devices away from power sources (>50mW)

• Beware of “Temperature Memory Effect”:Use common-centroid layout for matched devices with different current density


Common-Centroid Layout

• Determine groups of matched components• Depends on circuit function• E.g.

• All transistors in a mirror• Diff-pair and load in an amplifier

• Should they be matched individually or jointly?

• Divide into segments• Unity element• Avoid small (<70%) fractional elements if no GCD


Common-Centroid Patterns• Coincidence:

– Center of all matched devices co-incide

• Symmetry:– X- and Y-axis– R’s and C’s exhibit 1-axis symmetry

• Dispersion:– High dispersion reduces sensitivity to higher order (nonlinear)

gradients– E.g.

• ABBAABBA: 2 runs (ABBA) of 2 segments (AB, BA)• ABABBABA: 1 run of 2 segments (AB, BA)• ABABBABA has higher dispersion (preferable)


Common-Centroid Patterns• Compactness:

– Approximately square layout– 2D patterns

• Better approximation of square layout• Usually higher dispersion possible, e.g.

DASBD DASBDBSAD DASBDBSAD DBSAD DBSADASBD DBSADASBD

DASBDBSADDBSADASBD

• Orientation:– Stress induced mobility variations: several percent error– Tilted wafers: ~5% error

EECS 240 Lecture 17: MOS S & H B. Boser 1

MOS Sample & HoldIdeal Sampling Practical Sampling

vIN vOUT

CS1

φ1

vIN vOUT

CM1

φ1

• Grab exact value of Vinwhen switch opens

• kT/C noise• Finite Rsw limited bandwidth• Rsw = f(Vin) distortion• Switch charge injection• Clock jitter


kT/C Noise

2

2

1212

12

−≥

∆≤

FS

B

B

B

VTkC

CTk

0.003 pF0.8 pF13 pF

206 pF52,800 pF

812141620

Cmin (VFS = 1V)B [bits]


MOSFET as Resistor• “off” state

– Roff– Ioff … beware of subthreshold conduction– Capacitive coupling– T-switch

• “on” state– Operate in triode region with VDS small– Nonlinear– Threshold voltage, Body effect– N/P/C-MOS– Constant VGS switch


Switch On-Resistance

M_n10 / 0.35

M_n10 / 0.35

M_n10 / 0.35

Supply

VDD = 3VVSS = 0V

VC_N1us

VC_N1us

VC_P1us

M_p25 / 0.35

M_p25 / 0.35

Vi

VDSdc = 100mV

MOS Switch On-Resistance

DC Analysis

sweep from 0 to 3 (100 steps)Device Vi

DC_Vi

vcn

vcp

va

vb

M_const10 / 0.35

M_const10 / 0.35

M_const10 / 0.35

M_const10 / 0.35

M_const10 / 0.35

M_const10 / 0.35

VC_CONST1us

VC_CONST1us

VC_CONST1us

VC_CONST1us


Acquisition Bandwidth• The resistance R of switch

S1 turns the sampling network into a lowpass filter with risetime = RC = τ

• Assuming Vin is constant during the sampling period and C is initially discharged (a good idea—why?):

vIN vOUT

CS1

φ1

R

( )τ/1)( tinout evtv −−=



Example:B = 14, C = 13pF, fs = 100MHzT/τ >> 19.4, R << 40Ω

vIN vOUT

CS1

φ1

φ1

T=1/fS

R

( )

CBfR

BTT

Vvev

ftvv

s

B

FSin

fin

soutin

s

72.0

72.012ln

12

:CaseWorst

21

21

<<

≈−

<<

=∆<<

∆<<

=−

−

τ

τ



( )

( )

( )

THDD

in

THDD

in

DS

VVvo

ON

THDDox

oVV

vo

inTHDDox

THGSox

ON

VDS

triodeD

ON

DSDS

THGSoxtriodeD

RR

VVLWC

RR

vVVLWC

VVLWC

R

dVdI

R

VVVVLWCI

−

−

→

−=

−=

−=

−−=

−=

≅

−−=

1

1 ith w1

1

1

1

2

0

)(

)(

µ

µ

µ

µ


Sampling Distortion

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45-120

-100

-80

-60

-40

-20

0

H1 = -49.4dBFS

H2 = -66.3dBFS

H3 = -105.2dBFS

DC = -43.4dBFS

A = -0.1dBFS

Frequency [ f / fs ]

Ampl

itude

[ d

BFS

]

N = 16384 SNR = 61.9dB SDR = 49.2dB SNDR = 47.4dB SFDR = 49.3dB

−=

−

−−THDD

inVV

vT

inout evv1

21 τ

T/τ = 10VDD – VTH = 2V VFS = 1V


Sampling Distortion

T/τ = 20VDD – VTH = 2V VFS = 1V

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45-120

-100

-80

-60

-40

-20

0

H1 = -69.5dBFS H2 = -76.3dBFS

H3 = -83.5dBFS

DC = -65.3dBFS

A = -0.0dBFS

Frequency [ f / fs ]

Ampl

itude

[ d

BFS

]

N = 16384 SNR = 62.0dB SDR = 68.6dB SNDR = 58.6dB SFDR = 69.5dB

• SFDR is very sensitive to sampling distortion

• Solutions:• Overdesign switches

increased switchcharge injectionincreased clock pwr

• Complementary switch• Large VDD/VFS

increased noise• Constant VGS ≠ f(Vin)

…



VDD = 1V


Constant VGS Sampling

• Switch overdrive voltage is independent of signal• Error from finite RON is linear (to first order)




Constant VGS Sampling Circuit

Supply

VDD = 3VVSS = 0V

Constant Vgs Switch

C11pF

C21pF

M110 / 0.35

M210 / 0.35

VDD

VP1100ns

Transient Analysisto 1.5us

M310 / 0.35

C31pF

M1210 / 0.35

M510 / 0.35

M410 / 0.35

M810 / 0.35

M910 / 0.35

M910 / 0.35

M610 / 0.35

M1110 / 0.35

M1110 / 0.35

M1110 / 0.35

M1110 / 0.35

VS11.5V1MHz

CH1pF

P

P


Clock MultiplierSupply

VDD = 3V

VSS = 0V

Clock Booster

C11pF

C21pF

M1

10 / 0.35

M2

10 / 0.35

VDD

VP1100ns

P

P_N

P_BoostP_Boost_N

Transient Analysisto 500ns

R1

1GOhm

R2

1GOhm


Constant VGS Sampler: Φ LOW

• Sampling switch M11 is OFF

• C3 charged to VDD

Constant Vgs Switch: P is LOW

VDD

M3

10 / 0.35

C3

1pF

M1210 / 0.35

M410 / 0.35

OFF

VS11.5V1MHz

CH1pF

~ 2 VDD(boosted clock)

VDD

VDD

VDD

OFF M11OFF


Constant VGS Sampler: Φ HIGH

• C3 previously charged to VDD

• M8 & M9 are on:C3 across G-S of M11

• M11 on with constant VGS = VDD

Constant Vgs Switch: P is HIGH

C31pF

M810 / 0.35

M910 / 0.35

M910 / 0.35

M1110 / 0.35

M1110 / 0.35

M1110 / 0.35

M1110 / 0.35

VS11.5V1MHz

CH1pF

VDD




Complete Circuit

Ref: A. Abo et al, “A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter,” JSSC May 1999, pp. 599.

Clock Multiplierfor M3

Switch

M7 & M13 for reliability



Body-effect causes residual dependence of Ron on Vin


Charge Injection

• “Extra” charge dumped onto holding capacitor• Cause:

– Cov charge sharing– Channel charge

• Problems:– Offset– Distortion (error charge is function of VIN)

• Solutions:– Dummy switches– Bottom-plate sampling


Worst-Case Error

• Error significant in many applications• Worst case: not all QCH goes onto C2• Signal dependent: QCH, VTH f(Vin)• Solution?

C2Vin

( )

( )

( ) mV426.031000

50.3510V

:Example

:error pedestalmax

:charge channel

22

=−××

=∆

−−==∆

=

−−=

THSSDDoxCH

SSin

THinDDoxCH

VVVC

WLCCQV

VV

VVVWLCQ


“Small Switch”

Reduced ∆V incase in τ: no optimum

( )

( )

( )( )

µ

µ

µτ

2

2

2

22

22

L

VVVC

WLC

VVVLWC

CFOM

VVVC

WLCCQV

VVLWC

CCR

THSSDDox

THSSDDox

THSSDDoxCH

THDDox

o

=

−−×−−

=

−−==∆

−==


Dummy Switch• Dummy switch is

half width• Depends on equal

charge split between source and drain

• Is split equal?

Ref: Bienstman et al, JSSC 12/1980, pp. 1051.

Eichenberger et al,JSSC 8/1989, pp. 1143.


Charge Injection Model

• On-state: MOSFET charge storage– Channel: – Overlap capacitance

• Turn-off:– Charge splits between C1 and C2

– Charge injected onto C2 corrupts signal– Error

Rs

C2C1

gVIN V1 V2

Vg

( )THINGoxCH VVVWLCQ −−≅

?2

2 =∆

INVCQ


Charge Injection Analysis

Ref: Wegmann et al, “Charge Injection in Analog MOS Switches,” IEEE J. Solid-State Circuits, pp. 1091, Dec. 1987.

B


Charge Injection AnalysisPartition parameter:

SPICE (BSIM 3v3):

( )

32132144 344 21

TFALLoxTHSSDD

oxFALLTHSSDD

tC

WLCV

VVV

CWLC

LtVVVB

ω

µ

××−−

=

−−=

2*

22

50%50%0.5

100%0%1

40%60%0 (default)

DrainSourceXPART


Minimizing Injection Error1. B >> 1: tFALL >> 1/ωT and C1 >> C2

• All charge injected onto C2 flows back onto C1 during “slow” turnoff • Impractical: slow and uselessly large C1

2. C1 = C2 and dummy switch (cf. Bienstmann)• Useless C1 (extra area and power)

3. B << 1: requires fast switching, only approximate

4. CMOS Switch• Partial cancellation for “some” Vin (when both XTR are on)• Depends on (poor) matching between NMOS and PMOS• Beware of PM AM conversion (jitter):

• Amount of injected charge depends on which switch turns of first• Better to depend on only on type switch turning off


Rejecting Injection Error

∆V = VOS + f(Vin)

VOS differential circuit

f(Vin) bottom plate = const. Vin sampling

Refs: R. C. Yen and P. R. Gray, "An MOS switched capacitor sampling differential instrumentation amplifier," IEEE International Solid-State Circuits Conference, vol. XXV, pp. 82 - 83, February 1982.

K. Lee and R. G. Meyer, "Low-distortion switched-capacitor filter design techniques," IEEE Journal of Solid-State Circuits, vol. 20, pp. 1103 - 1113, December 1985.


Bottom-Plate Sampling

• Switch Φ1a opens first– Injected charge is

constant, i.e. not f(Vin)– Removed by differential

implementation

• Switch Φ1b opens later– C2 disconnected

no charge injected

C2

Φ1b

Φ1a

Vin V2

time

on

off

time

on

off

Φ1b

Φ1a


MOS T&H

Ref: W. Yang, D. Kelly, I. Mehr, M. T. Sayuk, and L. Singer, "A 3-V 340mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR at Nyquist input," IEEE Journal of Solid-State Circuits, vol. 36, pp. 1931 - 1936, December 2001.

• G = 1

• Fmax = 1

• ∆Vicm at input of Gm


SC Gain Stage

Refs: R. C. Yen and P. R. Gray, "An MOS switched capacitor sampling differential instrumentation amplifier," IEEE International Solid-State Circuits Conference, vol. XXV, pp. 82 - 83, February 1982.

S. H. Lewis and P. R. Gray, "A pipelined 5-Msample/s 9-bit analog-to-digital converter," IEEE Journal of Solid-State Circuits, vol. 22, pp. 954 - 961, December 1987.

• G = Cs / Cf

• Fmax = 1 / (1+G)= 0.5 for G=1

• ∆Vicm remains on Cs


Jitter• All of the preceding analyses assume that sampling impulses are

spaced evenly in time• Actual clocks show some distribution around the nominal value T• The variability in T is called jitter • Typical clocks have >100ps+ jitter• Excellent (and expensive) clocks have <1ps jitter

Refs: T. H. Lee, K. S. Donnelly, J. T. C. Ho, J. Zerbe, M. G. Johnson, and T. Ishikawa, "A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM," IEEE Journal of Solid-State Circuits, vol. 29, pp. 1491 -1496, December 1994.

R. Farjad-Rad, W. Dally, H. Ng, R. Senthinathan, M. E. Lee, R. Rathi, and J. Poulton, "A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips," IEEE Journal of Solid-State Circuits, vol. 37, pp. 1804 - 1812, December 2002.


Jitter

• The dominant cause of clock jitter in most chips is power supply noise produced by unrelated activity in other parts of the chip

• The inverter symbol represents a chain of gates in the sampling clock path

Noisy VDD

JitterFree

Clock

JitteredOutputClock


Jitter

• Let’s assume the inverter delay is 100psec, and that the delay varies by 20% per volt change in VDD(20psec/V)

• 200mV of power supply noise becomes 4psec of clock jitter

Noisy VDD

JitterFree

Clock

JitteredOutputClock


Jitter

• Sampling jitter adds an error voltage proportional to the product of (tJ-t0) and the derivative of the input signal at the sampling instant

• Jitter doesn’t matter when sampling dc signals

nominalsampling

time t0

actualsampling

time tJ

x(t)

x’(t0)


Jitter

Error voltage (1st order):

nominalsampling

time t0

actualsampling

time tJ

x(t)

x’(t0)( ) ( )dttdxtte o

oj −=


Jitter EstimateSinusoidal input Worst case

( )( )

∆ttxte

AftxtfAftx

tfAtx

∆tfA

x

xx

x

x

)(')(

2)('2cos2)('

2sin)(

:Jitter :Frequency

:Amplitude

≤

≤

==

πππ

π

sB

BFS

sx

FS

f∆t

Ate

ff

AA

π21

22)(

2

1

<<

≅∆

<<

=

=

+

0.5 ps0.8 ps1.2 ps

10 MHz100 MHz

1000 MHz

16128

∆t << thanfsB

EECS 240 Lecture 18: Offset Cancellation B. Boser 1

Offset Cancellation Overview• Techniques:

– Correlated double sampling (CDS)– Chopper stabilization

• Reject offset and 1/f noise

• Alphabet soup– CDS: autozeroing, ping-pong opamp, self-calibrating opamp– Chopping: synchronous detection, dynamic element matching

• Reference– Ch. Enz and G. C. Temes, “Circuit Techniques for Reducing the Effects of

Op-Amp Imperfections,” Proc. IEEE, Nov. 1996, pp. 1584-1614.


Output Offset Cancellation

• Output still corrupted by switch charge injection

bottom plate sampling

• Requires

( )in

Cosinout

osC

AVVVVAV

AVV

=−−=

−=

:2 Phase

:1 Phase DDos VAV <


Multistage Implementation

R. Poujois and J. Borel, "A low drift fully integrated MOSFET operational amplifier," IEEE Journal of Solid-State Circuits, vol. 13, pp. 499 - 503, August 1978.


Results

µV5<osV

σ

Differential implementation also uses chopper stabilization.


Input Offset Cancellation

( )

( )

1

1

:(b) Phase

1

:(a) Phase

, +−=

+−=

+−=

+=−=

−−=

AVV

AVVAV

VVVAV

AAVVV

VVAV

osresos

osino

cosino

osoc

ooso


Multistage Cancellation

• Open switches left to right• Residual offset from S1 … SN-1 (charge injection?)

cancelled by final stage• Capacitive coupling reduces gain• Application: comparators


Offset Compensated SC Gain Stage

S1

S2

C1

S1

C2

S2 S1

S2ViVo

Vos

VC1

VC2


SC Gain Stage: Φ1

Assuming infinite open-loop gain.

S1C1

S1

C2

S1

S2ViVo

Vos

VC1

VC2

( ) osi

CCtot

osC

osiC

VCCVCVCVCQ

VVVVV

211

2211

2

1

1

+−=+=

−=−=

Φ


SC Gain Stage: Φ2

( )( )

io

tottot

ositot

osotot

osoC

osC

VCCV

QQ

VCCVCQ

VCCVCQ

VVVVV

2

1

211

212

2

1

12

1

2

=

→=

+−=

+−=

−=−=

ΦΦ

Φ

Φ

S2

C1

C2

S2

S2Vo

Vos

VC1

VC2

• Charge on C1, C2 is redistributed• Total charge stays same!• At end of phase 2:


SC Gain Stage Implementation

S1

S2

C1

S1

C2

S2 S1

S2ViVo

Vos

VC1

VC2

Cx

• Amplifier must be unity-gain stable

• Output pulled back to Vos in each cycle

• No feedback during clock non-overlapCx

• Charge injected at input node


Gain Compensated SC Stage

Clocks in parentheses are for inverting operation.


Gain Compensated SC Stage• C3 replaces unity-gain feedback reset • C3 charged to Vout during Φ2

• Output never reset (to zero)• Reduced slewing requirement• Reduced static error:

• Lowdown: works only for highly oversampled inputs!

22

12

1

11

1

ACCC

CVV

in

out

++

=


Gain Compensated SC Stage• Vos = 5 … 10mV• CMRR = 50dB• Distortion: 0.1 … 0.2%

• Is it worth it?

K. Martin, L. Ozcolak, Y. S. Lee, and G. C. Temes, "A differential switched-capacitor amplifier," IEEE Journal of Solid-State Circuits,Vol. 22, pp. 104 - 106, February 1987.


Offset Cancellation Comparison

• Offset cancellation options– At input– At output

(of first gain stage)– At input of auxiliary amp

M. Degrauwe, E. Vittoz, and I. Verbauwhede, "A micropower CMOS-instrumentation amplifier," IEEE Journal of Solid-State Circuits, vol. 20, pp. 805 - 807, June 1985.


Auxiliary Amplifier Offset Cancellation( ) ( )

( )

( )

++

+++

=

+−=

++

+++

=

−−==

−−−−=

444444 3444444 21

44 344 214434421

offset referredinput

21

22

2

2

1

2

2

111

222211

222

211

2

12

222112

ampaux

222

amp main

111

11

11

swOSswOS

OSOSout

swOSswOS

OSOSo

OSOSout

VAAV

AA

AA

AVVA

VAVAVAV

VVAAVV

AAV

VVAVAVV

VVAVVAV

2 node b, phase :1 node a, phase :

:Injection Charge Switch

2

1

sw

sw

VV Offset, charge injection attenuated if A1 >> A2


Aux Amp Options

M. Degrauwe, E. Vittoz, and I. Verbauwhede, "A micropower CMOS-instrumentation amplifier," IEEE Journal of Solid-State Circuits, vol. 20, pp. 805 - 807, June 1985.


Precision Gain Stage

H. Ohara, H. X. Ngo, M. J. Armstrong, C. F. Rahim, and P. R. Gray, "A CMOS programmable self-calibrating 13-bit eight-channel data acquisition peripheral," IEEE Journal of Solid-State Circuits, vol. 22, pp. 930 - 938, December 1987.


Amplifier with Auxiliary Input

• Offset: 300 µV


Gain Trimming


CDS and Flicker Noise

S1

S2A . S/H Σ

S2Vi Vo

V1 V2

V1/f

S1

S2

V1

V2

T = 1/fs

time[kT]


Flicker Noise Analysis

( ) ( ) ( )

( ) ( )

( )43421

4444 34444 21321

sH

Ts

fnieq

st

V

ffio

n

d

nieq

esVsV

e

TkTVkTVkTVAkTV

−=

→

−−+=

−

−

2/1

d

error referredinput

/1/1

signal

1

by tDelay

Transform Laplace

2


Flicker Noise Frequency Response

( )

2sin

2cos1

1

1

2

2

TjTe

esHTj

Ts

n

ωω

ω

+−=

−=

−=

−

−

( )

( )s

jsn

jsn

ffTsH

T

T

TTT

TTsH

2sin2

4sin2

4sin4

2cos12

2sin

2cos

2cos21

2sin

2cos1

2

1

22

222

πω

ω

ω

ωωω

ωω

ω

ω

==

=

−=

++−=

+

−=

→

→

444 3444 21


Flicker Noise SpectrumK 1:= fs 1:=

Sf f( )Kf

:= Hf f( ) 2 sinπ f⋅2 fs⋅

⋅:=

0 1 2 3 4 50

1

2

3

4

5

Hf f( )2

Sf f( ) Hf f( )2⋅

f

• Flicker noise is differentiated

• Essentially removed at low frequency

• Choosing fs/2 sufficiently large effectively removes flicker noise

• Noise above fs/2 folds to baseband

• Thermal noise folded to 0 … fs/2


Chopper Stabilization


Chopper Amp Bandwidth & DelayExample 1:

Amplifier is ideal LPF• Gain Ao• BW 2 fs

DC gain ~ 0.8 Ao

Example 2: Amplifier introduces 90o phase shift

DC gain is 0

( ) ( )[ ]( ) ( )[ ]yxyxyx

yxyxyx++−=

++−=

sinsincossincoscoscoscos

2121


Chopper Results

K. Hsieh, P. R. Gray, D. Senderowicz, and D. G. Messerschmitt, "A low-noise chopper-stabilized differential switched-capacitor filtering technique," IEEE Journal of Solid-State Circuits, vol. 16, pp. 708 - 715, December 1981.


• Offset: 0.5µV• Offset drift: 0.01µV/oC• Input noise: 1.5µVp-p DC … 10Hz 480nV/rt-Hz avg• Open-loop gain: 160dB• Slew rate: 4V/µS• Unity-gain bandwidth: 4MHz• PSRR: 125dB• CMRR: 120dB


Chopper Residual Offset

A. Bakker, K. Thiele, and J. H. Huijsing, "A CMOS nested-chopper instrumentation amplifier with 100-nV offset," IEEE Journal of Solid-State Circuits, vol. 35, pp. 1877 - 1883, December 2000.

Spikes from input chopper due to charge injection mismatch.


Nested Chopper Amplifier

• Inner chopper runs at high frequency to remove 1/f noise• Outer chopper runs at low frequency to minimize “spiking” and remove

residual offset from inner chopper. 1/f-noise is no issue since it has been reduced by inner chopper.


Results


ComparisonCDS

• Samples Signal– No continuous time operation

(except ping-pong)

• Flicker noise removed– No need for LPF

• Increased baseband noise due to thermal noise folding

• Can enhance amplifier gain

Chopper Stabilization

• Modulates Signal– Compatible with continuous

time operation

• Flicker noise to high frequency– Requires LPF to remove noise

• Virtually no thermal noise folding if fclk >> B

• Finite BW amp reduces gain

EECS240_Advanced Analog IC Boser

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