EECE579: Digital Design Flows

Usman Ahmed

Dept. of ECE

University of British Columbia

Implementing Digital Circuits

Custom

Standard CellsCompiled Cells

Macro Cells

Cell-based

Gate ArraysStructured ASICs

FPGA's

Array-based

Semicustom

Digital Circuit Implementation Approaches

Implementing Logic Circuits

HDLHDL

Logic SynthesisLogic Synthesis

FloorplanningFloorplanning

PlacementPlacement

RoutingRouting

Tape-out

Circuit ExtractionCircuit Extraction

Pre-Layout Simulation

Pre-Layout Simulation

Post-Layout Simulation

Post-Layout Simulation

StructuralStructural

PhysicalPhysical

BehavioralBehavioralDesign Capture

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Standard Cell Design

Functionalmodule(RAM,multiplier,…)

Routingchannel

Logic cellFeedthrough cell

Row

s o

f ce

lls

• Library of cells that implement different gates

• Cells can have different width but all cells have same height

(hence Standard Cells)

• Many variants of the same cell

Standard Cell Design

Functionalmodule(RAM,multiplier,…)

Routingchannel

Logic cellFeedthrough cell

Row

s o

f ce

lls

• Logic Synthesis

Transform the HDL description into library cells

• Placement

Where to place a cell ?

• Routing

Connect the placed cells.

Standard Cell Design

Functionalmodule(RAM,multiplier,…)

Routingchannel

Logic cellFeedthrough cell

Row

s o

f ce

lls

Optimizations:• Gate Resizing• Buffer Insertion• In-place Re-synthesis

Standard Cell Design: An Example

Standard Cell Design

Functionalmodule(RAM,multiplier,…)

Routingchannel

Logic cellFeedthrough cell

Row

s o

f ce

lls

• Routing channel can be narrowed if more interconnect layers are available

Standard Cell Design: New Generation

• Cell-structure hidden under interconnect layers

Standard Cell Design: Summary• Used only for the high-

speed or low-power applications

• Very expensive, and time consuming

• (> $2M just for the mask costs)

• Very high re-spin cost

FPGAs

• FPGA: Field-Programmable Gate Array

Circuit Description

Expensive Chip

Manufacturing

GateArray

What’s Inside an FPGA?

•

Logic Blocks

- used to implement

logic

- lookup tables and

flip-flops

Altera: LABs

Xilinx: CLBs

What’s Inside an FPGA?

•

I/O Blocks

- interface off-chip

- can usually support

many I/O Standards

What’s Inside an FPGA?

• Connection

Block

Logic Block

Sw itch Block

Routing Track(Horizontal)

Routing Channel(Vertical){

TILE

Basic Logic Gate: Lookup-Table

Function of each lookup table can be configured by shifting in bit-stream.

Logic Block:

• Inputs

Bit-S

tream

Logic Clusters

• D Q

D Q

D Q

Lo

cal I

nte

rco

nn

ect

Several lookup tables are grouped into “clusters”

- Typically 8 to 10 lookup

tables per cluster

Connections between lookup tables in the same cluster are fast

Connections between lookup tables in different clusters are slow

What’s Inside an FPGA?

• Connection

Block

Logic Block

Switch Block

Routing Track(Horizontal)

Routing Channel(Vertical){

Reconfigurable Logic:

Connect Logic Blocks using Fixed Metal Tracks and Programmable Switches

Reconfigurable Logic:

Connect Logic Blocks using Fixed Metal Tracks and Programmable Switches

Implementing Systems in an FPGA

High-speed I/O

Embedded PowerPCEmbedded memories

Hardwired multipliers

FPGA Fabric

Xilinx Vertex-II Pro

Advantages of FPGAs:• "Instant Manufacturability": reduces time to market• Cheaper for small volumes because you don’t need to pay for

fabrication• means you don’t need to be a big company to make a chip

• Relaxes Designers -> relaxed designers live longer!

Disadvantages of FPGAs:• Slower than custom or standard cell based chips• Cannot get as much circuitry on a single chip• Today: ~ 1M gates is the best you can do

~ 200 MHz is about as fast as you can get

• For large volumes, it can be more expensive than gate arrays and custom chips

Structured ASICs

• Combines good features of FPGAs and Standard Cell ASICs

All the layers are customized for a circuit- Standard Cell ASIC

Some layers are generalized while a few layers are customized for a circuit

- Structured ASIC

All the layers are generalized for any circuit- FPGA

Interconnect

Layers

Transistors

Logic Blocks

• Choices– Fine Grained

• Basic gates: NAND, NOR, XOR, FF etc.

– Medium Grained• Lookup Tables

– Coarse Grained• Multi-input, Multi-output blocks (e.g., PLAs)

• Configurability– SRAM cells– Vias

• Lower Level (e.g., between M1 and M2)

• Upper Level (Via stacks brought up to the configurable layers)

Routing Fabrics

• Metal and Via Programmable– More flexibility, more efficiency– Employed in most structured ASIC offerings

• Via Programmable– Regular, easy to manufacture– Metal is fixed and every segment may not be

fully utilizable, → Can be Inefficient

Design Flows

Design Flows

Design Flows

Design Flows

Design Flows

Implementing Logic Circuits

HDLHDL

Logic SynthesisLogic Synthesis

FloorplanningFloorplanning

PlacementPlacement

RoutingRouting

Tape-out

Circuit ExtractionCircuit Extraction

Pre-Layout Simulation

Pre-Layout Simulation

Post-Layout Simulation

Post-Layout Simulation

StructuralStructural

PhysicalPhysical

BehavioralBehavioralDesign Capture

D

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n Ite

ratio

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ratio

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