EECE476

Lecture 8: Altera ToolsFor Your Project

(no textbook)

The University ofBritish Columbia EECE 476 © 2005 Guy Lemieux

2

Altera Tools Overview

• Quartus II– simulates, compiles Verilog into gates– version 5.0 (web edition)

• Nios-II Development Kit– compiles C into NIOS code– version 5.0.1

• ModelSim– Verilog simulator– for advanced users– download from Altera

3

Important Notes about Tools

• Remember, this course is about Computer Architecture, not tools

• You need to learn these tools for your homework & project– You must display competency with tools during your project

demonstration– This shows you did the work yourself

• I will not test your knowledge of the tools on a test• I will not test your detailed knowledge of Verilog

• However:– You should be able to read and understand simple Verilog– You may have to write small amounts of (mostly correct) Verilog

4

Where Are They?• At school…

– Only PCs in MCLD402 have the tools installed– Lab is available when not booked for courses (eg: eece353, 379)

• At home…– Free licensing (web registration required during installation)

– Obtain the software• Bring a blank CD-R to MCLD402• Browse C:\ISO\ and double-click on the ISO image file.• This should launch NTI software and burn the image file on your CD-R.

– Note: do not copy the ISO file onto the CD-R, burn it directly as an image file.– If you do copy it, you can use http://www.daemon-tools.cc/dtcc/portal/portal.php

– Warning: the Altera Tools need a powerful computer• 1GB free disk, 512MB+ RAM, powerful CPU

5

Installing Altera ToolsObtain software on CD-R.

First, install Quartus II software.1. Insert your burned CD-R into your computer.2. If it autorun starts an install program, press EXIT.3. Browse the CD-R drive, run ‘quartusii_50_sp1_web_edition_single.exe’4. Follow detailed installation instructions on course web site. Note special

instructions on disabling software firewalls, etc. (Don’t skip this step!)http://www.ece.ubc.ca/~elec476/altera/

Second, install NIOS-II software.1. Browse the CD-R drive, run ‘Launcher.exe’2. Choose ‘Install Altera NIOS II Development Kit’3. Accept all default options

6

Altera Quartus II

Flow:1. Create a “new project”

2. Add Verilog code to the project

3. Edit your Verilog code

4. Compile it

5. Simulate it

6. Debug it

7. Go to step 3

7

Quartus: New Project

• File New Project Wizard– Next– Choose a working directory

• Name your project (eg, my_xor)• Name your top-level design file (eg, my_xor)

– Add design files: eg, my_xor.v– Press Next a few times

• Choose ‘Cyclone’ device family• Choose ‘7’ as the speed grade, then select ‘1C20F400C7’

– Finish

8

Verilog Example: XOR Gate

module my_xor( C, A, B );

output C;

input A, B;

assign C = (A ^ B);

endmodule

Convention: Outputs come first in the “parameter list”

Operation Operator

~ Bitwise NOT

& Bitwise AND

| Bitwise OR

^ Bitwise XOR

9

Quartus: Initial Settings

• File New.. .Verilog HDL File– Copy my_xor contents, save as my_xor.v

• File New …– Other Files …– Vector Waveform File– Save as ‘my_xor.vwf’

10

Quartus: Compile & Simulate Your Design

• Processing Start Compilation– (wait a while)

• Open my_xor.vwf– Right-click in the ‘Name’ column (white area)– Insert Node or Bus…

• Node Finder…– Press List button– Under ‘Nodes Found’, choose inputs ‘A’ and ‘B’– Press ‘>’ button to move them to ‘Selected nodes’– Press OK

• Press OK– You now have two input waveforms

• Try to change their value (select region, right-click or press buttons)– Save

• Processing Start Simulation– (wait a bit)

11

Quartus: Timing Waveforms

12

Quartus: Timing Waveforms

output glitch

inputs

gate delay(~8ns here)

13

Quartus: Faster Compile & Simulation – Using Functional Mode

• By default, Quartus compiles into gates– Slow mapping process– Often, only want “function”, not precise gate-level timing– “Functional simulation” runs faster

• Also removes gate delay and glitching

• Processing Generate Functional Simulation Netlist

• Assignments Settings…– Select Simulator– Simulation mode: Functional

• As your project grows…– may have to switch to Timing, recompile, then back to Functional

14

Quartus: Functional Waveforms

Looks perfect!

15

Altera Nios IINIOS Development Kit (NDK)

• Four key components:– NIOS II IDE

• Integrated Development Environment for Windows, GUI-based programming environment• Based on Eclipse http://www.eclipse.org• Start Programs Altera Kits NIOS II DevKit Nios II IDE

– Cygwin http://www.cygwin.com• “Linux” layer on top of Windows• Start Programs Altera Kits NIOS II DevKit Nios II SDK Shell

– GNU C Compiler Tools ‘gcc’ http://gcc.gnu.org• A popular, free C compiler that targets many different CPUs• Integrated into the IDE

– Documentation• Start Programs Altera Kits NIOS II DevKit NIOS II Documentation• Click ‘full documentation’ under item 4.• Click ‘The Nios II Processor Reference Handbook’

• These are already installed as part of the NDK!

16

About NIOS II Licensing…

• Purpose of NIOS– The NIOS CPU is an embedded CPU– Altera’s business is to sell hardware

• Sell you a big FPGA: NIOS + logic for rest of system– Altera documentation

• Describes how to build a NIOS computer system on an FPGA• Includes a “reference design” for an entire NIOS II computer system• This is not really useful to you• The NIOS CPU itself is encrypted, you cannot view or modify it

• Licensing– The NIOS software tools are “free”– BUT, you don’t have a license to use Altera’s encrypted CPU

netlist (SoPC builder)• Don’t use it. It won’t really help you in this course.

17

NIOS IDE: New Project

• File New Project…– Altera NIOS II, C/C++ Application, Next– Select Project Template: Dhrystone– Select Target Hardware: Browse…

C:\Altera\nios2\examples\verilog\niosii_cyclone_1c20\full_featured\full_1c20.ptf

– Next/Finish

– …wait a bit…

18

NIOS IDE: Compile & Run

• Project Build All– (wait a little while… the first time is slow!)

• Run Run As NIOS2-ISS (Instruction Set Simulator)

or• Run Debug As NIOS2-ISS

• Slick GUI...– You can play, but this tool won’t help your project much– Command-line tools are what you really need

19

NIOS Cygwin

• What is it?– Unix command-line shell under windows– Unix utilities: ls, less, grep, sed, awk, etc…

• You’ll need to ‘brush up’ on your Unix

• Why?– Can use gcc to compile C to NIOS code– Can assemble/disassemble NIOS code– Use it to write test cases for your CPU

• Writing NIOS programs in binary is painful!• Let the tools help you

20

GCC and Objdump

Compiling and Disassembling:

% nios2-elf-gcc –O –c dhrystone.ccompiles program, optimizes code, writes object file dhrystone.o

% nios2-elf-objdump –S dhrystone.o disassembles object file (or executable file) to screen (stdout)shows instructions, labels, memory addresses, and binary machine code

Compiling to Assembly and Assembling:

% nios2-elf-gcc –O –S dhrystone.ccompiles program, optimizes code, writes assembly file dhrystone.sshows labels and instructions only (no addresses or binary code)

% nios2-elf-gcc –c dhrystone.sassembles program, writes object file dhrystone.o

21

Sample NIOS Assemblyint main(){ int a = 1; int b = 1; int c; int i;

for( i=2; i <= 100; i++ ) { c = a + b; a = b; b = c; }

return c;}

Run these commands:% nios2-elf-gcc –O2 –S fib.c% cat fib.s

Output is shown in next column.

% nios2-elf-gcc –c fib.s

.file "fib.c" .section .text .align 3 .global main .type main, @functionmain: addi sp, sp, -8 movi r4, 1 stw fp, 4(sp) mov r5, r4 mov fp, sp movi r3, 98.L6: add r2, r5, r4 addi r3, r3, -1 mov r5, r4 mov r4, r2 bge r3, zero, .L6

ldw fp, 4(sp) addi sp, sp, 8 ret .size main, .-main .ident "GCC: (GNU) 3.3.3 (Altera Nios II 1.0 b316)"

Assembly CodeC Code

22

Sample NIOS Disassemblyint main(){ int a = 1; int b = 1; int c; int i;

for( i=2; i <= 100; i++ ) { c = a + b; a = b; b = c; }

return c;}

Run these commands:% nios2-elf-gcc –O2 –c fib.c% nios2-elf-objdump –S fib.o

Output is shown in next column.

fib.o: file format elf32-littlenios2

Disassembly of section .text:

00000000 <main>: 0: defffe04 addi sp,sp,-8 4: 01000044 movi r4,1 8: df000115 stw fp,4(sp) c: 200b883a mov r5,r4 10: d839883a mov fp,sp

14: 00c01884 movi r3,98

18: 2905883a add r2,r5,r4 1c: 18ffffc4 addi r3,r3,-1 20: 200b883a mov r5,r4 24: 1009883a mov r4,r2 28: 183ffb0e bge r3,zero,18 <main+0x18>

2c: df000117 ldw fp,4(sp) 30: dec00204 addi sp,sp,8 34: f800283a ret

Disassembled CodeC Code

23

Writing your own NIOS Programs

• Software flow for writing NIOS test programs

– Write in C% vi foo.c

– Compile into assembly% nios2-elf-gcc –O –S foo.c

– Modify assembly code (eg, remove unsupported instructions)% vi foo.s

– Assemble% nios2-elf-gcc –c foo.s

– Disassemble% nios2-elf-objdump –S foo.o > foo.txt

– Extract binary machine code% vi foo.txt