EE695K: Modeling and Optimization of High Performance ...chengkok/ee695K/lecture1.pdf · Office...

EE695K VLSI Interconnect

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EE695K: Modeling and Optimizationof High Performance Interconnect

Instructor: Cheng-Kok KohEmail: [email protected]: MSEE 220Telephone: 496-3683Office Hours: Wed, Fri: 10:30 - 12 am

or by appointments

Grading Policy

• Homework 20%• Mid-Term Exam 30%• Project 50%• Your final grade will depend on the total of the

three components• You get an A if your score ≥ 90.• Students caught engaging in an academically

dishonest practice will receive a failing grade forthe course. University policy on academicdishonesty will be followed strictly.


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Course Requirements

• Unofficial Prerequisites– EE559 MOS VLSI Design– EE608 Computational Models and Methods

• They will help your appreciation of the materials inthis course

References

• Circuits, Interconnects, and Packaging for VLSI,H. Bakoglu, Addison Wesley

• Cong et al., Performance Optimization of VLSIInterconnect Layout, Integration, the VLSI Journal 21(1996) 1--94.

• Selected research papers from TCAD, TVLSI, andmajor CAD conferences such as DAC and ICCAD

• Digital Integrated Circuits: A Design Perspective,J. Rabaey, Prentice Hall

• Principles of CMOS VLSI Design: A SystemsPerspective, 2nd Ed.,N. H. E. Weste and K. Eshraghian, Addison Wesley


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Related VLSI CAD Conferences and Journals

• ACM IEEE Design Automation Conference (DAC)• International Conference on Computer Aided Design(ICCAD)• IEEE International Symposium on Circuits and Systems

(ISCAS)• Design, Automation and Test in Europe (DATE)• Asia and South Pacific Design Automation Conference (ASP-

DAC)• IEEE Transactions on CAD of Circuits and systems (T-CAD)• ACM Trans. on Design Automation of Electronic Systems

(TODAES)• Integration: The VLSI Journal• IEEE Transactions on Circuits and Systems (T-CAS)• IEEE Trans. on VLSI Systems (T-VLSI)

Course Outline

• Lecture 1: Overview and Introduction: Trends of VLSIInterconnect, Challenges of Interconnect Design

• Lecture 2: Modeling of VLSI Interconnects: Interconnectas R(L)C Tree/Networks, Elmore Delay Model,Moment Computation, Asymptotic Waveform,Evaluation, Pade Via Lanczos, Pole Analysis,Transmission Line

• Lecture 3: Modeling of VLSI Devices• Lecture 4*: Parasitic Extraction• Lecture 5: Timing-Driven Placement: Delay

budgeting, Net-based timing-driven placement, Path-based Timing-Driven Placement

• Lecture 6: Device Optimization: Device Sizing, BufferInsertion, Transistor Ordering


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Course Outline (Continued)

• Lecture 7: Interconnect Topology Optimization: forWirelength Minimization, for Pathlength Minimization,for Delay Minimization

• Lecture 8: Interconnect Sizing: Local RefinementBased, Dynamic Programming-Based, SensitivityBased, Mathematical Programming, TerminizationOptimization

• Lecture 9: Simultaneous Topology Optimization, BufferInsertion, Buffer and Wire Sizing

• Lecture 10: Clock Network Design: Zero-Skew,Bounded-Skew, Buffer and Wire Optimization, Non-Tree routing, Clock Schedule

• Lecture 11*: Noise Modeling, Control, and Avoidance

Class Project

• Develop a CAD tool to perform repeater planningduring floorplanning

• C++ is the preferred programming language• Grading policy for class project:

– 40% based on presentation (to be held in the last week ofclass)

– 60% based on write-up (to be turned in on the last day ofsemester)

• Like a conference submission• Evaluation will be based on technical merits, clarity of

presentation


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Overview

• Moore’s Law• CMOS scaling theory• Interconnect performance implied by NTRS’97• Need for a new design paradigm

Pad Metal1 Via Metal2

I/OData Path

ROM/

RAM

PLA

A/DConverter

Randomlogic

Basic Components In VLSI Circuits

• Devices– Transistors– Logic gates and cells– Function blocks

• Interconnects– Local signals– Global signals– Clock signals– Power/ground busses


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Storageelement

CombinationalLogic

Clock Period ≥ td-gates + td-interconnects + tskew + tsu + tds

td-gates = gate delay in comb. logic

td-interconnects = interconnect delay in comb. logic

tskew = clock skew

tsu = set-up time

tds = delay within storage elements

Interconnectdelay

Determining Factors of System Performance

Single-Phase Edge-Triggered Clocking

• Storage elements: edge-triggered flip-flops, edge-triggered TSPC registers

CLR1 R2D1 Q1 D2 Q2

pFFt

CLKCLKskew ttt −= '

setupt

intdevicelogic ttt +=

CLK 'CLK


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Maximum Clock Frequency

skewsetuplogicpFFcycle ttttT −++> max,max,max,min,

skewtD2

Q1

D1

CLK

CLK’

cycleT

setupt

setupt holdt

logict

Make tskew positive to increase clock frequencyMinimum clock period determined by maximum delay between latches

pFFt

Capturing the Correct Data

skewlogicpFFhold tttt −+< min,min,max,

skewtD2

previous state

Q1

D1

CLK

CLK’

cycleT

setupt

setupt holdt

logict

pFFt

holdt

Maximum positive clock skew determined by minimum delay between latches

max,holdwidthclk tt >−

(to avoid race conditions)

(to guarantee data is captured)


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Interconnect-Driven Design

Importance of VLSI Interconnect Design

• Technology Trends:– Deep sub-micron design: < 0.25-0.18 micron CMOS

technology– High-Speed: 500 MHz to 1 GHz

• Impact on VLSI System Design– Interconnect delay becomes the dominating factor in system

performance• Consumes 50%-70% clock cycle

– Distributed nature of interconnects becomes significant• Becomes distributed RCL circuits or lossy transmission lines.

Moore’s Law

• The min. transistor feature size decreases by 0.7Xevery three years (Electronics Magazine, Vol. 38,April 1965)

• True in the past 30 years!


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Evolution in Complexity

Evolution in Transistor Count


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Evolution in Performance

National Technology Roadmap forSemiconductor (NTRS’97)

Technology (um) 0.25 0.18 0.15 0.13 0.10 0.07Year 1997 1999 2001 2003 2006 2009

# transistors 11M 21M 40M 76M 200M 520MOn-Chip Clock (MHz) 750 1200 1400 1600 2000 2500

Area (mm2) 300 340 385 430 520 620Wiring Levels 6 6-7 7 7 7-8 8-9


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Parameter Scaling FactorDimensions (W, L, tgox, Xj) 1/S

Substrate doping (NSUB) SVoltages (VDD, VTN, VTP) 1/S

1/S

1/S

1

1/SPower-dissipation per gate (P=IV) 1/S2

1/S3

Area per device (A=WL) 1/S2

Power-dissipation density (P/A) 1

))V(Vte

LW

(I deviceper Current 2TDD

gox

oxDS −∝

))V(VtWLe(C ecapacitanc Gate 2

TDDgox

oxg −=

)IV

(R resistance-on TransistorDS

DDtr ∝

)CRI

VC(t delay date Intrinsic gtr

av

g =∆=

t )(P gateper product delay-Power ×

Parameter Scaling FactorDimensions (W, L, tgox, Xj) 1/S

Substrate doping (NSUB) SVoltages (VDD, VTN, VTP) 1/S

1/S

1/S

1

1/SPower-dissipation per gate (P=IV) 1/S2

1/S3

Area per device (A=WL) 1/S2

Power-dissipation density (P/A) 1

))V(Vte

LW

(I deviceper Current 2TDD

gox

oxDS −∝

))V(VtWLe(C ecapacitanc Gate 2

TDDgox

oxg −=

)IV

(R resistance-on TransistorDS

DDtr ∝

)CRI

VC(t delay date Intrinsic gtr

av

g =∆=

t )(P gateper product delay-Power ×

Scaling of MOS Transistor

Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET).The main dimensions that determine device properties are gate oxide thickness

tgox; gate length L, gate width W; and junction depth Xj

Leff

W

S D

toxXj

G

B

Ideal Scaling of MOS Transistors

• All horizontal & vertical dimensions of a transistor (W,L, tox, Xj) are reduced by S

• All voltages (VDD, VTN, VTP) are reduced by S• Substrate doping (Nsub) is increased by S


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( )[ ]( )

−−−−≤−−

≤=

tngsdstngsn

tngsdsosostngsn

tngs

ds

VVVVVßVVV/VVVVß

VVI

2

2

)2/(2

0 (Cut-off)

(Linear in terms of VGS)

(Saturation, independent of VDS)

LW

Cµß oxnn ⋅⋅=Gain Factor

ox

ox

teelectron mobility

Current Through an NMOS Transistor

Geometry of transistor

Technology Scaling Models

• Full Scaling (Constant Electrical Field)– Ideal Model: dimensions and voltages scale togather by the

same factor S

• Fixed Voltage Scaling– Most common model until recently: only dimensions scale,

voltages remain constant

• General Scaling– Most realistic for today’s situation: voltages and dimensions

scale with different factors


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Scaling Relationships for Long channel Devices

Scaling of Short Channel Devices


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Propagation Delay Scaling

20p

50p

100p

200p

500p

1n

0.5 1.0 5.0 10.0

Channel Length : Left (µm)

Gat

e D

elay

: τD

d(se

c/st

age)

F/O = 1R.T. Operation

Present ResultsReported Results

Ref.[4]3.5V

Ref.[5]3.5V

3.3V2.5VRef.[7]

2.5V

VDDScaling

VDD=5V

10p0.1

Basic interconnection parameters

Lint

Wsp Wint

HintTox

Ideal Scaling of VLSI Interconnects

• Cross Sectional dimensions ( Wint, Hint, Wsp, Tox) arereduced by S

• Die Size and global interconnection lengths areincreased by Sc


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(Fringing and mutual capacitances are neglected)

Parameter Scaling FactorCross sectional Dimensions (W int , H int , W sp, t ox) 1/S

S2

1

RC constant per unit length (R int C int ) S2

Local interconnection RC delay (l loc) 1/S

1Die size (D C) SC

Global interconnection length (l int ) SC

S2(SC)2

Transistor line time of flight (l int /v c) SC

)HW1

?(Rintint

intint = lengthunit per Resistance

)lC(R 2locintint delay RC ctioninterconne Local

)t

W(C

ox

intoxint ε= lengthunit per eCapacitanc

)lC(R 2intintint delay RC ctioninterconne Global

Parameter Scaling FactorCross sectional Dimensions (W int , H int , W sp, t ox) 1/S

S2

1

RC constant per unit length (R int C int ) S2

Local interconnection RC delay (l loc) 1/S

1Die size (D C) SC

Global interconnection length (l int ) SC

S2(SC)2

Transistor line time of flight (l int /v c) SC

)HW1

?(Rintint

intint = lengthunit per Resistance

)lC(R 2locintint delay RC ctioninterconne Local

)t

W(C

ox

intoxint ε= lengthunit per eCapacitanc

)lC(R 2intintint delay RC ctioninterconne Global

Scaling of Local and Global Interconnections

Ideal Qussi-Ideal Constant-R GeneralizedScaling Scaling Scaling Scaling

Thickness (Hint) 1/S 1/SH

Width (Wint) 1/S 1/S 1/SW

Separation (Wsp) 1/S 1/S 1/Ssp

Insulator thickness (tox) 1/S 1/Sox

Length (lloc) 1/S 1/S 1/S

Resistance (Rint) S 1 SWSH/S

Capacitance to substrate 1/S 1/S3/2 Sox/SSW

Capacitance between lines 1/S Ssp/SSH

RC delay (T) 1Voltage drop (IR) 1 1/S SWSH/S2

Current density (J) S 1 SWSH/S

Parameter

S1/

2HW /SSS≈

1/S≈

1/S≈1/S≈1/S≈

S1/S1/S1/

S1/S1/

S1/

S1/S

S

S1/≈

Ideal Qussi-Ideal Constant-R GeneralizedScaling Scaling Scaling Scaling

Thickness (Hint) 1/S 1/SH

Width (Wint) 1/S 1/S 1/SW

Separation (Wsp) 1/S 1/S 1/Ssp

Insulator thickness (tox) 1/S 1/Sox

Length (lloc) 1/S 1/S 1/S

Resistance (Rint) S 1 SWSH/S

Capacitance to substrate 1/S 1/S3/2 Sox/SSW

Capacitance between lines 1/S Ssp/SSH

RC delay (T) 1Voltage drop (IR) 1 1/S SWSH/S2

Current density (J) S 1 SWSH/S

Parameter

S1/

2HW /SSS≈

1/S≈

1/S≈1/S≈1/S≈

S1/S1/S1/

S1/S1/

S1/

S1/S

S

S1/≈

not good for packing density

Local Interconnects under Different Scaling Rules


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Ideal Constant Constant GeneralizedScaling Dimension Delay Scaling

Thickness (Hint) 1/S 1 SC 1/SH

Width (Wint) 1/S 1 SC 1/SW

Separation (Wsp) 1/S 1 SC 1/Ssp

Insulator thickness (tox) 1/S 1 SC 1/Sox

Length (lloc) SC SC SC SC

Resistance (Rint) S2SC SC 1/SC SWSHSC

Capacitance (Cint) SC SC SC

RC delay (T) S2(SC)2 (SC)2 1 SWSH(SC)2

Parameter

2≈

CS≈

1/S≈

Ideal Constant Constant GeneralizedScaling Dimension Delay Scaling

Thickness (Hint) 1/S 1 SC 1/SH

Width (Wint) 1/S 1 SC 1/SW

Separation (Wsp) 1/S 1 SC 1/Ssp

Insulator thickness (tox) 1/S 1 SC 1/Sox

Length (lloc) SC SC SC SC

Resistance (Rint) S2SC SC 1/SC SWSHSC

Capacitance (Cint) SC SC SC

RC delay (T) S2(SC)2 (SC)2 1 SWSH(SC)2

Parameter

2≈

CS≈

1/S≈S: Scaling factor for device dimensions.Sc:Scaling factor for chip size

Global Interconnects under Different Scaling Rules

Interconnection time delay and average gate delay versus yearof fabrication for the state-of-art chip fabricated that year.

1970 1980 1990Year

10-7

10-8

10-9

10-10

10-11

DE

LAY

TIM

E (s

ec)

POLY

- Si (

500µ

Ωcm)

W S

i 2 (3

0)W

(10)

Al (3

)

τG

τI

Delay versus Year of Fabrication


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Technology (um) 0.25 0.18 0.15 0.13 0.10 0.07

Res. ρ (uΩ /cm) 3.3 2.2 2.2 2.2 2.2 1.8

Dielectric constant 3.55 2.75 2.25 1.75 1.75 1.5

Min. wire width 0.25 0.18 0.15 0.13 0.10 0.07

Min. wire spacing 0.34 0.24 0.21 0.17 0.14 0.10

Metal aspect ratio 1.8:1 1.8:1 2.0:1 2.1:1 2.4:1 2.7:1

Via aspect ratio 2.2:1 2.2:1 2.4:1 2.5:1 2.7:1 2.9:1

Vdd (V) 2.15 1.65 1.35 1.35 1.05 0.75

Interconnect Parameters from NTRS’97

Cf Ca

Cx

Capacitance Computation

• Capacitance extraction using a 3D field solver(FastCap)


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Derived Interconnect & Device Parameters

Technology (um) 0.25 0.18 0.15 0.13 0.10 0.07

Ca (aF/um) 29.0 21.2 16.2 12.0 14.4 8.56

Cf (aF/um) 41.8 30.2 24.8 18.3 14.1 14.8

2X min.

width &

spacing Cx(aF/um) 71.0 58.3 49.4 42.8 45.3 41.6

Ca (aF/um) 73.5 53.6 40.6 30.0 26.6 19.5

Cf (aF/um) 63.5 47.3 38.4 28.5 28.2 23.6

5X min.

width &

spacing Cx(aF/um) 18.3 16.9 15.4 14.8 16.5 16.7

0.17 0.12 0.11 0.085 0.070 0.042

1.71 1.86 2.26 2.25 2.39 2.42

Buffer input cap. (fF)

Buffer Rd (x10KΩ )

Buffer intrin. delay (ps) 70.5 51.1 48.7 45.8 39.2 21.9

Impact of Interconnect Optimization on FutureTechnology Generations

0.01

0.1

1

10

0.25 0.18 0.15 0.13 0.1 0.07Technology (u m)

Del

ay (n

s)

1mm

2cm DS

2cm BIS

2cm BISWS

Intrinsic gatedelay


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Impact of Interconnect Optimization on FutureTechnology Generations

Technology (um) 0.25 0.18 0.15 0.13 0.10 0.071mm (ns) 0.059 0.049 0.051 0.044 0.052 0.0422cm DS (ns) 2.589 2.48 2.65 2.62 3.73 4.672cm BIS (ns) 1.779 1.55 1.59 1.51 1.74 1.552cm BISWS (ns) 0.895 0.793 0.77 0.7 0.77 0.672

Significance of Coupling Capacitance

0

0.2

0.4

0.6

0.8

1

0.25 0.18 0.15 0.13 0.1 0.07

Technology Generation (um)

Cx/Ctotal

Min. Spacing

2x Min. Spacing


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Coupling Noise

0

0.1

0.2

0.3

0.4

0.25 0.18 0.15 0.13 0.1 0.07

Technology (u m)

Lmax (mm)

10% Vdd min. Spacing

10% Vdd 2x min. Spacing

0.000

0.050

0.100

0.150

0.200

0.250

0.300

0.350

250 180 150 100 70

Technology (nm)

Noi

se (%

Vdd

) a pair of in-phase aggressors

one aggressor

a pair of skewed

Coupling Noise

• Coupling noise from two adjacent aggressors to themiddle victim wire with 2x min. spacing. Rise time is10% of project clock period.

• Coupling noise depends strongly on both spatial andtemporal relations!


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Interconnect Complexity

Technology (um) 0.25 0.18 0.13 0.10 0.07Length (m) 820 1,480 2,840 5,140 10,000

Wiring Levels 6 6-7 7 7-8 8-9Opt. # buffers per net few many

Opt. # wiresizes per net few manyOpt. # buffers per chip 5K 25K 54K 230K 797K

• Performance

• Signal reliability

• Electromigration

Distributions of Wire lengths

1E+00

1E+01

1E+02

1E+03

1E+04

1E+05

1E+06

1E+07

0 10 20 30Length (mm)

Num

ber

of In

terc

onne

cts

0.07 um tech.

0.25 um tech.

Rent's exponent = 0.6Rent's coefficient = 4.0Avg. fanout = 3


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Implications

• Communication is more expensive than computation• Interconnect performance has become the bottleneck

of the overall circuit/system performance• Interconnect modeling and optimization has become

very difficult due to the distributed nature ofinterconnects and their spatial and temporalinteractions

• A new design paradigm/flow is needed to handleinterconnect-dominated designs in the future

System Specification

Functional Design

Logic Design

Circuit Design

X=(AB*CD)+(A+D)+(A(B+C))

Y=(A(B+C))+AC+D+A(BC+D))

VLSI Design Cycle


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Physical Design

Fabrication

Packaging

VLSI Design Cycle (continued)

Transistors/Cells

Interconnection

Interconnection

Transistors/Cells

Conventional Approach New Approach

Interconnect-Driven Design

Need a New Paradigm for VLSI Design


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Program

Data

Data/Object

Program

Conventional Approach New Approach

Data Base Design

Object-oriented design

Paradigm Change in Software Design

Summary

• Technology scaling according to Moore’s Law hasbeen the driving force behind the exponential growthof the semiconductor industry

• Interconnect (esp. global interconnect) performancehas become the bottleneck of the overall systemperformance

• Interconnect modeling and optimization has becomevery important, yet difficult

• A new design paradigm is needed for interconnect-driven (or interconnect-centric) design

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