EE5324 VLSI Design II - Samex...
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![Page 1: EE5324 VLSI Design II - Samex Entaboutme.samexent.com/classes/spring09/ee5324/lecture/Lect_01_Intro...2 3 Action Required • Make sure your CAD tools are setup properly – Tutorial](https://reader033.fdocuments.in/reader033/viewer/2022051723/5ab7f60f7f8b9ac10d8c6371/html5/thumbnails/1.jpg)
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EE5324
VLSI Design II
Professor Chris H. Kim
University of MinnesotaDept. of ECE
www.umn.edu/~chriskim/ [email protected]
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Practical Information• Class webpage
– http://www.ece.umn.edu/class/ee5324
• Instructor: Chris Kim– Office: EE/CSci 4-161, Email: [email protected]
– Ph: (612) 625 2346
– Office hrs: M 11am–noon, or by appointment
• TA: Wei Zhang– Email: [email protected]
– Ph: (612) 626 0834
– Office hrs: W 11am-noon, or by appointment
(EE/CSci 4-168)
• UNITE videos– http://www.myu.umn.edu/
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Action Required
• Make sure your CAD tools are setup properly
– Tutorial on class website
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Course Overview
• Targeted for students who have already taken EE5323 or an equivalent class
• Focus this year will be on circuit design, device issues, and implementation of functional units (memories and arithmetic units)
• Real world challenges and solutions for designing high-performance and low-power circuits
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Prerequisites• EE 5323 VLSI Design I or equivalent
– MOS transistor
– Static, dynamic logic, pass transistor logic
– Sequential logic
• Familiarity with VLSI CAD tools
– Cadence: LVS, DRC, Extract
– HSPICE, Cosmoscope
• Basic knowledge on CMOS device operation
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Class Materials• J. Rabaey, A. Chandrakasan, B. Nikolic, Digital
Integrated Circuits: A Design Perspective, Prentice Hall, 2nd edition, 2003.
• Lecture notes– Check the class webpage on a regular basis
• Other references– Y. Taur, T. Ning, Fundamentals of Modern VLSI Devices,
Cambridge University Press, 2002.
– A. Chandrakasan, W. Bowhill, F. Fox, Design of High-Performance Microprocessor Circuits, IEEE Press, 2001.
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Other References• Conferences
– International Solid-State Circuits Conference (ISSCC, slides posted on IEEExplore)
– Symposium on VLSI Circuits (VLSI)
– Custom Integrated Circuits Conference (CICC)
– Off campus access to IEEExplore: www.lib.umn.edu/cgi-bin/ieee.cgi
• Journal– IEEE Journal of Solid-State Circuits (JSSC)
– IEEE Trans. On VLSI Systems (TVLSI)
– Intel Technology Journal
– IBM Journal on R & D
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Grading Policy• Assignments (20%)
– ~4 homeworks
– 20 min paper review (2 person team)
• Midterm exam (25%)– In class, open book, open notes, calculators
permitted
• Final exam (30%)– Open book, open notes, calculators permitted
• Term-long project (25%)– 2k-bit SRAM design
– Optimize for area, stability, speed, and power consumption
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CAD Tools• Cadence
– Schematic editor, layout editor, DRC, LVS, EXT
• HSPICE, cosmoscope
• Technology files
– FreePDK 32nm
• You need to be familiar with the tools in order to execute the term project
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Term Project• Two-person project
– Email me if you need a partner
• 2k-bit (128x16b) SRAM design
– Full custom
– LVS, DRC clean
– Design parameters: area, stability, speed, and power consumption (leakage and active)
– Simulations using predictive 32nm technology model
– Literature survey, search for SRAM design references
– Prepare to spend long hours on schematic and layout
• Interim, final report, final presentation
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Class Policies
• Students caught engaging in an academically dishonest practice will receive a failing grade for the course.
• University policy on academic dishonesty will be followed strictly.
– www.osai.umn.edu/syllabus.html
• No late homework/project
• No extra work will be accepted for improving the final grade
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Course Topics• Scaling issues, CMOS (2-3 weeks)
• Memories: ROM, RAM (2-3 weeks)
• Arithmetic units: Adder, multiplier (1-2 weeks)
• High performance design (1-2 weeks)– High performance logic family, clocking strategies,
interconnects
• Low power design (2-3 weeks)– Low voltage designs, leakage control techniques,
circuit/device/technology issues, memory
• Variation tolerant design (1-2 weeks)– PVT compensating techniques
• Power and clock distribution, interconnect, reliability (1-2 weeks)
• Bulk and SOI
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Moore’s Law
� Intel founder and chairman Gordon Moore predicted in 1965 that the number of transistors on a chip will double every 18-24 months
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Transistor Scaling
� Constant E-field scaling: voltage and dimensions (both horizontal and vertical) are scaled by the same factor k, (~1.4), such that the electrical field remains unchanged.
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Scaling in the Vertical Dimension
• Transistor Vt rolls off as the channel length is reduced
• Shallow junction depth reduces Vt roll-off
• However, series resistance increases
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Scaling in the Vertical Dimension
• Vertical dimension scales less than horizontal
• Aggravates short channel effect (Vt roll-off)
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Constant Field ScalingDevice and circuit parameters Factor
Scaling assumptions
Device dimensions (tox, L, W, Xj)
Doping concentration (Na, Nd)
Voltage (V)
1/k
k
1/k
Device parameters
Electric field (E)
Capacitance (C=εA/t)
Current (I)
Channel resistance (Rch)
1
1/k
1/k
1
Circuit parameters
Delay (CV/I)
Power (VI)
Switching energy (CV2)
Circuit density (1/A)
Power density (P/A)
1/k
1/k2
1/k3
k2
1
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Constant Voltage ScalingDevice and circuit parameters Factor
Scaling assumptions
Device dimensions (tox, L, W, Xj)
Doping concentration (Na, Nd)
Voltage (V)
1/k
k
1
Device parameters
Electric field (E)
Capacitance (C=εA/t)
Current (I)
Channel resistance (Rch)
k
1/k
k
1/k
Circuit parameters
Delay (CV/I)
Power (VI)
Switching energy (CV2)
Circuit density (1/A)
Power density (P/A)
1/k2
k
1/k
k2
k3
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Constant Voltage Scaling• More aggressive scaling than constant field
• Limitations
– Reliability problems due to high field
– Power density increases too fast
• Both constant field and constant voltage scaling have been followed in practice
• Field and power density has gone up as a byproduct of high performance, but till now designers are able to handle the problems
ITRS Roadmap
• Leakage power and process-voltage-temperature variation poses enormous threat to Moore’s law
1 B
1 V
3 GHz
100 W
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• International Technology Roadmap for Semiconductors 2002 projection (http://public.itrs.net/)
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Transistor Scaling
� 65nm in production, 45nm near production, 32nm in research phase
� New technology generation introduced every 2-3 years
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Cost per Transistor
� You can buy 10M transistors for a buck� They even throw in the interconnect and package for free
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Transistors Shipped Per Year
� Today, there are about 100 transistors for every ant - Gordon Moore, ISSCC ‘04
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Transistors per Chip
� 1.7B transistors in Montecito (next generation Itanium)� Most of the devices used for on-die cache memory
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Moore’s Wrong Prediction
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Chip Frequency
� 30% higher frequency every new generation
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Die Size
� ~15% larger die every new generation� This means more than 2X increase in transistors per chip
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Supply Voltage Scaling
� Supply voltage is reduced for active power control
fVCP ddactive
2∝∝∝∝
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4 Decades of Transistor Scaling
Dual Core Xeon Processor - 2006
Single Core Itanium Processor - 2005
• “An 8-Core 64-Thread 64b Power-Efficient SPARC SoC”, Sun Microsystems, ISSCC 2007
• Concurrency to combat power and thermal issues
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IBM’s CELL processor - 2005
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Power Density
Year
Po
we
r d
en
sit
y (
W/c
m2)
� High-end microprocessors: Packaging, cooling� Mobile/handheld applications: Short battery life
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Power Trend: High Performance vs. Low Power Applications
959085800.01
0.1
1
10
100
Year
Po
we
r (W
)x4 / 3years
Published at ISSCC [Sakurai]
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Active and Leakage Power
Year
Po
we
r (W
)
� Transistors are becoming dimmersdd
t
L
VV
Cdelay
−−−−
∝∝∝∝
1)
/exp(
qmkT
VI t
leak
−−−−∝∝∝∝
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Leakage Power Crawling Up in Itanium 2
� Transistor leakage is perhaps the biggest problem
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Leakage Power versus Temp.
� Leakage power is problematic in active mode for high performance microprocessors
0.18µµµµ, 15mm die, 1.4V
0% 0% 1% 1% 2% 3% 5% 7% 9%
-
10
20
30
40
50
60
70
Temp (C)
Po
wer
(Watt
s) Leakage
Active
0.1µµµµ, 15mm die, 0.7V
6% 9% 14%19%
26%33%
41%
49%
56%
-
10
20
30
40
50
60
70
Temp (C)
Po
wer
(Watt
s)
Leakage
Active
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Thermal Runaway
� Destructive positive feedback mechanism� Leakage increases exponentially with temperature� May destroy the test socket ���� thermal sensors required
Increased heating
Higher leakage
Higher power dissipation
Increased static current
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Gate Oxide Thickness
� Electrical tox > Physical tox
� Due to gate depletion and carrier quantization in the channel
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Gate Tunneling Leakage
� MOSFET no longer have infinite input resistance� Impacts both power and functionality of circuits
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Process Variation in Microprocessors
� Fast chips burn too much power� Slow chips cannot meet the frequency requirement
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Process Variation in Transistors
� More than 2X variation in Ion, 100X variation Ioff
� Within-dies, die-to-die, lot-to-lot
0.4
0.6
0.8
1.0
1.2
1.4
0.01 0.1 1 10 100
Normalized IOFF
No
rma
lize
d I
ON
NMOS
PMOS
100X
2X
150nm, 110°°°°C
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Sources of Process Variation
� Intrinsic parameter variation (static)
- Channel length, random dopant fluctuation
� Environmental variation (dynamic)
- Temperature, supply variations
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Sub-wavelength Lithography
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Line Edge/Width Roughness
• Ioff and Idsat impacted by LER and LWR
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Random Dopant Fluctuation
� Vt variation caused by non-uniform channel dopant distribution
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Resolution Enhancement Techniques (RET)
Optical Proximity Correction (OPC)
Phase Shift Masking (PSM)
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Supply Voltage Integrity
• IR noise due to large current consumption
• Ldi/dt noise due to new power reduction techniques (clock gating, power gating, body biasing) with power down mode
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Supply Voltage Integrity
• Degrades circuit performance
• Supply voltage overshoot causes reliability issues
• Power wasted by parasitic resistance causes self-heating
• Vdd fluctuation should be less than 10%
Courtesy IBM
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� Design complexity surpasses manpower� Effective CAD tools, memory dominated chips
Productivity Gap
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Lithography Tool Cost
� What will end Moore’s law, economics or physics?
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Interconnect Scaling• Global interconnects get longer due to larger
die size
• Wire scaling increases R, L and C
• Example: local vs. global interconnect delay
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Interconnect Delay Problem
� Local interconnect has sped up (shorter wires)� Global interconnect has slowed down (RC doesn’t scale)
1997 SIA technology roadmap
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Interconnect Metal Layers
� Local wires have high density to accommodate the increasing number of devices
� Global wires have low RC (tall, wide, thick, scarce wires)
M1M2M3
M4
M5
M6
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Cross Talk Noise
� As wires are brought closer with scaling, capacitive coupling becomes significant
� Adjacent wires on same layer have stronger coupling
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Cross Talk Noise
� Multiple aggressors multiple victims possible� Cross talk noise can cause logic faults in dynamic circuits
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Cross Talk and Delay� Capacitive cross talk
can affect delay� If aggressor(s) switch
in opposite direction, effective coupling capacitance is doubled
� On the other hand, if aggressor(s) switch in the same direction, Cc is eliminated
� Significant difference in RC delay depending on adjacent switching activity
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Soft Error In Storage Nodes
• Soft errors are caused by
– Alpha particles from package materials
– Cosmic rays from outer space
Logic 1 Logic 0
Vinduced
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Soft Error In Storage Nodes
• Error correction code
• Shielding
• SOI
• Radiation-hardened cell
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More Roadblocks
� Memory stability� Long term reliability� Mixed signal design issues� Mask cost� Testing multi-GHz processors� Skeptics: Do we need a faster computer?� …
� Eventually, it all boils down to economics
61
Summary� Digital IC Business is Unique
� Things Get Better Every Few Years
� Companies Have to Stay on Moore’s Law Curve to Survive
� Benefits of Transistor Scaling� Higher Frequencies of Operation
� Massive Functional Units, Increasing On-Die Memory
� Cost/MIPS Going Down
� Downside of Transistor Scaling� Power (Dynamic and Static)
� Process Variation
� Design/Manufacturing Cost
� ….