ee457 Final Sp2019 -

May 8, 2019 10:44 am EE457 Final - Spring 2019 1 / 13 C Copyright 2019 Gandhi Puvvada

EE457 Final Exam (~33%)Closed-book Closed-notes Exam; No cheat sheets;

No calculators, no cell phones. Verilog Guides are not needed and are not allowed.Smart phones, tablets, and all kinds of computing/Internet devices are not allowed.

This is a Crowdmark exam. Please do not write on margins or on the backside.Spring 2019

Instructor: Gandhi PuvvadaWednesday 5/8/2019 (A 3-hour exam) 05:00 PM - 08:00 PM (180 min) in SGM101

Viterbi School of EngineeringUniversity of Southern California

Ques# Topic Page# Time Points Score

1 Lab 7 Part 3 modifications 2-5 79

2 Lab 6 Early Branch Design with a Dummy Stage 6-7 35

3 16x4 FIFO 8 38

4 Cache and Virtual Memory 9 32

5 Tomasulo OoO 10-11 39

6 CMP_CMT, MOESI 11-12 51

7 Terminology 13 8

Total Cover+12 = 13

282

Perfect Score 275


1 ( 9+40+30 = 79 points ) min. Lab 7 Part 3 modifications

Given below is very brief part of the Spring 2011 MT question that you went through. The next to next page contains the solution block diagram for the same.

========== In the Fall 2010 midterm exam, we have an ADD4 unit in each of the two EX stages, EX1 and EX2. Here, those two stages, EX1 and EX2, are merged into EX12. So ADD8 needs an extra clock in EX12 as it has to go through the second ADD4 also. Further we introduced a BZ (Branch if Zero) instruction. BZ $X, JJJJ; (PC) <= JJJJ if ($X) = 0 The instructions are 32-bits in size, but the addresses are only 16-bit. PC is 16-bit wide and is incremented by a "1". The JJJJ in the BZ $X, JJJJ stands for a 16-bit (4-digit hex) absolute branch address. If the source register $X is a zero then we branch to JJJJ [ (PC) <= JJJJ if ($X) = 0 ].==========

In this exam we added one more ADD4 unit in the EX stage and called the stage EX123 (to stand for merged state of what otherwise would have been three stages, namely EX1, EX2, and EX3. This supports ADD12 besides ADD4 and ADD8. ADD8 needs one extra clock and ADD12 needs two extra clocks in the EX123 stage. The block diagram is given after the solution block diagram of the Spring 2011 MT question. We can draw a suitable state diagram with 2 or 3 states (with or without a small counter I) to generate the STALL_123. Let us use shorthand names: A4 for EX123_ADD4, A8 for EX123_ADD8, and A12 for EX123_ADD12. I have created below a 3-state state diagram with states, FC (First Clock), SC (Second Clock) and TC (Third Clock). I have also created a 2-state state diagram with states, FiC (First Clock), SubC (Subsequent Clock(s)). In the 2nd diagram, I used a counter I, initialized to zero in Fic and incremented in SubC.

4pts

5pts

C1

C1

C2C2

1

FC SC TC

If C1, activate STALL_123

If ______, continueSTALL_123else release it.

Release

RESET_B

C3

C3

C4

FiC SubC

If C3, activate STALL_123

If ________, continueSTALL_123else release it.

RESET_B

I <= 0;I <= I + 1;

C4

STALL_123

SD#1 (State Diagram #1)


complete it

complete it

If it doesn’t fit there, write it outside

If it doesn’t fit there, write it outside


Let us assume that we use one-hot implementation for these state machines. So, we can make use of the one-hot state variables QFC, QSC, and QTC, in the case of the first state diagram, SD#1, and QFiC and QSubC in the case of the second state diagram, SD#2. Arrive at the conditions and STALL_123 in the boxes below for each of the two state diagrams. Use simple gates (AND, OR, NAND, NOR, Inverter) to show your logic. STALL_123 generation logic is called ______ (NSL/OFL)

Complete the Time-Space diagram below. Note $R is the destination register and $X is the source register in ADD4 $R, $X. And $X is the source register in BZ $X, JJJJ .

The FU_Br and XBR_Mux in Box #1 are necessary. T / FIf answered True, produce FORW_Br and complete connections on the Block diagram. Otherwise, cross it off. In either case, explain why you think it is necessary or unnecessary with an example.____________________________________________________________________________ ____________________________________________________________________________ The bubble-injection logic using 4 AND gates in Box #2 above is unnecessary. T / FExplain: _____________________________________________________________________ ____________________________________________________________________________

1 pts

21pts In the clock, in which you are preparing to return to the

FC state (whether it is from the SC or TC), the STALL_123 is definitely inactive. T / F

C1


C2

STALL_123

In the clock, in which you are preparing to return to the FiC state from the SubC, the STALL_123 is definitely inactive. T / F

C3


C4

STALL_123

2 pts 2 pts

2 pts 2 pts

2 pts 2 pts

4 pts 4 pts

19pts

STALL_BR

AD

D4

AD

D8

RA

MO

VID_ADD4

ID_ADD8

ID_MOV

ID_BZA

DD

12ID_ADD12

STALL_BR

FU_B

r

FOR

W_B

r

Box #1 Box #2

0

1

XBR_Mux

You can write A4 for ADD4A8 for ADD8A12 for ADD12

6+4 bonus

1+3 pts

1+4 pts

May 8, 2019 10:44 am

EE457 Final - Spring 2019 5 / 13C

Copyright 2019 G

andhi Puvvada

PC

XA

Reg. File

XA

RA

RDR-Write

0

10

1

A

Cout

Comp Station in ID Stage

ID_XMEX123

P

IF ID EX123 WBComp Station in ID Stage

Q

ID_XA EX123_RA

P=Q

ID_XA Matched with EX123_RA

XD

HDU_BR

EN

XM

EX12

3

A+4

FU

EN

RD

Writ

e

RA

XD

RESET_BRESET_B

1. Produce STALL_123 on anothr page and use it here. Produce STALL_BR here.

3. Produce FORW, PCSource, IF_Flush.

EX123_ADD4

EX123_ADD8

EX123_RA

WB_RA

WB_Write

WB_RDX1_MuxR1_Mux

SKIP1

Modified LAB 7 Part 3 Block Diagram

I-M

EM

EN

RESET_B

ADD4STALL_BR

EN

FORW

Three ADD4’s in EX123 stage

ADD

4A

DD

8

RA

MO

V

ADD

4A

DD

8

RA

MO

V

EX123_MOV

2. Produce SKIP1, SKIP2, and SKIP3. ADD4 uses the first ADD4 unit and ADD8 uses the first two ADD4 units.

ID_ADD4

ID_ADD8

ID_MOV

BZ

XD_ZERO

ID_BZ

+1

0

1

JJJJ

BranchAddress

16

16 1616

ID_XMEX123

EX12

3_W

rite

PCSource

IF_Flush

EX123_XMEX123

AD

D12

AD

D12

ID_ADD12EX123_ADD12

0

1A

Cout

A+4R2_Mux

SKIP2

ADD4

0

1A

Cout

A+4R3_Mux

SKIP3

ADD4

4. Draw the rest of the logic (Enables, RF connections, etc. (similat to the Spring 2011 Midterm Solution)).

RESET_B

0

1

XBR_MuxID_XA

FU_B

r

FOR

W_B

r

26+4pts


2 ( 35 points ) min. Lab 6 Early Branch Design with a Dummy Stage (total 6 stages)

On the next page, we have reproduced the solution page to the "Dummy Stage between the original EX and the original MEM stages" design from the Q#1 of the Final exam of Fall 2018 that you went through.

Your lab partner read the following note on the solution page.

He expressed concern about priority among items forwarded into the EX stage. Investigate his concern. Use words such as the following in your investigation summary on next page. "near senior", "farther senior", "less significant", "more significant", "natural order", "total seniors", "overwritten", "over-ridden", "thanks, but no thanks", "remember to reject"

Would you use a beq or an R-type instruction as recipient of the help here?_____ (beq/R-Type)Explain: _____________________________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________ Would you use a lw or an R-type instruction as provider of the help here?_____ (lw/R-Type)Explain: _____________________________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________ The note on solution page reads, "Forwarding from MEM to EX is redundant to the forwarding from Dummy to ID. Hence MEM to EX forwarding path can be removed." So, is it possible that we could have chosen to remove the help from Dummy to ID and retained the help from MEM to EX?______ Yes / No. Explain _______________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________ We use S#1 (standing for senior #1) for the nearest senior, S#2 (standing for senior #2) for the next senior, who is slightly farther, and so on. Here the provider of help is _______ (S#1/S#2/S#3/S#4) to the recipient of help. Is it possible that the distance between the two (recipient and provider) may change because of any stalls? And, if the distance may change, would that make our plan to remove redundancy inappropriate?! Explain. ________________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________

ALU

ALUSrc

ALU

_res

ult

Stor

e_da

ta

11

11

1

00

00

0

Rs

RtIF ID EX Dummy MEM WB

MEM-to-EXDummy-to-ID

Forwarding from MEM to EX is redundant to the forwarding from Dummy to ID. Hence MEM to EXforwarding path can be removed. Hence comparison units in FU and forwarding mux pairs count inEX were reduced back to 2 and 4 respectively.


Relative priority concern investigation summary


3 ( 10+8+2+14+2+2 = 38 points ) min. 16x4 FIFO (for this question the FIFO has 16 locations)

3.1 If you calculated (WP-RP) and the result came out to be zero, in which case or situation, you say it is ambiguous as it could mean EMPTY or FULL and in which case or situation you say it is not ambiguous and it indicates that the FIFO is clearly __________ (FULL/EMPTY)? Narrate below. (WP-RP) == 0 => ambiguous: ___________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________ (WP-RP) == 0 => non-ambiguous: ________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________

3.2 One of the two (single-clock FIFO or the 2-clock FIFO) has two choices, where as the other has only one choice. What choice are we talking about? Who has what choice(s)? _____________ ___________________________________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________

3.3 If you are looking for a single-clock FIFO, but if, in the lab, there are only 2-clock FIFOs available, it ______ (is/isn’t) possible to substitute a 2-clock FIFO for a single-clock FIFO.

3.4 You are building a 2-clock 256-deep FIFO (256 = 28 => (n=8); So [(n+1) = 9]. You would use _____ (9-bit/8-bit/7-bit) counters for WP and RP. You would use _____ (9-bit/8-bit/7-bit) subtracters, altogether a total of ____ (state a number) of them. You would perform ________ (Mod-512/Mod-256/Mod-64) subtraction by _________________ (ignoring/considering) __________ (incoming/outgoing) borrow. If the producer clock is 1 MHz and the consumer clock is 16 MHz in an application using this 256-deep FIFO, it _________ (is/isn’t) possible that the producer thinks that the FIFO is ___________ (FULL/EMPTY) and the consumer thinks that it is ____________ (FULL/EMPTY) at the same time. Explain your choice of "is possible" or "isn’t possible". ____________________________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________

3.5 If there is one subtracter in a FIFO to calculate depth as the difference of WP and RP, it (the FIFO) is most likely a _____ (A/B) where A = Single-Clock FIFO, B = a Two-Clock FIFO. Gray code counters are used in ______ (A/B).

3.6 Never ever synchronize by sampling and holding (circle all applicable):(a) a multi-bit data item where one bit at most changes at any time(b) a multi-bit data item where multiple bits could be changing simultaneously(c) none of the above

10pts

2 pts

4 pts

4 pts

8pts

2pts

14pts

2pts

2pts


4 ( 10 + 14 + 8 = 32 points) min. Cache and Virtual Memory

4.1 Mr. Bruin saw your division of the VA (Virtual Address) and PA (Physical Address) and thought that you made a mistake as the set fields are quite different. Please explain to him. _______ _________________________________ _________________________________ _________________________________ _________________________________ _________________________________ _________________________________ If, you competitor, Miss Trojan, saw the same diagram, find what all information she would have gathered. ____________________________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________

4.2 VIPT stands for ________________________________(what)_______ cache / virtual memory.PIPT stands for ________________________________(what)_______ cache / virtual memory.In Q#4.1 above, are you doing (or could you be doing) VIPT or does it have to be PIPT? _______ How can you tell? _____________________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________ ____________________________________________________________________________ _____________ (VIPT/PIPT) has an advantage over _____________ (VIPT/PIPT) TLB access, then Cache Tag Access, followed by Cache Tag Check,... if we said so much, even before we complete our sentence, people would conclude that we are doing ________ (VIPT/PIPT) because ____________________________________________________________________________________________________________________________________________

4.3 The number of TAG RAMs in a cache system ___________ (needs/does not need) to be a power of 2.The number of Sets in a set-associative cache system _________ (needs/does not need) to be a power of 2.The number of words per block in a cache system __________ (needs/does not need) to be a power of 2.

For the same 64KB cache, if you double DoSA, you will be ______________ (doubling/halving/neither) the number of TAG RAMs, ______________ (doubling/halving/neither) the depth of TAG RAMs, and ______________ (doubling/halving/neither) the number of TAG comparators.

If you have a cache miss, the CCU (Cache Control Unit) will _________ ( i / ii / iii)(i) fetch the block from the MM (main memory) (ii) will consult the MMU to find if the page is present in the MM before going to the MM(iii) will raise an exception in some systems

VA31 VA[1:0]VA14 VA13VA17VA18

4-bitSet Field

PA31 PA[1:0]PA4 PA3PA17PA18

14-bitSet Field

DoSA = 4

DoSA = 4 10pts

14pts

8pts


5 ( 3+9+2+7+10+2+6 = 39 points) min. Tomasulo OoO

5.1 RAS (Return Address Stack) is not shown in the above diagrams. Would you show it in _____ (i / ii / iii/ iv)(i) the LHSD (Left-hand side design) (ii) the RHSD (Right-hand side design) (iii) both (iv) neither?RAS helps ______________ (jal / jr $31 / any jr say jr $8 / multiple of these / none of these).

5.2 Memory disambiguation rules are _______ (more / less) in the LHSD than in the RHSD. WAW needs to be checked in ___________ (LHSD only / RHSD only / in both / in neither). Bypass counters and a SAB (Store Address Buffer) are discussed in the context of ___________ (LHSD only / RHSD only). They _______ (can also be / cannot be) used in other design. Cache in the back-end is considered a ________________ (fixed latency/variable latency) device, hence a Load buffer in the LHSD and LS buffer in RHSD are added to the design to help ____________ (LSQ/CDB/Issue Unit).

5.3 Dispatch unit monitors CDB and causes writing into the register file in ___________ (LHSD only / RHSD only / in both / in neither).

5.4 RST (Register Status Table) in the LHSD is associatively searched _____ ( i / ii / iii / iv)(i) during dispatching a new instruction, (ii) during completion of an earlier instruction, (iii) both, (iv) none.This search sometimes yields in multiple matches and we need to prioritize and select one match. True/False.In RHSD, associative search is conducted in ROB for ____ (1 / 2) ____________ (source/destination) register(s) of the instruction being dispatched. This search sometimes yields multiple matches with the destination registers of the senior instructions in ROB and we need to prioritize and select. True/False.

5.5 The SAB (Store Address Buffer) in RHSD saves a lot of headache to the ROB. The ___ (lw/sw) instructions in the LSQ search for matching store address(es) left by _______________________ (the youngest senior / any / all senior / all junior / all senior and junior) ______ (lw / sw) instruction(s) in the SAB and match the count with the bypass counter to see if it is OK (i.e. no __________ (RAW / WAW / WAR) dependency violation) to proceed to the D_Cache. Entries in the SOB __________ (bear/do not bear) their ROB Tag. Some entries in the SOB may get flushed on branch misprediction. T / F

ROB

I -Cache

��

Dispatch

I-Fetch Queue

Integer Queue

Load/StoreQueue

DivQueue

Mult Queue

CDB

Back-end

Front-end

ROB(Re-order Buffer)

Reg File

BPB

Exe Unit Exe UnitCache

Exe Unit Exe Unit

Issue Unit

��

Addr Buff

OoO Execution and In-Order Committing with ROB (Re-Order Buffer)

LS_Buffer

CacheIoI - OoE - OoC design IoI - OoE - IoC design

Left Design

Rig

ht D

esig

n

Load Buffer

3131

OoO Execution and OoO Commitment with RST

1+2 pts

6+3 pts

2 pts

7 pts

9+1 pts


5.6 One can have SAB with no bypass counters in a design. T / FOne can have bypass counters with no SAB in a design. T / F

5.7 Issue unit is ______________________ (basically the same / quite different) in the two designs, LHSD and RHSD. It tries to maximize the throughput in the back-end while meeting the CDB constraint. What is the CDB constraint? _______________________________________________ ___________________________. There ______ (is/isn’t) a CDB register, just upstream of the CDB.

6 ( 10+3+3+4+3+3+5+3+3+7+7 = 51 points) min. CMP_CMT, MOESI, Mutual exclusion

6.1 ILP stands for __________________ parallelism where as TLP stands for ________________ parallelism. Our OoE design tries to exploit ___________ (ILP/TLP/both/neither).Intel’s trade name for SMT (_______________________) is HTT, which stands for ___________________ _________ and it exploits ________________ (ILP/TLP/both/neither). Compared to processor speeds, memory speeds are relatively _________ (low / high) and this caused ____________________ (saturation / increase) in ________(ILP/TLP) and necessitated exploring ____________ (ILP/TLP).

6.2 Cache coherency is needed in the following (circle your choices):1. Single-core single threaded processor2. Multi-core, each core running a single thread3. Single-core processor, with multiple threads in that single core4. Multi-core Multi-threaded processor

6.3 We were told that exceptions are taken in the program order but not temporal orderThe above statement differentiating program order and temporal order is significant in which of the following (circle them).(a) single cycle CPU (b) multi-cycle CPU (c) 5-stage in-order CPU (d) OoO Tomasulo with ROB

6.4 In the CMP organization on the side, an 4 x 8 crossbar is used as the memory interconnection network. Cross-bar provides ______________ (highest/average/lowest connectivity and is ________ (most / least) expensive. Maximum connectivity here means _____ (4 / 8 / neither) simultaneous connections. Crossbar is a __________________ (circuit-switched/packet-switched) network.

6.5 Less MPI (Miss rate Per Instruction) means ________ (more/less) CPI. In the MPI calculations, the "per instruction" refers to ___________ (all / only memory accessing) instructions.

6.5.1 In a system with a L1, L2, L3, and MM, L1 cache MPI is 10% and the L1 miss penalty is 10 clocks (i.e. L2 access time is 10 clocks) and L2 cache MPI is 5% and the L2 miss penalty is 20 clocks (i.e. L3 access time is 20 clocks) , and L3 cache MPI is 2% and the L3 miss penalty is 250 clocks (i.e. MM access time is 250 clocks) what is the overall CPI assuming there are no other problems causing lowering of the CPI. ________ Calculation of CPI ____________________________________________________________

2 pts

4+2 pts

10 pts

3 pts

3 pts

P0

L1$

P1

L1$

P3

L1$

Crossbar Memory

Shared L2 cacheL2$ L2$ in 8 banks

Interconnection Network

4 pts

2+1 pts

3 pts


6.6 The O (Owner) state in MOESI protocol makes that block in that L1 cache the designator helper. T/F Common to O and M states ________________________ (being dirty / being the only copy).Common to E and M states ________________________ (being dirty / being the only copy).If the block in the owner state needs to be replaced by another block, there will be no owner for that block. T / F In that situation the block shall be flushed to MM T/ F

6.7 The cache shall be a non-blocking cache in a (circle your choices):1. Single-core single threaded processor2. Multi-core, each core running a single thread3. Single-core processor, with multiple threads in that single core4. Multi-core Multi-threaded processor

6.7.1 In the context of a Non-blocking cache, MSHR stands for ________________________. MSHR is filled with a request by the ________ (CCU/SCU) and it is attended to by the ________ (CCU/SCU).

6.8 ISA support (example: LL and SC in MIPs) is necessary to provide mutual exclusion (circle all applicable)(a) between interacting processes in a multi-processing system (b) between interacting threads running on different cores (c) between interacting threads running on the same core _______________ (However / Even ) if there is only one thread per core and you have established MOESI between cores, atomic test and set __________ (can / cannot) be guaranteed with the simple (ordinary) lw and sw instructions. In MIPs ISA, LL stands for ____________________ and SC stands for ______________________.

6.9 BAR stands for a Barrier Count. An example of a BAR is our Walls Completed Count, which acts as a barrier to reach 4 before we can start the Roof building process. BAR can be incremented in a critical section after obtaining a lock. Or it can be incremented using a lock-less coding method. In the two codes below, for every load, you decide whether to use LL or LW and for every store you decide whether to use SC or SW.

5 pts

2+1 pts

3 pts

7 pts

7 pts


7 ( 8 points) min. TerminologyTomasulo Part 3 (to be covered in EE560 and EE557)PRF stands for _______________________FRL stands for _______________________RAT stands for _______________________FRAT stands for _______________________ RRAT stands for _______________________

Blank Area

We enjoyed teaching this challenging course. Hope you all also enjoyed it. Hope to see some of you in the EE560 :) Best! Gandhi, TAs: Tanvir and Shreya, Mentor: Spandan, HW Graders: Ruizhi and Lan Lab graders: Rui and Jinxin

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