EE415 VLSI Design

NOTICES

•Final Homework 4.10, 4.13, 4.14, 4.18 Due

Monday March 15 Before 12:00 Noon (EECS

Mailbox)

•Final Project Report due by Monday March 15

EE415 VLSI Design

NOTICES

•Online Lectures and Quiz Solutions

•Check Grade Page

•Homework

EE415 VLSI Design

NOTICES

•Congratulations on completing Final Project!

•Publish your work!

•Resume/Job Applications

•Mentor Graphics

•EE416

•Thank You!

EE415 VLSI Design

Final Exam

•Tuesday March 16 at 8:00 AM in Rm. 317

•Comprehensive (focus on latter part)

•Open Book, Notes, Quizzes, Homework, Lectures

•Open ended questions

•Bring color pencils

•Go though Quizzes and Homework

•Probably 4 questions (may have a choice)

EE415 VLSI Design

SEQUENTIAL LOGIC

Read Chapter 6

EE415 VLSI Design

Master-Slave Flip-Flop

D

InA

B

Overlapping Clocks Can Cause

• Race Conditions

• Undefined Signals

EE415 VLSI Design

2 phase non-overlapping clocks

D

In

t12

EE415 VLSI Design

2-phase dynamic flip-flop

DIn

Input Sampled

Output Enable

EE415 VLSI Design

Flip-flop insensitive to clock overlap

DIn

VDDVDD

M1

M3

M4

M2 M6

M8

M7

M5

section section

CL1 CL2

X

C2MOS LATCH

Two Modes

•Evaluation

•Hold

EE415 VLSI Design

How does C2MOS work?

Two Modes

•Evaluation

•Hold

Operates as a negative edge-triggered master-

slave D FF

= 1

In CL1

= 0

CL1 CL2

EE415 VLSI Design

Flip-flop insensitive to clock overlap

DIn

VDDVDD

M1

M3

M4

M2 M6

M8

M7

M5

section section

CL1 CL2

X

C2MOS LATCH

Two Modes

•Evaluation

•Hold

EE415 VLSI Design

C2MOS avoids Race Conditions

DIn

1

M1

M3

M2 M6

M7

M5

1

VDDVDD

(a) (1-1) overlap

X

only PDN are enabled input cannot propagate to

output

condition for signal propagation active PDN followed by active

PUN

EE415 VLSI Design

C2MOS avoids Race Conditions

DIn

VDDVDD

M1

M4

M2 M6

M8

M5

0 0

(b) (0-0) overlap

X

only PUN are enabled input cannot propagate to

output

condition for signal propagation active PUN followed by active

PDN

EE415 VLSI Design

PipeliningR

EG

RE

G

R

EG

log.

RE

G

RE

G

RE

G

.

RE

G

RE

G

logOut Out

a

b

a

b

Non-pipelined version Pipelined version

EE415 VLSI Design

Pipelined Logic using C2MOS

InF Out

VDD

VDD

VDD

C2C1

GC3

NORA CMOS

What are the constraints on F and G?

EE415 VLSI Design

Example

1

VDD

VDDVDD

Number of a static inversions should be even

i.e. logic functions (implemented using static CMOS)

between latches must be non-inverting

EE415 VLSI Design

NORA CMOS

•Stands for NO-RAce CMOS

•Implements fast pipelined datapaths using dynamic logic

•Combines C2MOS pipeline registers and np-CMOS dynamic logic

blocks

•Module consists of a comb. logic block (static, dynamic, or

mixed) followed by a C2MOS latch

•Logic and latch are clocked so that both are in evaluation or

hold (precharge) mode simultaneously

•Block which is in evaluation during = 1 is called a -module

•NORA datapath consists of alternating blocks on and _BAR

modules

EE415 VLSI Design

NORA CMOS Modules

VDDVDD

PDN

In1In2In3

VDD

PUN

Out

VDD

Out

VDD

PDN

In1In2In3

VDD

In4

In4

VDD

(a)-module

(b)-module

Combinational logic Latch

EE415 VLSI Design

Design Rules for NORA CMOS

The dynamic logic Rule:

•Inputs to a dynamic n (p) block are only allowed to make a 0

1 (1 0) transition during the evaluation period

The C2MOS Rule:

•The number of static inversions between C2MOS latches should

be even (in the absence of dynamic nodes); if dynamic nodes are

present, the number of static inverters between a latch and a

dynamic gate in the logic block should be even. The number of

static inversions between the last dynamic gate in a logic block

and the latch should be even as well.

EE415 VLSI Design

NORA CMOS Modules

VDDVDD

PDN

In1In2In3

VDD

PUN

Out

VDD

Out

VDD

PDN

In1In2In3

VDD

In4

In4

VDD

(a)-module

(b)-module

Combinational logic Latch