EE330 Lab Final Project Curtis Mayberry and Josh Sevcik.
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Transcript of EE330 Lab Final Project Curtis Mayberry and Josh Sevcik.
Exercise AssistantEE330
Lab Final ProjectCurtis Mayberry and Josh Sevcik
Project OverviewCreate an exercise assistant that will take in
an Ascii user input describing the user and the user’s current heart rate and then will return to the user useful exercise information.
This Exercise information includes the total Calories burned for the day, current Calorie balance, time remaining until the desired calorie deficit at current pace, and a warning light that warns the user if their heart rate is too high.
Assumptions5 digit Ascii input available in parallelInput limits
Age < 127 years Weight < 511 kg V0_max < 255 Calories: up to 9999 input Desired deficit: up to 9999 input
Exercise assistant should not be used for much longer than 24 hours
General module layout
ASCII Converter Computational unit
Heart Rate Converter
Warning light
Balance 7 seg display
driver
Calories 7 seg display
driver
Time Remaining 7 seg display
driver
Ascii Inputs
To 7 segment Displays
To Heart Rate Warning Light
Original module layout
ASCII Converter
EstExp
Heart Rate Converter
Warning light
Balance 7 seg display
driver
Calories 7 seg display
driver
Time Remaining 7 seg display
driver
Ascii Inputs
To Heart Rate Warning Light
Balance Calc
Warning Light
Day’s Exp
Time Remaining
Calc
Input plan Any input that is not a number is ignoredFirst number of five number input specifies
the input to be changedThis allows any input to be changed at any
time0: Age2: Weight3: V0_max4: Calories5: Desired Deficit6: Reset
7-segment output3 separate seven segment displays4 digits a piece32 pin output to seven segment displays
Code example for Ascii Converteralways @(posedge clk)
beginif(reset)
beginage = 20;weight = 135;sex = 0;v0_max = 40;Calories = 2000;desired_deficit = 100;end
else if ((ascIn[34:32]==3'b011) && (ascIn[27:25]==3'b011) && (ascIn[20:18]==3'b011) && (ascIn[13:11]==3'b011) && (ascIn[6:4]==3'b011))
begin//convert first decimal number(least significant)case(ascIn[3:0])4'b0000: bOut0 = 0;
Layout Sample: Ascii Converter
Schematic Sample: Ascii Converter
Further Notes
Consider This… always @(posedge clk or posedge calc_reset) begin if(calc_reset) begin Exp <= 0; cycles <=0; EE <= 0; bal <= 0; tr <= 0; end else begin
//estimator module EE <= ((-593954)+sex*((-363781)+2710*age+3940*weight+4040*v0_max+6340*heart) + (1-
sex)*(2740*age+1030*weight+3800*v0_max+4500*heart))/41840;
//Days_Exp module cycles<=cycles+1; //Exp=cycles; Exp<=((cycles*EE)/360);
//balance module bal <= Calories - Exp;
//time_remaining module tr<=(desired_def - Exp)/EE; end end
SuccessesAll DRC checks passedAll modules work:
Simulations successfulAll circuits synthesized in RTLAll circuits imported to Cadence
WeaknessesLVS ran, but not completely successfulProblems with pins needing renamed and 5-digit ascii parallel load may require extra circuitry
( can be accommodated in another module or in input device)
Separate module had trouble instantiating into one main module (net-list error attributed to Library issues)
Biggest mistake: Breaking it up into too many pieces, the project was overestimated- 8 was too many, but 3 was the correct numberMade sense at beginning but as we became more
comfortable with Verilog, coding larger modules became easier
Bringing it all together //converted inputs
wire [13:0] age, weight, sex, v0_max, Calories, desired_deficit, heart_converted;
wire [13:0] EE; //Estimated Expenditure (output of estimator)wire [13:0] Exp; //Day's Expenditure (output of estimator)wire [13:0] bal; //balance (goes to 7 segment converter modulewire [13:0] tr;
output [32:0] caloriesdisplay, balancedisplay, trmaindisplay;output warning;
//sub-circuitsascii_decode ascii_converter_inst(ascii_input, reset_ascii_conv, age, weight, sex, v0_max, Calories, desired_deficit, clk);
heartrateconverter heartconv_inst(heart, clk, heart_converted);
estimator estimator_inst(clk, age, weight, sex, v0_max, heart_converted, EE);
heartwarning heartwarning_inst(age, heart_converted, warning, clk);
Days_Exp Days_Exp_inst(EE,Exp,clk);
balance balance_inst(desired_deficit, bal, Exp, clk);
time_remaining time_remaining_inst(bal, EE, tr, clk);
seg4 seg4_inst(clk, Calories, bal,tr,caloriesdisplay,balancedisplay,trmaindisplay);
Questions?
Learned a lot of VerilogLearned how to write Verilog to ensure
synthesis and LVSLearned a lot about design planning and
design considerations