Ee325 cmos design lab 4 report - loren k schwappach

EE325, CMOS Design, Lab 4: L-Edit NMOS Inverter Characteristics

1

Colorado Technical University

PSpice, L-Edit Designed NMOS Inverter Analysis

Lab 4 Report Submitted to Professor R. Hoffmeister

In Partial Fulfillment of the Requirements for EE 325-CMOS Design

By Loren Karl Robinson Schwappach

Student Number: 06B7050651

Colorado Springs, Colorado Due: 17 May 2010

Completed: 26 May 2010


2

Table of Contents

Lab Objectives ..................................................................................................................................................................................................................................... 3

Requirements and Design Approaches/Trade-Offs .................................................................................................................................................................. 3

L-Edit NMOS Inverter........................................................................................................................................................................................................................ 4

NMOS Inverter Cross Section ...................................................................................................................................................................................... 4

NMOS Inverter Design Rule Check ............................................................................................................................................................................ 4

NMOS Inverter L-Edit Extracted NMOS.SPC File ................................................................................................................................................... 5

NMOS Inverter Modified SCNA.SPC File ................................................................................................................................................................... 5

Characteristic Curves for the NMOS Inverter ............................................................................................................................................................................. 6

Circuit Layout .................................................................................................................................................................................................................. 6

PSpice Simulation Results............................................................................................................................................................................................ 8

Voltage Transfer Function of the NMOS Inverter ..................................................................................................................................................................... 9

Circuit Layout ................................................................................................................................................................................................................10

PSpice Simulation Results..........................................................................................................................................................................................11

Truth Table ....................................................................................................................................................................................................................11

Power Consumption of the NMOS Inverter ..............................................................................................................................................................................12


Small Signal Characteristics of the NMOS Inverter ................................................................................................................................................................13

Circuit Layout ................................................................................................................................................................................................................13


Frequency Response of the NMOS Inverter .............................................................................................................................................................................15

Circuit Layout ................................................................................................................................................................................................................15


Propagation Delay and Rise/Fall Times of the NMOS Inverter ...........................................................................................................................................17

Circuit Layout ................................................................................................................................................................................................................17

PSpice Simulation Results................................................................................................................................................................................... 18-19

Digital Frequency Response of the NMOS Inverter ................................................................................................................................................................20

PSpice Simulation Results................................................................................................................................................................................... 20-21

Maximum Frequency of the circuit using the NMOS Inverter .............................................................................................................................................22


Summary of Results .........................................................................................................................................................................................................................23

Conclusion and Recommendations .............................................................................................................................................................................................24


3

Lab Objectives

This objective of this lab is to gain additional experience in the use and features of one of the

most popular analog and digital simulation software packages; PSpice (specifically OrCAD

Capture CIS Demo Version 15.7). As an added objective, the user should complete this lab

assignment with a greater understanding of the common characteristics of N-channel MOSFET’s

(NMOS) device, specifically the NMOS built for EE325 Lab 2 using L-Edit Student Edition

Version 7.2. The user should further be able to compare the characteristics of the NMOS

inverter circuit against the IRF-150 Power MOSFET circuit analyzed during EE325 Lab 3. This

lab will evaluate/compare the L-Edit NMOS inverter characteristics against the IRF-150 results

from Lab 3 by generating device characteristic curves, voltage transfer function, frequency

response diagram (bode plot), and time domain analysis of specific frequencies needed to

compute the characteristic rise/fall times, and propagation delays, and maximum frequency.

Requirements and Design Approaches / Trade-offs

There are no specific design requirements for this project since it is not a design project, but a

PSpice learning / inverter characteristic comparison lab. The primary objective of this lab is to

learn the procedures and methods in using the PSpice simulation software and to identify and

analyze key characteristics of the N-channel MOSFET (NMOS) inverter circuit while comparing

the results against the IRF-150 Power MOSFET inverter circuit analyzed for lab 3. The NMOS

inverter circuit and data collected through this lab analysis will be compared again in lab 5. To

successfully accomplish the PSpice analysis of the NMOS inverter, the user must have

successfully completed EE 325 lab 2 using L-Edit. The user must have extracted the

NMOS.SPC file created during lab 2, the L-Edit SCNA.SPC file edited during lab 2, Cross-

Section results from lab 2, DRC results from lab 2, and L-Edit NMOS Tanner Database File

from lab 2. These files should be compared against the figures / data presented on the following

pages.


4

L-Edit N-Channel MOSFET (NMOS) Inverter Layout

Figure 1: L-Edit NMOS Inverter created for EE325 Lab 2. A slight modification to Lab 2 NMOS left Active

Layer and it’s contained Metal layers was accomplished, in order to eliminate the DRC errors created by Lab

2, due to the Drain, Gate, and Source Metal layers (had to be 3 µm apart). However this modification still

allowed the NMOS W=18 µm and L = 6 µm.

The layers used in the L-Edit design of this NMOS inverter are identified below...

light purple = P-Select layer,

teal = N-Select layer,

red = Poly layer (width = 6µm),

green = two Active layers inside the (P / N)-Select layers both heights = 18µm,

blue = four Metal layers with assigned ports (Substrate, Source, Gate, and Drain),

black = Contact layers (12 Active inside Metal/Active layers, and 1 Poly Metal/Poly layer.

L-Edit NMOS Inverter Cross Section Obtaining the NMOS Inverters cross section was accomplished by clicking Tools/Cross-Section and clicking on the NMOS inverter using the “Pick” button.

Figure 2: EE325 Lab 2 L-Edit NMOS Inverter Cross Section.

L-Edit NMOS Inverter Design Rule Check The DRC errors were removed by increasing left Active/Metal layer spacing as shown above.

-------------------- NMOS.SPC --------------------- DRC Errors in cell Cell0 of file G:\CMOS Design\LAB 4\NMOS.

0 errors. DRC Merge/Gen Layers Elapsed Time: 0.000000 seconds.

DRC Test Elapsed Time: 0.000000 seconds. DRC Elapsed Time: 0 seconds.

-------------------------------------------------------


5

L-Edit NMOS Inverter Extracted File Some important things to not about this file, are the “Node Name Aliases”, these are the net aliases names that must be used in PSpice. Also mentioned are L=6 µm and W = 18 µm.

-------------------- NMOS.CSE --------------------- * Circuit Extracted by Tanner Research's L-Edit V7.12 / Extract V4.00 ;

* TDB File: G:\CMOS Design\LAB 4\NMOS, Cell: Cell0 * Extract Definition File: C:\LEdit\mosis\morbn20.ext

* Extract Date and Time: 05/25/2010 - 21:49 * WARNING: Layers with Unassigned AREA Capacitance.

* <Poly Resistor> * <Poly2 Resistor> * <N Diff Resistor> * <P Diff Resistor>

* <N Well Resistor> * <P Base Resistor>

* WARNING: Layers with Unassigned FRINGE Capacitance. * <Pad Comment> * <Poly Resistor>

* <Poly2 Resistor> * <N Diff Resistor> * <P Diff Resistor>

* <N Well Resistor> * <P Base Resistor>

* <Poly1-Poly2 Capacitor> * WARNING: Layers with Zero Resistance.

* <Pad Comment> * <Poly1-Poly2 Capacitor>

* <NMOS Capacitor> * <PMOS Capacitor>

* NODE NAME ALIASES * 1 = Gate (12,33) * 2 = Drain (5,33)

* 3 = Source (19,33) * 4 = Substrate (29,33)

M1 Source Gate Drain Substrate NMOS L=6u W=18u AD=126p PD=50u AS=126p PS=50u * M1 DRAIN GATE SOURCE BULK (8 9 14 27)

* Total Nodes: 4 * Total Elements: 1

* Extract Elapsed Time: 0 seconds .END

-------------------------------------------------------

Edited SCNA.CSE File Required for L-Edit NMOS Inverter in PSpice Lines 2 and 11 of this file were edited to change CMOSN to NMOS and CMOSP to PMOS.

-------------------- SCNA.SPC --------------------- * THESE ARE TYPICAL SCNA SPICE LEVEL 2 PARAMETERS

.MODEL NMOS NMOS LEVEL=2 LD=0.250000U TOX=417.000008E-10 + NSUB=6.108619E+14 VTO=0.825008 KP=4.919000E-05 GAMMA=0.172

+ PHI=0.6 UO=594 UEXP=6.682275E-02 UCRIT=5000 + DELTA=5.08308 VMAX=65547.3 XJ=0.250000U LAMBDA=6.636197E-03

+ NFS=1.98E+11 NEFF=1 NSS=1.000000E+10 TPG=1.000000 + RSH=32.740000 CGDO=3.105345E-10 CGSO=3.105345E-10 CGBO=3.848530E-10

+ CJ=9.494900E-05 MJ=0.847099 CJSW=4.410100E-10 MJSW=0.334060 PB=0.800000 * Weff = Wdrawn - Delta_W

* The suggested Delta_W is -0.25 um .MODEL PMOS PMOS LEVEL=2 LD=0.227236U TOX=417.000008E-10

+ NSUB=1.056124E+16 VTO=-0.937048 KP=1.731000E-05 GAMMA=0.715 + PHI=0.6 UO=209 UEXP=0.233831 UCRIT=47509.9

+ DELTA=1.07179 VMAX=100000 XJ=0.250000U LAMBDA=4.391428E-02 + NFS=3.27E+11 NEFF=1.001 NSS=1.000000E+10 TPG=-1.000000

+ RSH=72.960000 CGDO=2.822585E-10 CGSO=2.822585E-10 CGBO=5.292375E-10 + CJ=3.224200E-04 MJ=0.584956 CJSW=2.979100E-10 MJSW=0.310807 PB=0.800000

* Weff = Wdrawn - Delta_W * The suggested Delta_W is -1.14 um

--------------------------------------------------------


6

Characteristic Curves for the NMOS Inverter Circuit

In order to begin analyzing the L-Edit NMOS inverter, you must have OrCAD 15.7 Demo installed (or a later, working variant). Next open OrCAD Capture CIS and create a new project using Analog / Mixed (A/D). After the project space is ready a design schematic should be built as shown in figure 3 below. Building a schematic is as simple as laying down parts and connecting the components with wire. The main PSpice parts/components we will use in this lab are (Rectangle acts as a virtual holder for the L-Edit NMOS inverter, VDC, VAC, VPULSE, 0Ground, C/ANALOG, R/ANALOG, and Net Alias). A rectangle was drawn to act as a virtual placeholder for the L-Edit NMOS inverter device. Once you have everything pieced together, and you have to place the correct net aliases consistent with the L-Edit NMOS inverter Gate, Drain, Substrate, and Source as in figure 3, you are ready to run a PSpice simulation. First, create a new simulation profile. You must include the L-Edit NMOS inverter “NMOS.SPC” (extracted) and modified “SCNA.SPC” (L-Edit directory) files by locating them and clicking “Add to Design” under the “Configuration Files” tab (figure 4). Next, set the simulation settings to use a DC Sweep, with a Primary Sweep of “Vdrain” from 0 V to 5 V in small 1 mV increments (figure 5), and a Secondary Sweep of “Vgate” from 0 V to 5 V in 1 V increments (figure 6). The result of this simulation is seen in figure 7.

Figure 3: PSpice circuit used for the L-Edit NMOS inverter Id-Vd curves.

Vgate5Vdc

Vdrain5Vdc

NMOS (Extracted) Device

W / L = 18 / 6

RS

1

Gate

Source

Drain

0

0 0

0

Substrate

Circuit used for generating the L-Edit NMOS

inverter (Id - Vd) curves.


7

Figure 4: PSpice Simulation Settings: Configuration Files requires for analyzing the L-Edit NMOS Inverter

in PSpice.

Figure 5: DC Sweep, Primary Sweep Config. Figure 6: DC Sweep, Secondary Sweep Config.


8

Figure 7: Characteristic curves for the L-Edit NMOS Inverter. (0-5 V Sweeps).

Noted in figure 7 above, the L-Edit NMOS inverter curves flattened out at larger Vdrain

voltages than the IRF-150 Power MOSFET curves (3 V NMOS vs. 2 V IRF-150 when

V_Vgate = 5 V) but at a much lower Vdrain currents (950 µA NMOS vs. 7 A IRF-150

when V_Vgate = 5 V).

V_Vdrain

0V 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V

-I(Vdrain)

0A

0.5mA

1.0mAI

D

r

a

i

n

Note: V_Vgate < 1V curve is not visible

than the IRF-150 curves.

also at much smaller currents

voltages than the IRF-150 curves but

Notice NMOS curves flatten out at larger

approx. (1 V, 2 A) vs L-Edit NMOS (2.4 V, 570 uA)

Note: Lab 3 IRF-150 curve at V_Vgate = 4 V flattened at

Note: Lab 3 IRF-150 curve at V_Vgate = 5 V flattened at

approx. (2 V, 7 A) vs L-Edit NMOS (3 V, 950 uA)

V_Vgate = 1 V

V_Vgate = 2 V

V_Vgate = 3 V

V_Vgate = 4 V

V_Vgate = 5 V

Secondary Sweep: Vgate (0-5 Vdc), 1 V increment

Primary Sweep: Vdrain (0-5 Vdc), .001 V increment

Characteristic Curves for the L-Edit NMOS Inverter


9

Voltage Transfer Function for the NMOS Inverter Circuit

To generate the voltage transfer function (Vout vs. Vin) of the L-Edit NMOS inverter, the circuit design was updated to include a 50 kΩ resister after the VDC source “Vdrain”, and a 1 pF capacitor after the 50 kΩ resister going to ground. Two net aliases “Vout” and “Vin” were then added until the circuit finally matched the circuit shown by figure 8. Next the circuit simulation settings were again adjusted. After the Secondary Sweep was removed, the Primary Sweep was updated to sweep “Vgate” from 0 V to 5 V in small 1mV increments (figure 9). The new simulation was run with the results shown by the bottom half of figure 10. You may need to add a trace of “V(Vout)” if you didn’t attach a voltage probe to Vout. Next, a line with a slope of 1 was drawn originating from (0 V, 0 V) to (3 V, 3 V). The intersection of this line with the voltage transfer function graph of V(Vout) was noted as the L-Edit NMOS inverters logic threshold or switching point. This threshold voltage is the point where Vin = Vout, and was determined to be approximately 1.8299 V (-27% of Ideal). The Ideal inverters Logic Threshold is VDD/2 – 0 = 2.5 V. The IRF-150 Power MOSFET’s logic threshold was approx 2.86 V (+15% of Ideal). Next a new plot was added to graph the slope (derivative) of “Vout” (Top half of figure 10). Creating a new plot is as simple as clicking plot/new plot and giving the new plot a trace (In this case d(V(Vout))). The points where the new slope = -1 are used to define the noise margins of this inverter. An easy way to find these locations is by using the search command and typing “search forward level(-1)”. Using this technique twice to find both locations where the slope = -1 the following could be defined. Once found you can identify the specific x-value with the “search forward xvalue(###)” command, where ### is the x-value you are searching for. After adding these coordinates the following data was obtained.

L-Edit NMOS Noise Margin Comparison Table

Noise Magin Comparison Parameter

Ideal Inverter

IRF-150 Inverter

NMOS Inverter

IRF-150 % error

(vs. Ideal)

NMOS % error

(vs. Ideal)

NMOS abs. diff in %

error (vs. IRF-150)

Logic Threshold or Switching Point 2.5 V 2.8682 V 1.8299 V +15% -27% 12% worse

VIH = minimum HIGH input voltage 2.5 V 2.8965 V 2.1214 V +16% -15% 1% better

VIL = maximum LOW input voltage 2.5 V 2.8311 V 941.732 mV +13% -62% 49% worse

VOH = minimum HIGH output voltage 5 V 4.9886 V 4.9105 V 0% -2% 2% worse

VOL = maximum LOW output voltage 0 V 32.908 mV 711.519 mV N/A N/A N/A

Noise Margin Low = NML = VIL – VOL 2.5 V 2.798 V 230 mV +12% -91% 79% worse

Noise Margin High = NMH = VOH – VIH 2.5 V 2.092 V 2.7891 V -16% 12% 4% better

Table 1: L-Edit NMOS Noise Margin Comparison Table, all percentages are rounded, last column is a

difference comparison of the IRF-150’s % error to ideal to the L-Edit NMOS inverter %error to ideal.


10

Figure 8: PSpice circuit for generating the L-Edit NMOS inverter voltage transfer function (Vout vs. Vin).

Notice the addition of R1 (50 kΩ), CL (1 pF), and Net Aliases Vout, and Vin.

Figure 9: PSpice simulation setup parameters for the NMOS inverter voltage transfer function.

Vgate5Vdc

Vdrain5Vdc


W / L = 18 / 6

RS

1

GateVin

Source

0

0 0

0

Substrate


inverter voltage transfer function (Vout vs. Vin)

R1

50k

CL

1pF

Vout

Drain

0


11

Figure 10: PSpice simulation results displaying voltage transfer characteristics of the L-Edit NMOS inverter

circuit. The top plot is a graph of the slope of V(Vout) the points where slope = -1 identify the points needed

to calculate the noise thresholds of the device. You can see from the graph of Vout vs. Vin that the L-Edit

NMOS NML is -91% of the Ideal NML (the IRF-150 was +12% of the Ideal NML), while the L-Edit NMOS

NMH is +12% of the Ideal NMH (the IRF-150 was -16% of the Ideal NML). So the while the L-Edit NMOS

inverters NMH is closer to the ideal (abs diff. of 4% better), the NML is much farther (abs diff. of 79% worse). This means the L-Edit NMOS inverter will work well for Logic (low) inputs < 941 mV and Logic (high)

inputs > 2.121 V. The IRF-150 Power MOSFET inverter worked well with Logic (low) inputs < 2.8311 V and

Logic (high) inputs > 2.8965 V.

Vin Vout

0 1

1 0

After analyzing figure 10 the truth table above (table 2) can be developed. It is obvious from this truth table that this circuit is acting as an inverter, although with a much lower NML than the IRF-150 Power MOSFET’s NML. A Vin < 941 mV (Low) results in a Vout of 4.91 V (High), while a Vin > 2.12 V (High) results in a Vout of 711 mV (Low).

V_Vgate

0V 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V

V(Vout)

0V

2.5V

5.0VV

o

u

t

SEL>>So.. NMH is approx +12% of Ideal, +33% of IRF-150

So.. NML is approx -91% of Ideal, -92% of IRF-150

Ideal NMH = 2.5 V, IRF-150 NMH = 2.092 V

Ideal NML = 2.5 V, IRF-150 NML = 2.798 V

NMOS NMH = Vout(high) - Vin(high) = 2.7891V

NMOS NML = Vin(low) - Vout(low) = 230mV

NMOS Voltage Transfer Function (Vout vs. Vin V_Vgate)

This is a simple strait line (slope = 1)

Vin (low), Vout (high)

Vin (high), Vout (low)

Logic Threshold or Switching Point

(2.1214,711.519m)

(941.732m,4.9105)

(1.8299,1.8299)

D(V(Vout))

-5.0

-2.5

0S

l

o

p

e Used for finding NML and NMH

These points determine Vin(low) and Vin(high)

Interesting points are where Slope = -1

Graph of V(Vout)'s Slope

Slope of V(Vout) = -1

Slope of V(Vout) = -1

(2.1214,-1.0000)

(941.732m,-1.0000)

Table 2: Truth table for the L-Edit NMOS inverter.


12

Power Consumption of the NMOS Inverter Circuit

Modifications to the circuit used in generating the voltage transfer function (figure 8) are not required (other than switching the V-probe at “Vout” for a W-probe at “Vdrain”) for finding the power consumed, nor are modifications to the simulation settings. By running a simulation using a W-probe at “Vdrain” the following results were obtained as shown by figure 11.

Figure 11: PSpice simulation results showing power consumed by the L-Edit NMOS inverter circuit.

As observed from figure 11, minimum power (24 pW) is consumed when the transistor is inverting an input (Vin) logic Low (0) into an output (Vout) logic High (1), however maximum power (481 µW) is consumed when the transistor is inverting an input (Vin) logic High (1) into an output (Vout) logic Low (0). The power consumed at Vin = 0 V is 24 pW, while the power consumed at Vin = 5 V is 481 µW. The IRF-150 consumed a minimum of 56 µW (2.3M times more power) to invert a low input into a high output, and consumed 25 mW (52 times more power) to invert a high input into a low output. A complex logic circuit composed of 2000 such NMOS inverters, where half have a logic 0, and the other half have a logic 1 could consume approx 481 mW of power (1000 * 24 pW + 1000 * 481 µW = 481 mW). This is much smaller (approx. 52 times less) than the power required for accomplishing this same feat using only IRF-150 inverters (requires approx. 25W). So for low power (digital) applications the NMOS inverter is much better suited as a logic inverter.

V_Vgate

0V 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 3.5V 4.0V 4.5V 5.0V

-W(Vdrain)

0W

250uW

500uWP

o

w

e

r

C

o

n

s

u

m

e

d

L-Edit NMOS Inverter

IRF-150 Max Power = 25 mW (52 times higher)

IRF-150 Min Power = 56 uW (2.3M times higher)

Max Power = 481uW

Min Power = 24pW

Power = 24pW

Power = 481uW

Power = 317uW

Power = 429uW

Power = 8.9uW

Minimum (High) Input voltage = 2.12 V

Maximum (Low) Input voltage = 942mV

(2.1214,428.848u)

(941.732m,8.9472u)

(5.0000,480.613u)

(0.000,24.255p)

Logic Threshold, Switching Point

Previously Determined

Power Consumed as a function of Vin

(1.8299,317.004u)


13

Small Signal Characteristics of the NMOS Inverter Circuit

In order to find the small signal characteristics of the L-Edit NMOS inverter, the VDC power source “Vgate” voltage was changed (see figure 12) to the threshold voltage determined by figure 11. Next circuit simulation settings were adjusted for Bias Point analysis, and the check box for calculating small-signal DC gain was checked. “Vgate” was used as the simulation input source and “V(Vout)” was provided as an Output variable name as illustrated in figure 13.

Figure 12: PSpice circuit used to find the small signal characteristics of the NMOS inverter.

Figure 13: PSpice simulation settings for finding small signal characteristics.

Vgate1.8299Vdc

Vdrain5Vdc


W / L = 18 / 6

RS

1

GateVin

Source

0

0 0

0

Substrate


inverter small signal characteristics.

Vgate is now at threshold voltage.

R1

50k

CL

1pF

Drain

Vout

0


14

Small data capture from the bottom of PSpice simulation output file… ---------------------------------------------------------------------------------------------------------------------

**** SMALL-SIGNAL CHARACTERISTICS

V(DRAIN)/V_Vgate = -5.730E+00 INPUT RESISTANCE AT V_Vgate = 1.000E+20

OUTPUT RESISTANCE AT V(DRAIN) = 4.792E+04

--------------------------------------------------------------------------------------------------------------------- So the gain is approximately 5.73 (IRF-150 gain was 113.7, 19.8 times lower), input resistance is approximately 100 EΩ (exa-ohms) or higher, due to PSpice limits (Same as IRF-150), and output resistance is approximately 47.92 kΩ (IRF-150 was 997.8 Ω, 48 times higher). At this point it seems that this circuit has a good gain, extremely high input impedance and low output impedance. So the IRF-150 Power MOSFET inverter circuit provides a higher gain than the L-Edit NMOS inverter circuit, with a smaller output resistance. One of the main contributors to this large output resistance is the 50 kΩ resister “R1” located after “Drain” (The IRF-150 circuit used a 1 kΩ resister).


15

Frequency Response of the NMOS Inverter Circuit

To find the frequency response of the circuit using the L-Edit NMOS Inverter a VAC source (with 1 VAC, and the threshold voltage VDC) was swapped for the VDC source “Vgate” as shown in figure 14. Simulation settings were then adjusted to provide a good bode plot diagram showing frequencies from 1Hz to 10GHz (plotted logarithmically) at 10 points per decade as shown by figure 15. The results shown by figure 16 indicated the circuit was behaving like a low pass filter with a corner (f * 3 dB) frequency of 2.426 MHz. You may need to add a trace of “DB(V(Vout))” This indicates that frequencies less than the corner frequency will respond better (larger gains realized) than frequencies greater than the corner frequency (less gain realized, until eventually the NMOS inverter is unable to keep up with the large frequencies and is non-functional.

Figure 14: PSpice circuit used for finding the NMOS circuits frequency response.

Figure 15: PSpice simulation settings for creating a bode plot of the circuit’s frequency response.

Vdrain5Vdc


W / L = 18 / 6

RS

1

GateVin

Source

0

0 0

0

Substrate

Circuit used for finding the L-Edit NMOS

inverter frequency response. Vgate is now

a VAC source (1 VAC) at threshold DC voltage.

R1

50k

CL

1pF

Drain

Vout

0

V11Vac

1.8299Vdc


16

Figure 16: PSpice simulation results (bode plot) of circuits frequency response. Corner freq = 2.4262 MHz

(43 times the value of the IRF-150’s corner freq.). You should observe that frequencies below 1.3 MHz

receive great gain and allow the IRF-150 switching speeds to approximate that of an ideal inverter.

You can see from the results displayed in figure 16 the L-Edit NMOS inverter has a larger cutoff

frequency than the IRF-150 Power MOSFET inverter (Approx 2.43 MHz vs. 56 kHz). This

allows the NMOS inverter to work in a much larger, although still limited (frequencies in the

GHz range, are widely used today) realm of engineering circuits. This fact tied together with the

power consumption requirements of the NMOS circuit vs. IRF-150 make the NMOS design a

sure win over the IRF-150 in the realm of low power digital circuitry. However, it pales in

comparison to a CMOS inverter, especially in the power consumption category.

Frequency

1.0Hz 10Hz 100Hz 1.0KHz 10KHz 100KHz 1.0MHz 10MHz 100MHz 1.0GHz 10GHz

DB(V(Vout))

-50

0

50V

g

a

i

n

(

d

B

)

IRF-150 Corner Freq. = 56.410 kHz (43 times less )

Note: The NMOS inverter acts like a LP Filter (Approx -14dB / decade)

10 * f( 3 dB ) = 24.26 MHz

.1 * f( 3 dB ) = 242.6 kHz

f( 3 dB ) = 2.426MHz

frequency response

Bode plot for L-Edit NMOS inverter

Estimation of Corner Freq. = 2.426 MHz

and the voltage gain is reduced .707 of max

the power out is reduced to 1/2 of max

This is the frequency at which

Corner Frequency (Max -3 dB)

Will check this out at later time.

Max freq. is the frequency where Vout reaches 90% of Vdd (4.5 V)

This was found by adding seperate Vout trace

Estimation of Max Freq. = 1.376 MHz

(1.3757M,13.064)

(2.4262M,12.164)


17

Propagation Delays of the NMOS Inverter Circuit

The circuit was again modified by replacing the VAC source “Vgate” with a Vpulse source as shown by figure 17. This figure was used in conjunction with the variable values used in table 3 for analyzing the circuits propagation delay (current) and digital frequency response (upcoming) sections of this report. For each simulation a Time Domain Analysis was performed to allow the user to see 3 to 5 periods (run to time = 3 to 5 * PER), and step size < 1/1000 (I used 1ps for simplicity) of each period as shown by figure 18. Simulation results are shown on figure 19.

Figure 17: PSpice circuit for finding the L-Edit NMOS inverter circuits propagation delays and digital

frequency response at f( 3 dB ), .1 * f( 3 dB ), 10 * f( 3 dB ). V1 = 0, V2 = 5, TD = 0, and TR/TF/PW/PER

come from Table ?.

Vpulse : Variables used for NMOS PSpice schematic

Frequency (Hz) Period

(PER) (s)

Pulse Width

(PW) (s)

Time-Rise &

Time-Fall (TR & TF)

(s)

f3db = 2.426 MHz 412.2 ns 206.1 ns 1 ps

.1 * f3db = 242.6 kHz 4.122 µs 2.061 µs 1 ps

10 * f3db = 24.26 MHz 41.22 ns 20.61 ns 1 ps

Table 3: Variables used by PSpice circuit figure 17.

Vdrain5Vdc


W / L = 18 / 6

RS

1

GateVin

Source

0

0 0

0

Substrate

Circuit used for finding the L-Edit NMOS

inverter digital frequency response and

propagation delays. Vgate is now a Vpulse

source (TR, TF, PW, PER) are set using table.

R1

50k

CL

1pF

Drain

Vout

0

VgateTD = 0

TF = 1psPW = 206.1nsPER = 412.2ns

V1 = 0

TR = 1ps

V2 = 5

V


18

Figure 18: PSpice simulation settings for finding the NMOS inverter propagation delays and digital

responses. Run to times should be 3-5 * PER, and step size should be = TR / TF.

Figure 19: PSpice simulation results showing rise time, fall time and propagation delays of circuit at input

freq. = 2.426 MHz = f(3dB).

Time

600ns 650ns 700ns 750ns 800ns 850ns

V(Vout)

0V

2.5V

5.0VV

o

l

t

a

g

e

This result is not always very accurate

Max Switching Freq = 8.392 MHz

tP (Prop Delay Time) = 18.859 ns

prop. delay (HL) = 2.742 ns

prop. delay (LH) = 34.976 ns

t(HL) fall = 7.298 ns

t(LH) rise = 111.861 ns

Frequency = f(3dB) = 2.426 MHz

Rise / Fall Times and Propagation Delays

tp(HL) = time to fall from 5 to 2.5V

tp(LH) = time to rise from 0 to 2.5V

.1 Vdd

.9 Vdd to.1 Vdd to .9 Vdd

t(LH) riset(HL) fall

Capacitance

Parasitic

(840.000n,206.254m)

(832.169n,500.000m)

(827.142n,2.5000)

(824.871n,4.5000)

(824.400n,4.9140)

(735.402n,4.5000)

(653.454n,2.5000)

(623.541n,500.000m)

(618.478n,10.673m)


19

From the results obtained by figure 19 above we can calculate the following (table 4).. Note a small %error in tPHL and tPLH may be the parasitic capacitance and resistance of the

NMOS inverter.

NMOS Inverter Rise/Fall Times and Propagation Delay Comparison Parameter Ideal IRF-150 NMOS

tHL = the time it takes output voltage to drop from 4.5 V to .5 V 0 s 21 ns 7.3 ns

tLH = the time it takes output voltage to rise from .5 V to 4.5 V 0 s 4.453 µs 111.9 ns

tPLH = the time it takes output voltage to rise from 0 to 2.5 V 0 s 1.774 µs 35ns

tPHL = the time it takes output voltage to fall from 5 V to 2.5 V 0 s 13 ns 2.7 ns

tP = Propagation delay time = .5 * ( tPLH + tPHL ) 0 s 831 ns 18.9 ns

Max Switching Frequency (calculated) = 1/( tLH + tHL ) *Note: Calculated result is usually far off from actual result.

∞ 223.5 kHz 8.389 MHz

Max Switching Frequency (observed/actual) ∞ 100 kHz Not yet

known at this point.

Table 4: NMOS Inverter Rise/Fall times and Propagation Delay Comparisons.

From figure 19 and table 4’s results, the NMOS circuit’s propagation delays and rise/fall times are much smaller than the IRF-150’s propagation delays and rise/fall times. This further stakes the previous claim, that the NMOS inverter circuit is the better inverter to utilize, for high frequency, low power (digital) applications.


20

Digital Frequency Response of the NMOS Inverter Circuit

Now the NMOS inverter circuits digital response is analyzed using the circuit from the previous section (figure 17) and substituting for the frequencies provided by table 3. The digital response is checked first at the corner frequency of 2.426 MHz (as done previously), then at 242.6 kHz, and finally at 24.26 MHz. The results follow (Note, you will need to read the captions next to each figure for an understanding of the results)…

Figure 20: PSpice simulation results showing digital response of output at frequency of 2.426 MHz. Note the

red is the input square pulse (Vin), and the green is the output inverted response (Vout). This is acting as an

OK inverter since the output reaches over 90% of the operating range within a pulse width, however this

response should improve with a lower input frequency. It is noted that the NMOS low is approx .2 V not 0 V.

Figure 21: PSpice simulation results showing digital response of output at frequency of 242.6 kHz (.1 *

corner). Notice the digital response is much cleaner now and is nearly that of an ideal inverter.

Time

0.20us 0.40us 0.60us 0.80us 1.00us 1.20us 1.40us 1.60us 1.80us0.03us

V(Vout) V(Vin)

0V

2.5V

5.0VV

o

l

t

a

g

e

Frequency = f(3dB) = 2.426 MHz(890.939n,5.0000)

(716.852n,0.000)

(411.409n,4.9116)

(206.102n,14.327m)

Time

2us 4us 6us 8us 10us 12us 14us 16us 18us 19us

V(DRAIN) V(GATE)

0V

2.5V

5.0VV

o

l

t

a

g

e

Frequency = .1 * f(3dB) = 242.6 kHz

(11.519u,0.000)

(9.2857u,5.0000)

(8.9559u,197.820m)

(5.2831u,197.759m)

(3.1393u,5.0000)


21

Figure 22: PSpice simulation results showing digital response of output at frequency of 24.26 MHz (10 *

corner). Notice the digital response is horrible now. The NMOS inverter simply cannot switch fast enough to

follow the input signal. This is now a non-functional inverter.

As observed from figures 20 thru 22 above, the lower the frequency is with respect to the corner frequency the better the NMOS inverter circuit performs. As the frequencies increase much higher than the corner frequency, the NMOS inverter cannot switch fast enough to follow the input signal (the rising edge time constant is too long per the switching speed.). This is mostly due to the large (50 k) load resistance and partially due to the internal capacitance of the NMOS inverter. However, as already stated, the NMOS inverter performs as a digital logic inverter much better than the IRF-150 Power MOSFET. The NMOS inverter can work with higher frequencies, requires a lot less power, and switches much faster.

Time

40.0ns 60.0ns 80.0ns 100.0ns 120.0ns 140.0ns 160.0ns 180.0ns20.5ns

V(DRAIN) V(GATE)

0V

2.5V

5.0VV

o

l

t

a

g

e

Frequency = 10 * f(3dB) = 24.26 MHz

(78.702n,0.000)

(48.514n,5.0000)

(59.332n,198.101m)

41.366n,1.6905)


22

Maximum Frequency of the NMOS Inverter

The maximum frequency is the frequency at which the output just reaches 90% or 10% of the operating range within a pulse width. Finding the maximum frequency is done through a little trial and error. Using the corner frequency as a starting position the frequency was incrementally increased until the output reached 90% of VDD = 4.5 V. This was found to be approximately 4.3 MHz, as shown in figure 23 below. The components that limit the frequency response of the NMOS inverter circuit are the circuit and NMOS device resistances, and the circuit 1pF and NMOS parasitic capacitances.

Figure 23: PSpice simulation results of testing freq. = 4.3 MHz as maximum frequency. Notice output

reaches approx 4.5 V (90% of 5 V).

Time

100ns 120ns 140ns 160ns 180ns 200ns 220ns 240ns 260ns

V(DRAIN)

0V

2.5V

5.0VV

o

l

t

a

g

e

Frequency = 4.3 MHz

By slowly increasing frequencies this freq. was found

Output reaches approx. 90% of operating range

Approximation of Max Frequency Response

Approx 4.5V -> 90% of 5V

(232.514n,4.5129)


23

LAB 4: Summary of Results

Evaluation Procedure

Parameter Ideal

Inverter

IRF-150 Inverter Circuit

NMOS Inverter Circuit

Winner IRF-150 vs NMOS Circuit

Transfer Char. VThreshold 2.5 V 2.8682 V 1.8299 V IRF-150

Noise Margins

NMH 2.5 V 2.092 V 2.7891 V IRF-150

NML 2.5 V 2.798 V 230 mV IRF-150

Power

P @ 0 V 0 W 56 µW 24 pW NMOS

P @ 5 V 0 W 25 mW 481 uW NMOS

PMax 0 W 25 mW 481 uW NMOS

Rise Time tLH 0 s 4.453 µs 111.9 ns NMOS

Fall Time tHL 0 s 21 ns 7.3 ns NMOS

Propagation Delays

tPHL 0 s 13 ns 2.7 ns NMOS

tPLH 0 s 1.774 µs 35 ns NMOS

tP 0 s 831 ns 18.9 ns NMOS

Small Signal Gain Av ∞ 113.7 5.73 IRF-150

Impedances Rin ∞ ∞ ∞ Tie

Rout 0 997.8 Ω 47.92 kΩ IRF-150

3dB Corner Frequency

f3dB N/A 56.23 kHz 2.4262

MHz NMOS

Maximum Frequency

fMax ∞ 100 kHz 4.3 MHz NMOS

Table 5: Summary of results for Lab 4


24

Conclusion and Recommendations

As mentioned in previous sections for an ideal inverter (VIL=VIH=Vdd/2=2.5 V, VOH = Vdd=5 V, VOL=0 V, Noise margins = 2.5 V) and as displayed in the tables above, the NMOS inverter circuit NML is -91% of the Ideal NML (The IRF-150 is +12% of the Ideal NML), while the NMOS inverter circuit’s NMH is +12% of the Ideal NMH (The IRF-150 is -16% of the Ideal NMH). Furthermore, the NMOS inverter circuit has a voltage threshold of 1.8299 V while the IRF-150 Power MOSFET circuit had a Voltage Threshold of 2.8682 V. In addition, the IRF-150 circuit design had a small signal output impedance of 997.8 Ω (due to the small 1 kΩ

output resister), while the NMOS design had a small signal output impedance of 47.92 kΩ (due to

the large 50 kΩ output resister). These numbers initially suggested that the IRF-150 was a better choice as an inverter due to closer realization of an ideal switching point. However, by the end of the lab the additional analysis and comparison of the NMOS inverter against the IRF-150 circuit revealed a completely different story (on numerous levels). First, and of great importance, the IRF-150 is a Power MOSFET and demands much larger amounts of power than the NMOS inverter circuit. The IRF-150 consumed a minimum of 56 µW (2.3M times more power than the NMOS) to invert a low input into a high output, and consumed 25 mW (52 times more power than the NMOS) to invert a high input into a low output. This is a tremendous loss for the IRF-150, since power is of the utmost importance in today’s digital world. However the IRF-150 also provides a much larger gain than the NMOS circuit (113.7 vs. 5.73). This is another reason why the IRF-150 is a Power MOSFET. Last but not least, the IRF-150 circuit’s rise/fall times, and propagation delay times are much slower than the NMOS circuit’s. This means the IRF-150 switches too slow to act as a sufficient inverter at high frequency applications. While the NMOS circuit was also not a beast in this area, the NMOS circuit could handle maximum frequencies 43 times that of the IRF-150 Power MOSFET circuit. In summary, the IRF-150 design from lab 3 is insufficient as a high frequency, low power, large scale, digital inverter when up against the NMOS design. In such cases the NMOS inverter wins hands down.

Ee325 cmos design lab 4 report - loren k schwappach

Technology

Transcript of Ee325 cmos design lab 4 report - loren k schwappach