EE241B : Advanced Digital Circuitsinst.eecs.berkeley.edu/~ee241/sp20/Lectures/Lecture9... ·...
Transcript of EE241B : Advanced Digital Circuitsinst.eecs.berkeley.edu/~ee241/sp20/Lectures/Lecture9... ·...
inst.eecs.berkeley.edu/~ee241b
Borivoje Nikolić
EE241B : Advanced Digital Circuits
Lecture 9 – Timing
February 14, 2020, EETimes: Five Chip
Companies Hold 53% of Global Wafer Capacity
An increasing percentage of
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the largest producers.
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Announcements
• Project abstracts due today, by e-mail• Teams of 2
• Title
• One paragraph
• 5 relevant references
• Can also combine with CS252 or EE290 projects
• Quiz 1 on Tuesday, Feb 25, in class
• Office hour moved to 11am on Monday
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Outline
• ISSCC recap
• Module 2• Technology variability
• Module 3• Flip-flop timing
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2.P Design VariabilitySome Random Effects
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Negative Bias Temperature Instability
• PFET VTh’s shift in time, at high negative bias and elevated temperatures
• The mechanism is thought to be the breaking of hydrogen-silicon bonds at the Si/SiO2 interface, creating surface traps and injecting positive hydrogen-related species into the oxide.
• Also other charge trapping and hot-carrier defect generation
• Systematic + random shifts
Tsujikawa, IRPS’2003EECS241B L09 FLIP-FLOP TIMING 18
Random Telegraph Signal (RTS)
• Trapping of a carrier in oxide traps modulates Vth or Ids
• τe and τc are random and follow exponential distributions
Single Hole Trap Multiple Hole Trap
N. Tega et al, IRPS 2008.
τcτe
Capture
Emit
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-4-3-2-101234
1 10 100
CD
F (σ
)∆Vth (mV)
RTSRDF
RTS and Technology Scaling
• RTS exceeds RDF at 3 sigma with 20nm gates
Tega et. al, VLSI Tech. 09
L/W = 20/45nm
WL1
ΔVth, RTS~
WL1
ΔVth, RDF~
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3. Design for Performance
3.A Flip-Flop Timing
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Flip-Flop Parameters
D
Clk
Q
D
Q
Clk
TCQ
TH
PWm
TSU
Delays can be different for rising and falling data transitions
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Latch Parameters
D
Clk
Q
D
Q
Clk
TCQ
TH
PWm TSU
TDQ
Delays can be different for rising and falling data transitions
Unger and TanTrans. on Comp.10/86
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EXAMPLE CLOCK SYSTEM
Courtesy of IEEE Press, New York. 2000
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Clock Nonidealities
• Clock skew• Spatial variation in temporally equivalent clock edges; deterministic + random, tSK
• Clock jitter• Temporal variations in consecutive edges of the clock signal; modulation + random noise
• Cycle-to-cycle (short-term) - tJS• Long-term - tJL
• Variation of the pulse width • for level-sensitive clocking
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Clock Skew and Jitter
• Both skew and jitter affect the effective cycle time
• Only skew affects the race margin, if jitter is from the source• Distribution-induced jitter affects both
Clk1
Clk2
tSK
tJS
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Clock Uncertainties
2
43
Power Supply
Interconnect
5 Temperature
6 Capacitive Load
7 Coupling to Adjacent Lines
1 Clock Generation
Devices
Sources of clock uncertainty
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Clock Constraints in Edge-Triggered Systems
Courtesy of IEEE Press, New York. 2000EECS241B L09 FLIP-FLOP TIMING 28
3.B Timing with Uncertainty/Variations
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Pictorial View of Setup and Hold Tests
0 or moreswitching(s)allowed
Latest clock arrival time Earliest clock arrival time(next cycle)
Data must be stable
Hold time
Early RAT
Data must be stable
Setup time
Late RAT
Actual early AT Actual late AT
Earlyslack
Lateslack
ICCAD '07 Tutorial Chandu VisweswariahEECS241B L09 FLIP-FLOP TIMING 30
LF CF
Hold test
Handling of Across-Chip Variation
• Each gate has a range of delay: [lb, ub]• The lower bound is used for early timing• The upper bound is used for late timing
• This is called an early/late split
• Static timing obtains bounds on timing slacks• Timing is performed as one forward pass and one backward pass
LF CF
Setup test
Capturing early path
Launching late path
Capturing late path
Launching early path
ICCAD '07 Tutorial Chandu VisweswariahEECS241B L09 FLIP-FLOP TIMING 31
How is the Early/Late Split Computed?
• The best way is to take known effects into account during characterization of library cells• History effect, simultaneous switching, pre-charging of internal nodes, etc.• This drives separate characterization for early and late; this is the most accurate method
• Failing that, the most common method is derating factors• Example: Late delay = library delay * 1.05
Early delay = library delay * 0.95• The IBM way of achieving derating is LCD factors (Linear Combination of Delay) (FC=fast
chip, SC=slow chip, see next page)• Late delay = L * FC_delay + L * NOM_delay + L * SC_delay
Early delay = E * FC_delay + E * NOM_delay + E * SC_delay• Across-chip variation is therefore assumed to be a fixed proportion of chip-to-chip
variation for each cell type
ICCAD '07 Tutorial Chandu VisweswariahEECS241B L09 FLIP-FLOP TIMING 32
IBM Delay Modeling*
Intrinsic:Chip means
SystematicACV
RandomACV
Early Late Early Late
*P. S. Zuchowski, ICCAD’04
At a given cornerlate delay = intrinsic + systematic + randomearly delay = intrinsic – systematic – random
ICCAD '07 Tutorial Chandu VisweswariahEECS241B L09 FLIP-FLOP TIMING 33
Traditional Timing Corners
Fast
chi
p ea
rly
Fast
chi
p la
te
Intra-chip variation
Slow
chi
p ea
rly
Slow
chi
p la
te
Intra-chip variation
Chip-to-chip variation
Fast chip Slow chip
ICCAD '07 Tutorial Chandu VisweswariahEECS241B L09 FLIP-FLOP TIMING 34
The Problem with an Early/Late Split
• The early/late split is very useful• Allows bounds during delay modeling• Any unknown or hard-to-model effect can be swept under the rug of an
early/late split• But, it has problems
• Additional pessimism (which may be desirable)• Unnecessary pessimism (which is never desirable)
LF CF
Setup test
Capturing early path
Launching late path
This physically commonportion can’t be both fastand slow at the same time
ICCAD '07 Tutorial Chandu VisweswariahEECS241B L09 FLIP-FLOP TIMING 35
How to Have Less Pessimism?
• Common path pessimism removal
• Account for correlations
• Credit for statistical averaging of random
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Statistical Timing
• Deterministic
• Statistical
a
b
c++ MAX
b
a
c++ MAX
ICCAD '07 Tutorial Chandu VisweswariahEECS241B L09 FLIP-FLOP TIMING 37
Statistical Max Operation
*C. E. Clark, “The greatest of a finite set of random variables,” OR Journal, March-April 1961, pp. 145—162**M. Cain, “The moment-generating function of the minimum of bivariate normal random variables,” American Statistician, May ’94, 48(2)
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Unified View of Correlations
Independentlyrandom part
Spatially correlated part:within-chip distance-related correlation
Globally correlated part: chip-to-chip, wafer-to-wafer, batch-to-batch variation
1
0 Distance
Correlation Coefficient
Rrii XaXaaD 0
ICCAD '07 Tutorial Chandu VisweswariahEECS241B L09 FLIP-FLOP TIMING 39
Spatial Correlation vs. Early/Late Split
LF1 LF2 CFLF3
early clock
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Dependence on common virtual variables cancels out at the timing testICCAD '07 Tutorial Chandu VisweswariahEECS241B L09 FLIP-FLOP TIMING 40
Next Lecture
• Latch-based timing
• Flip-flops
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