1

EE241 - Spring 2005Advanced Digital Integrated Circuits

Lectures 4 and 5:Delay Modeling

2

ISSCC 2005

Keynotes (Monday Morning)Nanoelectronics for the Ubiquitous Information Society, Daeje Chin, Minister of Information and Communications, Korea

Ambient Intelligence: Broad Dreams and NanoscaleRealities, Hugo De Man, IMEC, Katholieke Universiteit Leuven, Belgium

Innovation and Integration in the Nanoelectronics Era, SunlinChou, Intel, Hillsboro, OR

Interesting Short Courses (on Su)Memory forum

“When processors hit the power wall”

3d Integration

2

3

Interesting SessionsMo

Non-Volatile MemoriesMultimedia Processing

TuHigh-speed links and clock generatorsMicroprocessors and Signal processingLow-Power wireless and advanced integrationClock distribution and power controlHigh-speed interconnects and building blocks

WeProcessor building blocksPLL, DLL and VCO’sDRAMSRAMClocking and I/O

4

Some other stuff

Panels:Mo: Towards the Nanoscale transistor

Tu: SRAM Design in the Nanoscale Era

Th Circuit Design ForumRobust Design for Nanoscale circuits

3

5

Projects

Projects info –Target benchmark: ultra low-power 8051 microcontroller (and its components)

Some interesting projects:

Ultra low-power clock dividers/multipliers

Sub-threshold design versus low-threshold design

Low-current voltage converters/multipliers

Design techniques for self-calibration

Energy recovery and reversible computing

The return of “current-driven logic”

Error-resilient circuits and architectures

Small-granularity self-timing / asynchronous

Device Models

4

7

K(VGS –VTHZ) Model

Drain current vs. gate-source voltage

0.0E+00

2.0E-04

4.0E-04

6.0E-04

8.0E-04

0 0.2 0.4 0.6 0.8 1 1.2

V GS [V]

I DS

[A

]

VTHZ

8

Transistor Leakage

-9

-8

-7

-6

-5

-4

-3

0 0.2 0.4 0.6 0.8 1 1.2

V GS [V]

log

I DS

[lo

g A

]

Subthreshold slope

Leakage current is exponential with VGS

VDS = 1.2V

5

9

Transistor Leakage

10

Transistor Leakage

Two effects:• diffusion current (like a bipolar transistor)• exponential increase with VDS (DIBL)

0

2

4

6

8

0 0.2 0.4 0.6 0.8 1 1.2 1.4

V DS [V]

I DS

[nA

]

6

11

Subthreshold Current

Subthreshold behavior can be modeled physically

⎟⎟⎟

⎠

⎞

⎜⎜⎜

⎝

⎛−⎟⎟

⎠

⎞⎜⎜⎝

⎛µ=

−−

qkT

Vds

qkTmThVgV

ds eeq

kT

L

WI 1

2

( )S

dsVThVgsV

ds W

WII

γ+−

= 100

0

Or: [Taur, Ning]

12

Leakage Components

Courtesy of IEEE Press, New York. © 2000

7

13

Leakage Components

1. pn junction reverse bias current

2. Weak inversion

3. Drain-induced barrier lowering (DIBL)

4. Gate-induced drain leakage (GIDL)

5. Punchthrough

6. Narrow width effect

7. Gate oxide tunneling

8. Hot carrier injection

14

Leakage Components

Drain-induced barrier lowering (DIBL)Voltage at the drain lowers the source potential barrier

Lowers VTh, no change on S

Gate-induced drain leakage (GIDL)High field between gate and drain increases injection of carriers into substrate -> leakage (band-to-band leakage)

8

15

DIBL, GIDL, Weak Inversion

Courtesy of IEEE Press, New York. © 2000

16

Stack Effect

NAND gate:

Reduction:

Courtesy of IEEE Press, New York. © 2000

9

17

MOS Transistor as a Switch

Discharging a capacitor

• Can solve:

( )DSDD vii =

dt

dVCi DS

D =

• Prefer using equivalentresistances

18

MOS Transistor as a SwitchTraversed path

10

19

MOS Transistor as a Switch

Solving the integral:

Averaging resistances:

with appropriately calculated Idsat

20

Equivalent Resistance

W/L=1, L=0.25µ

11

21

CMOS Performance

Propagation delay: ( ) LeqnpHL CRt 2ln= ( ) LeqppLH CRt 2ln=

Short channel Long channel

)( DDeq VfR ≠DD

eq VR

1∝

TDD VV >>for

ln2 = 0.7

22

MOS Capacitances

CGSO = CGDO

= CoxxdW

= CoW

Gate Capacitance

Overlap Capacitance

12

23

MOS Capacitances

Gate capacitanceNon-linear channel capacitance

Linear overlap, fringing capacitances

Miller effect on overlap capacitance

Non-linear drain diffusion capacitancePN junction

Wiring capacitancesLinear

24

Gate Capacitance

13

25

MOS Capacitances

0.25µm process

26

Gate and Drain Capacitances

0.13um Cdb/um vs. Vds

0.00E+00

2.00E-16

4.00E-16

6.00E-16

8.00E-16

1.00E-15

1.20E-15

1.40E-15

1.60E-15

1.80E-15

2.00E-15

0.0 0.4 0.8 1.2

Vds (V)

Cdb

(F

)

NMOS VGS=0

PMOS VGS=0

Gate capacitance Drain Capacitance

0.13um Cgs/um vs. Vgs

0.0E+00

2.0E-16

4.0E-16

6.0E-16

8.0E-16

1.0E-15

1.2E-15

1.4E-15

1.6E-15

1.8E-15

2.0E-15

0.0 0.4 0.8 1.2

Vgs [V]

Cgs

[F]

NMOS VDS=VDD

PMOS VDS=VDD

NMOS VDS=0

PMOS VDS=0

14

27

Gate Capacitances

Gate capacitance is non-linearFirst order approximation with CoxWL (CoxL = 2fF/µm)This is an overestimation

Need to find the actual equivalent capacitance by simulating itSince this is a linear approximation of non-linear function, it is valid only over the certain range

Different capacitances for HL, LH transitions and power computation

Drain capacitance non-linearity compensatesBut this changes with fanout

28

Gate Capacitance vs. VTh, VDD

Nose, Sakurai, ISLPED’00

15

29

FO4 Inverter Delay

In

tpShapes the input slope to FO4

FO4 load Suppresses Millerkickback

30

Calibrating Delays

Step RC delay model is a good first-order approximation

Accuracy can be improved by including:Slope effects

Non-linear capacitive loading

Signal arrival times

Wire models

16

31

Input Slope

Simulated vs. linear model

0

10

20

30

40

50

60

70

0 2 4 6 8 10

FanOut

Del

ay [

ps]

8

4

1

Driving gatefanout

32

Input slope

We can model the delay as tp = 0.7*RekvCWhen driving with non-step input, the rise/fall time is absorbed into Rekv

Rekv is different than one extracted straight from I-V

The output delay is linearly dependent on input rise/fall time tp = 0.7RC + ηtS

η = 0.17 in this example (~1/6)The model is limited to a range of fanouts

More accurate delay models propagate two quantities: delay and signal slope

Both can be modeled either as linear or table lookups

17

33

Standard Cell LibraryContains for each cell:

Functional information: cell = a *b * c

Timing information: function of

input slew

intrinsic delay

output capacitance

non-linear models used in tabular approach

Physical footprint (area)

Power characteristics

Wire-load models - function ofBlock size

Fan-out

Library

[from K. Keutzer]

34

Synopsys Delay Models

Linear (CMOS2) delay model

18

35

Example Cell Timing

36

Delay Dependency on Edge Rate

19

37

Transition Time

Linear: Piecewiselinear:

38

Cell Characterization

20

39

Synopsys Nonlinear Delay Model

Delay is a function of:

40

Synopsys Nonlinear Delay Model

21

41

Static Timing Analysis

clk

Combinationallogic

clk

Combinationallogic

clk

Combinationallogic

original circuit

extracted block

Combinationallogic

[from K. Keutzer]

42

Each Combinational Block

Arrival time in green A

C

B

f

2

2

2

1

0

1

0

.20.20

.20

.10

X

YZ

W

.15

.05

.05

.05

Interconnect delay in red

Gate delay in blue

What’s the right mathematical object to use to represent this physical object?

[from K. Keutzer]

22

43

Problem formulation - 1

C

B

f

X

Y

W

0

.05.1

1

.2

0

0

1

A

.15.20

.20

A

C

B

f

2

2

2

1

0

1

0

.20.20

.20

.10

X

YZ

W

.15

.05

.05

.05

12

2

2

Z

Use a labeled directed graph

G = <V,E>

Vertices represent gates, primary inputs and primary outputs

Edges represent wires

Labels represent delays

Now what do we do with this?

[from K. Keutzer]

44

Problem formulation - Arrival Time

Arrival time A(v) for a node v is time when signal arrives at node v

uu

A( ) max (A(u) d )→υ∈ υ

υ = +FI( )

X

Y

A(Z)

Z

x zd →

Y zd →

A(X)

A(Y)

where d is delay from to andu u, {X,Y}, {Z}.υ→ υ υ FI(υ) = =

[from K. Keutzer]

23

45

Static Timing Analysis

Computing critical (longest) path delayLongest path algorithm on DAG [Kirkpatrick, IBM Jo. R&D, 1966]

Used in most ASIC designs today

LimitationsFalse paths

Simultaneous arrival times

46

Signal Arrival Times

NAND gate:

1

24

47

Signal Arrival Times

NAND gate:

1

48

Simultaneous Arrival Times

NAND gate:

25

49

Impact of Arrival Times

A

B

Delay

0 tA - tB

A arrives early B arrives early

Up to 25%

50

Optimization for Performance

Performance critical blocks

Start with a synthesized designEasier to explore architectures

Easy to verify

Provides some level of performance optimization

Understand the limits of synthesized designs

26

51

Optimization for Performance

Options• Technology choice

CMOS, bipolar, BiCMOS, GaAs, Superconducting• Logic level optimizations

logic depth, network topology, fan-out, gate complexity• Circuit optimizations

logic style, transistor sizing• Physical optimization

implementation choice, layout strategy

• Do not ignore wiring!!

52

Logic Level Optimizations

R R

Logic Depth

or

Techniques: Restructuring, pipelining, retiming, technology mapping

Well covered by today’s logic and sequential synthesis

27

53

Logic Optimizations (2)

Technique: Removal of common sub-expressionStart from tree structure/output

Fanout

Tp = O(FO) also effects wiring capacitance

Late arriving

54

Logic Optimizations (3)

1 3 5 7 9fan-in

0.0

1.0

2.0

3.0

4.0

t p(n

sec)

tpHL

tp

tpLHlinear

quadratic

AVOID LARGE FAN-IN GATES! (Typically not more than FI < 4)

Tp = O(FI2) !Observation: only true if FI

translates in series devices -

otherwise linear

e.g. NAND pull-down

NOR pull-up

Fanin

28

55

Logic Optimizations (4)

Fan-out

t p(p

sec)

t

1 2 3 4 5 6 7

pINVtpNAND

F(Fan-in)

Slope is a function of “driving strength”

pNORt

All the gates have the same drive current

56

Technology Mapping for Performance

Alternative coverings

Use low FI modules on critical path(s)Library composition?