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Transcript of EE2174: Digital Logic and Lab Professor Shiyan Hu Department of Electrical and Computer Engineering...
EE2174: Digital Logic EE2174: Digital Logic and Laband Lab
Professor Shiyan HuProfessor Shiyan Hu
Department of Electrical and Computer Department of Electrical and Computer EngineeringEngineering
Michigan Technological UniversityMichigan Technological University
CHAPTER 8CHAPTER 8
ArithmeticArithmetic
Apr 18, 2023
PJF - 2Arithmetic
OverviewOverview
Binary AdditionBinary Addition Complement formsComplement forms SubtractionSubtraction MultiplicationMultiplication
Objectives of This LectureObjectives of This Lecture
What have we learned?What have we learned? Combinational Circuit BasicsCombinational Circuit Basics Three Design MethodologiesThree Design Methodologies
What are we going to learn?What are we going to learn? Applying the above knowledge to design Applying the above knowledge to design
AdderAdder This is the most fundamental arithmetic This is the most fundamental arithmetic
module designmodule design
Apr 18, 2023
PJF - 3Arithmetic
Apr 18, 2023
PJF - 4Arithmetic
1-bit Addison1-bit Addison Performs the addition of two binary bits.Performs the addition of two binary bits. Four possible operations:Four possible operations:
0+0=0+0=00 0+1=0+1=11 1+0=1+0=11 1+1=1+1=1100
Circuit implementation requires 2 outputs, Circuit implementation requires 2 outputs, one to indicate the one to indicate the sumsum and the other to and the other to indicate indicate carrycarry..
Apr 18, 2023
PJF - 5Arithmetic
Half Adder: DefinitionHalf Adder: Definition A half adder is to perform a A half adder is to perform a
1-bit addition. 1-bit addition. Inputs: AInputs: A00, B, B00
Outputs: SOutputs: S00, C, C11
Index indicates Index indicates significance, significance, 0 is for LSB and 1 is for the 0 is for LSB and 1 is for the next higher significant bit.next higher significant bit.
Boolean equations:Boolean equations: SS00 = A = A00 B B00
CC11 = A = A00BB00
AA00 BB00 SS00 CC
11
00 00 00 00
00 11 11 00
11 00 11 00
11 11 00 11
Truth Table
Apr 18, 2023
PJF - 6Arithmetic
Half Adder: ImplementationHalf Adder: Implementation SS00 = A = A00 B B00
CC11 = A = A00BB00
The output of a half adder are AND and The output of a half adder are AND and XOR results of the two given input bits.XOR results of the two given input bits.
AA00
BB00
SS00
CC11
Logic Diagram
1 bit1 bit
half adderhalf adder
AA00 BB00
CC11
SS00
Block Diagram
Apr 18, 2023
PJF - 7Arithmetic
n-bit Additionn-bit Addition Design an n-bit binary adder which Design an n-bit binary adder which
performs the addition of two n-bit binary performs the addition of two n-bit binary numbers and generates a nnumbers and generates a n-bit sum-bit sum and a and a carry outcarry out..
Example: Let n=4Example: Let n=4
CCoutout C C33 C C22 C C11 C C00 11 1 0 1 1 0 1 00 A A33 A A22 A A11 A A00 1 1 0 1 1 1 0 1 +B +B33 B B22 B B11 B B00 +1 1 0 1 +1 1 0 1 -------------- ---------- -------------- ---------- SS33 S S22 S S11 S S0 0 1 0 1 01 0 1 0
Apr 18, 2023
PJF - 8Arithmetic
Full Adder: DefinitionFull Adder: Definition In a half adder, only two input bits are considered.In a half adder, only two input bits are considered. What if there is a carry from the less significant bits?What if there is a carry from the less significant bits? A full adder is to perform the additions of 3 bits, i.e., A full adder is to perform the additions of 3 bits, i.e.,
two input bits and a carry-in bit.two input bits and a carry-in bit.
Apr 18, 2023
PJF - 9Arithmetic
Full Adder: Implementation Full Adder: Implementation (1)(1)
AAii BBii CCii SSii CCi+1i+1
00 00 00 00 00
00 00 11 11 00
00 11 00 11 00
00 11 11 00 11
11 00 00 11 00
11 00 11 00 11
11 11 00 00 11
11 11 11 11 11
The K-maps forThe K-maps for CCi+1i+1::
SSii::
11111100
00110000
BBiiCCii
AAii
00110011
11001100
BBiiCCiiAAii
Apr 18, 2023
PJF - 10Arithmetic
Full Adder: Implementation Full Adder: Implementation (2)(2)
Boolean equations:Boolean equations: CCi+1i+1 = A = AiiBBii + A + AiiCCii + B + BiiCCii
SSii = A = AiiBBii’ C’ Cii’ + A’ + Aii’B’Bii’C’Cii + A + Aii’B’BiiCCii’ + A’ + AiiBBiiCCii
= A = Aii B Bii C Cii
You can design a full adder You can design a full adder directlydirectly from the above equations (requires 3 from the above equations (requires 3 ANDs and 1 OR for CANDs and 1 OR for Ci+1i+1 and 2 XORs for and 2 XORs for SSii) ) Can we do better?Can we do better?
Apr 18, 2023
PJF - 11Arithmetic
ObservationsObservations DerivationDerivation
CCi+1i+1 = A = AiiBBii + A + AiiBBii’C’Ci i + A+ Aii’B’BiiCCii
= A= AiiBBii + (A + (AiiBBii’ + A’ + Aii’B’Bii)C)Cii
= A= AiiBBii + (A + (Aii B Bii)C)Cii
and Sand Sii = A = Aii B Bii C Cii
Why it helps?Why it helps? We can first compute AND and XOR results among AWe can first compute AND and XOR results among Aii
and Band Bii, i.e., A, i.e., AiiBBi i and Aand Aii B Bii, using a half adder., using a half adder. Let DLet Dii=A=Aii B Bii.. Next we can compute DNext we can compute DiiCCii and D and Dii C Cii using the other using the other
half adder.half adder.
Full Adder by 2 Half AddersFull Adder by 2 Half Adders A full adder can be implemented using two half A full adder can be implemented using two half
adders and an OR gate.adders and an OR gate.
Apr 18, 2023
PJF - 12ArithmeticApr 18, 2023
PJF - 12Arithmetic
AAii
BBii
CCii
CCi+i+
11
SSii
1 bit1 bit
full adderfull adder
AAii BBii
CCi+1i+1
SSii
CCii
Exercise 1Exercise 1
How many gates are reduced by the How many gates are reduced by the half adder based implementation?half adder based implementation?
How many transistors are needed in How many transistors are needed in the half adder based the half adder based implementation?implementation? See page 35 in chapter 4See page 35 in chapter 4 34 transistors34 transistors
Apr 18, 2023
PJF - 13Arithmetic
Apr 18, 2023
PJF - 14Arithmetic
n-bit Combinational Addersn-bit Combinational Adders
Perform multi-bit additionPerform multi-bit addition How?How?
Apr 18, 2023
PJF - 15Arithmetic
nn-bit Ripple Carry Adder-bit Ripple Carry Adder
It is constructed using It is constructed using nn 1-bit full 1-bit full adder blocks.adder blocks.
Cascade the full adders so that the Cascade the full adders so that the carry out from one becomes the carry out from one becomes the carry in to the next higher bit carry in to the next higher bit position.position.
Apr 18, 2023
PJF - 16Arithmetic
Example: 4-bit Ripple Carry Example: 4-bit Ripple Carry AdderAdder
CC44 C3 C2 C1 C0 C3 C2 C1 C0
A3 A2 A1 A0 A3 A2 A1 A0 +B3 B2 B1 B0 +B3 B2 B1 B0 -------------- -------------- S3 S2 S1 S0 S3 S2 S1 S0
Characteristics of Ripple Characteristics of Ripple Carry AdderCarry Adder
Simple designSimple design What is the limitation?What is the limitation?
Apr 18, 2023
PJF - 17Arithmetic
Apr 18, 2023
PJF - 18Arithmetic
Ripple Carry Adder DelayRipple Carry Adder Delay Circuit delay in an n-bit ripple carry adder is determined by Circuit delay in an n-bit ripple carry adder is determined by
the delay on the carry path from the LSB (Cthe delay on the carry path from the LSB (C00) to the MSB (C) to the MSB (Cnn).). Let the delay in a 1-bit FA be Let the delay in a 1-bit FA be . The delay of an n-bit ripple . The delay of an n-bit ripple
carry adder is ncarry adder is n since it is a sequential computation. since it is a sequential computation.
Exercise 2Exercise 2
What could be a potential What could be a potential improvement in terms of delay?improvement in terms of delay?
Suppose that two 128-bit numbers Suppose that two 128-bit numbers are to be added.are to be added.
Apr 18, 2023
PJF - 19Arithmetic
128 bits
A127 ,…………………………….…., A0B127 ,……………………………..…., B0
Main Idea: Predict Carry InMain Idea: Predict Carry In Use three 64-bit addersUse three 64-bit adders One computes the lower One computes the lower
64 bits, one computes 64 bits, one computes higher 64 bits assuming higher 64 bits assuming the carry in Cthe carry in C6464 is 0, and is 0, and one computes higher 64 one computes higher 64 bits assuming the carry bits assuming the carry in Cin C6464 is 1. is 1.
All three adders All three adders compute simultaneouslycompute simultaneously
After that, one knows After that, one knows the right carry in Cthe right carry in C6464..
One just needs to pick One just needs to pick the correct result the correct result corresponding to the corresponding to the right Cright C6464..
Apr 18, 2023
PJF - 20Arithmetic
64 bits64 bits
A127 ,………., A64B127 ,………., B64
A63 ,………., A0
B63 ,………., B0
C64=0
64 bits
A127 ,………., A64B127 ,………., B64
C64=1
Advantage and LimitationAdvantage and Limitation
What is the delay?What is the delay? 6464 for each adder for each adder Assuming that picking time is also Assuming that picking time is also , ,
total delay is 65total delay is 65.. What is the limitation?What is the limitation? To add two n-bit numbers, what is To add two n-bit numbers, what is
the best delay?the best delay? Implementation?Implementation?
Apr 18, 2023
PJF - 21Arithmetic
Summary of This LectureSummary of This Lecture A half adder adds 2 input bits but not the carry in bit.A half adder adds 2 input bits but not the carry in bit. A full adder adds 2 input bits and the carry in bit.A full adder adds 2 input bits and the carry in bit. A fully adder can be efficiently implemented using 2 A fully adder can be efficiently implemented using 2
half adders and an OR gate.half adders and an OR gate. A ripple carry adder consists of n full adder A ripple carry adder consists of n full adder
sequentially to perform n bit addition.sequentially to perform n bit addition. It is simple but with significant delay which needs It is simple but with significant delay which needs
improvement.improvement.
Apr 18, 2023
PJF - 22Arithmetic
Apr 18, 2023
PJF - 23Arithmetic
Decimal ArithmeticDecimal Arithmetic Design circuits that perform decimal Design circuits that perform decimal
arithmetic such as addition and multiplication.arithmetic such as addition and multiplication. Input is in binary coded form in BCDInput is in binary coded form in BCD BCD Decimal AdderBCD Decimal Adder
4 bits per decimal number as input4 bits per decimal number as input 5 bits as output indicate the decimal sum and the 5 bits as output indicate the decimal sum and the
carrycarry Remember BCD addition rules. Remember BCD addition rules. Add 0110 to the sum if it is greater than or equal Add 0110 to the sum if it is greater than or equal
to 1010 to 1010 That is, 1010, 1011, 1100, 1101, 1110, 1111That is, 1010, 1011, 1100, 1101, 1110, 1111
Apr 18, 2023
PJF - 24Arithmetic
Binary Coded Decimal (BCD) Binary Coded Decimal (BCD) AdderAdder
AddendAddend
4-bit binary adderz3 z2 z1 z0
4-bit binary adderS3 S2 S1 S0
BCD sum
0
K
C
C = K + z3z2 + z3z1
Apr 18, 2023
PJF - 25Arithmetic
2’2’s Complements Complement For a positive For a positive nn digit number digit number NN22 in binary, the in binary, the 22's 's
complement, complement, 22C(C(NN22), is given by:), is given by:
22C(C(NN22) = ) = 22nn--NN22 , if , if nn > 0 > 000 , if n = 0, if n = 0
Example: Example: NN2 2 =1010=1010 22C(C(NN22) = ) = 2244--NN22 = 10000 = 1000022 – 1010 – 101022 = 0110 = 011022
Example: Example: NN2 2 =11111=11111 22C(C(NN22) = ) = 2255--NN22 = 100000 = 10000022 – 11111 – 1111122 = 00001 = 00001 22
{{
Apr 18, 2023
PJF - 26Arithmetic
2’2’s Complement (cont.)s Complement (cont.) Here’s an easier way to compute the Here’s an easier way to compute the 2’s2’s
complement:complement:1.1. Leave all least significant 0’s and first 1 unchanged.Leave all least significant 0’s and first 1 unchanged.
2.2. Replace 0 with 1 and 1 with 0 in all remaining higher Replace 0 with 1 and 1 with 0 in all remaining higher significant bits.significant bits.
Examples:Examples:
N = 1010 N = 1010 N = 01011000N = 01011000 01 10 01 10 10101000 10101000
Apr 18, 2023
PJF - 27Arithmetic
1’1’s Complements Complement For a positive For a positive nn digit number digit number NN22 in binary, in binary,
the the 11's complement, 's complement, 11C(C(NN22), is given by:), is given by:
11C(C(NN22) = ) = (2(2nn-1) - N-1) - N22
Example: Example: NN2 2 =011=011 1C(1C(NN22) = () = (2233-1)--1)-NN22 = 111 = 11122 – 011 – 01122 = 100 = 10022
Example: Example: NN2 2 =1010=1010 1C(1C(NN22) = () = (2244-1) - -1) - NN22 = 1111 = 111122 – 1010 – 101022 = 0101 = 0101 22
Observation: 1’s complement can be Observation: 1’s complement can be derived by just complementing all the bits derived by just complementing all the bits in the number.in the number.
Apr 18, 2023
PJF - 28Arithmetic
ObservationObservation Compare 1’s complement with 2’s Compare 1’s complement with 2’s
complement:complement: 22nn--NN = [(2= [(2nn-1) - N] + 1-1) - N] + 1
Thus, the 2’s complement can be obtained by Thus, the 2’s complement can be obtained by deriving the 1’s complement and adding 1 to it.deriving the 1’s complement and adding 1 to it.
Example:Example: N = 1001N = 1001 2C(N) = 22C(N) = 24 4 – N = 10000 – 1001 = 0111– N = 10000 – 1001 = 0111 1C(N) = 21C(N) = 24 4 – 1 - N = 1111 – 1001 = 0110– 1 - N = 1111 – 1001 = 0110 2C(N) = 1C(N) + 1 = 0110 + 0001 = 01112C(N) = 1C(N) + 1 = 0110 + 0001 = 0111
Apr 18, 2023
PJF - 29Arithmetic
Subtraction with Subtraction with 2’2’s s complement complement
A-B can be simply computed as A+2C(B) and A-B can be simply computed as A+2C(B) and deleting the leading the carry 1deleting the leading the carry 1
7-3 7-3 (111)-(011)=(111)+(101)=(1100)(111)-(011)=(111)+(101)=(1100) delete the carry which gives (100)delete the carry which gives (100)
Apr 18, 2023
PJF - 30Arithmetic
Subtraction with Subtraction with 1’1’s s complement complement
A-B can be simply computed as A+1C(B), deleting A-B can be simply computed as A+1C(B), deleting the carry and adding 1the carry and adding 1
7-3 7-3 (111)-(011)=(111)+(100)=(1011)(111)-(011)=(111)+(100)=(1011) Delete carry which gives (011)Delete carry which gives (011) Add 1 which gives (100)Add 1 which gives (100)
Apr 18, 2023
PJF - 31Arithmetic
Binary Adder/SubtractorsBinary Adder/Subtractors If we perform subtraction using complements, we If we perform subtraction using complements, we
eliminate subtraction operation, and thus, can use an eliminate subtraction operation, and thus, can use an adder with appropriate complementer for adder with appropriate complementer for subtraction.subtraction.
Thus, to form an adder-subtractor circuit, we only Thus, to form an adder-subtractor circuit, we only need a selective complementer and an adder.need a selective complementer and an adder.
The subtraction The subtraction AA--BB can be performed by taking the can be performed by taking the 2's complement of 2's complement of BB and adding to and adding to AA..
The 2's complement of The 2's complement of BB can be obtained by can be obtained by complementing B and adding one to the result.complementing B and adding one to the result.
A-B A-B = A + = A + 2C2C(B) (B) = A + = A + 1C1C(B) + 1(B) + 1
= A + B’ + 1= A + B’ + 1
Apr 18, 2023
PJF - 32Arithmetic
4-bit Binary 4-bit Binary Adder/SubtractorAdder/Subtractor
–XOR gates act as programmable XOR gates act as programmable invertersinverters
Apr 18, 2023
PJF - 33Arithmetic
When When SS=0, the circuit performs =0, the circuit performs AA + + BB. The . The carry in is 0, and the XOR gates simply carry in is 0, and the XOR gates simply pass pass BB untouched. untouched.
Assume that A > B. When Assume that A > B. When SS=1, the carry =1, the carry into the least significant bit (LSB) is 1, and into the least significant bit (LSB) is 1, and BB is complemented (1’s complement) prior is complemented (1’s complement) prior to the addition; hence, the circuit adds to to the addition; hence, the circuit adds to A the 1’s complement of A the 1’s complement of B B plus 1 (from the plus 1 (from the carry into the LSB).carry into the LSB).
4-bit Binary Adder/Subtractor 4-bit Binary Adder/Subtractor (cont.)(cont.)
Apr 18, 2023
PJF - 34Arithmetic
4-bit Binary Adder/Subtractor 4-bit Binary Adder/Subtractor (cont.)(cont.)
S=0
0
B0
S=0 selects addition
B1B2B3
Apr 18, 2023
PJF - 35Arithmetic
4-bit Binary Adder/Subtractor 4-bit Binary Adder/Subtractor (cont.)(cont.)
S=1
1
B0’
S=1 selects subtraction
B1’B2’B3’
Apr 18, 2023
PJF - 36Arithmetic
Binary MultiplierBinary Multiplier
Binary multiplication resembles decimal Binary multiplication resembles decimal multiplication:multiplication: nn-bit multiplicand is multiplied by each bit of -bit multiplicand is multiplied by each bit of
the the mm-bit multiplier, starting from LSB, to form -bit multiplier, starting from LSB, to form nn partial products. partial products.
Each successive set of partial products is Each successive set of partial products is shifted 1 bit to the left.shifted 1 bit to the left.
Derive result by addition the Derive result by addition the mm rows of partial rows of partial products.products.
Apr 18, 2023
PJF - 37Arithmetic
Half Adders are Sufficientsince there is no Carry-inin addition to the two inputsto sum
Binary Multiplier CircuitBinary Multiplier Circuit2-bit by 2-bit multiplier2-bit by 2-bit multiplier