EE207: Digital Systems I, Semester I 2003/2004

EE207: Digital Systems I, Semester I 2003/2004

CHAPTER 6-i:

Programmable Logic Devices (PLDs)

Overview

• Three-State Buffers

• Programmable Logic Technologies– Read-Only Memory (ROM)– Programmable Logic Arrays (PLAs)– Programmable Array Logic (PAL)

Chapter 6-i: Programmable Logic Devices (6.5 -- 6-8)

2Apr 20, 2023

Three-State Buffers

• Buffer output has 3 states: 0, 1, Z

• Z stands for High-Impedance Open circuit

EN = 0 out = Z (open circuit)

EN = 1 out = in (regular buffer)

ENEN inin outout

00 XX ZZ

11 00 00

11 11 11

Apr 20, 2023

3Chapter 6-i: Programmable Logic Devices (6.5 -- 6-8)

in out

EN

Three-state buffer(BUF)/inverter(INV)

symbols


4Apr 20, 2023

in out

EN

in out

EN

in out

EN

in out

EN

3-state BUF, EN high

3-state BUF, EN low 3-state INV, EN low

3-state INV, EN high

Multiplexed output lines using three-state buffers

• Assume an output line that can receive data from either a system (circuit) A or a system B.


5Apr 20, 2023

A

B

out

wiredlogic

If A = B out = A = BIf A B a large enough current can be created, that causes excessive heating and could damage the circuit.

Multiplexed output lines using three-state buffers (cont.)

• Solution: SS AA BB ENENAA ENENBB outout

00 00 00 11 00 00

00 00 11 11 00 00

00 11 00 11 00 11

00 11 11 11 00 11

11 00 00 00 11 00

11 00 11 00 11 11

11 11 00 00 11 00

11 11 11 00 11 11

Apr 20, 2023


A

B

out

ENA

ENB

S

A

B

A

B

S

out0

1

Programmable Logic Devices (PLDs)

• Standard logic devices that can be programmed to implement any combinational logic circuit.

• Standard of regular structure

• Programmed refers to a hardware process used to specify the logic that a PLD implements


7Apr 20, 2023

Gate Symbols


8Apr 20, 2023

...

Conventional AND gate symbol

...

Array Logic OR gate symbol

One major difference!

abc

F

F = a.b.c

a b cF = 0

F = a.c

Read-Only Memory (ROM)

• Stores binary information permanently

• Non-Volatile (info is kept even when power is turned off)

k inputs = specify the # of addresses available

n outputs = specify the size of data


9Apr 20, 2023

ROM2k x nk m

Block Diagram

Read-Only Memory (cont.)

• Example: k=3, n=4

• There are 23=8 available addresses

• 4-bits are stored in each address

00

11

22

33

44

55

66

77

Apr 20, 2023


Address

3 4

8x4 ROM

ROM construction: Example of an 25x8 ROM

• Use a 5-to-32 decoder to generate the 32 addresses.• Use 8 OR gates, each can be programmed to be driven by any of

the decoder outputs.

Apr 20, 2023


Programmablelogic. # of interconnectionsis 2255x8x8

Programming the ROM, i.e. load desired data at

specified addresses


12Apr 20, 2023

ROM addresses ROM data

Address(in decimal)

0123

28293031

Programming the ROM (cont.)


13Apr 20, 2023

Example: Let I0I1I3I4 = 00010 (address 2). Then, output 2 of thedecoder will be 1, the remaining outputs will be 0, and ROM outputbecomes A7A6A5A4A3A2A1A0 = 11000101.

ROM-based circuit implementation

• Given a 2kxn ROM, we can implement ANY combinational circuit with at most k inputs and at most n outputs.

• Why?– k-to-2k decoder will generate all 2k possible

minterms

– Each of the OR gates must implement a m()

– Each m() can be programmed


14Apr 20, 2023

Example

• Find a ROM-based circuit implementation for:– f(a,b,c) = a’b’ + abc– g(a,b,c) = a’b’c’ + ab + bc– h(a,b,c) = a’b’ + c

• Solution:– Express f(), g(), and h() in m() format (use

truth tables)– Program the ROM based on the 3 m()’s


15Apr 20, 2023

Example (cont.)

• There are 3 inputs and 3 outputs, thus we need a 8x3 ROM block.

• f = m(0, 1, 7)• g = m(0, 3, 6, 7)• h = m(0, 1, 3, 5, 7)


16Apr 20, 2023

3-to-8decoder

01234567

a

b

c

f g h

Programmable Logic Arrays (PLAs)

• Similar concept as in ROM, except that a PLA does not necessarily generate all possible minterms (ie. the decoder is not used).

• More precisely, in PLAs both the AND and OR arrays can be programmed (in ROM, the AND array is fixed – the decoder – and only the OR array can be programmed).


17Apr 20, 2023

PLA Example


18Apr 20, 2023

AND array

OR array

• f(a,b,c) = a’b’ + abc• g(a,b,c) = a’b’c’ + ab + bc• h(a,b,c) = c

PLAs can be more compactimplementations than ROMs,since they can benefit fromminimizing the numberof products required toimplement a function

Another PLA Example

• Find a PLA-based circuit implementation for:– F1(A,B,C) = AB’ + AC + A’BC’– F2(A,B,C) = (AC + BC)’

• Solution:– 3 inputs, 2 outputs ( 2 OR gates)– 4 distinct product terms (4 AND gates)– Use XOR array to find complements


19Apr 20, 2023

PLA Example (cont.)

Apr 20, 2023


XOR array

F2’ F1

PLA Example (cont.)Tabular Form Specification

of interconnection programming

Apr 20, 2023


F1 = AB’+AC+A’BC’F2 = AC+BC

Determining the size of a PLA

• Given:– n inputs– p product terms– m outputs

• PLA size is:– Gates: n INV (and maybe n BUF) + p ANDs +

m ORs + m XORs– Programmable interconnections:

2np + pm + 2m


22Apr 20, 2023

Programmable Array Logic (PAL)

• OR plane (array) is fixed, AND plane can be programmed

• Less flexible than PLA

• # of product terms available per function (OR outputs) is limited


23Apr 20, 2023

PAL Example


24Apr 20, 2023

inputs

1st output section

2nd output section

3rd output section

4th output section

Only functions withat most four products can be implemented

PAL-based circuit implementation


25Apr 20, 2023

W = ABC + CDX = ABC + ACD + ACD + BCD Y = ACD + ACD + ABD

Can we implement more complex functions using PALs?

• Yes, by allowing output lines to also serve as input lines in the AND plane.

Apr 20, 2023


Example

• Implement the combinational circuit described by the following equations, using a PAL with 4 inputs, 4 outputs, and 3-wide AND-OR structure.– W(A,B,C,D) = m(2,12,13)– X(A,B,C,D) = m(7,8,9,10,11,12,13,14,15)– Y(A,B,C,D) = m(0,2,3,4,5,6,7,8,10,11,15)– Z(A,B,C,D) = m(1,2,8,12,13)


27Apr 20, 2023

Example (cont.)

• Use function simplification techniques to derive:– W = ABC’+A’B’CD’– X = A+BCD– Y=A’B+CD+B’D’– Z=ABC’+A’B’CD’+AC’D’+A’B’C’D

= W + AC’D’+A’B’C’D


28Apr 20, 2023

Example (cont.)


29Apr 20, 2023

Example (cont.)


30Apr 20, 2023

Tabular Form Specificationof interconnection programming

EE207: Digital Systems I, Semester I 2003/2004

Documents

Transcript of EE207: Digital Systems I, Semester I 2003/2004