EE101 Lab4 Guillemaud
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Transcript of EE101 Lab4 Guillemaud
1
Operational Amplifiers Nikolas Guillemaud
Partner: Kristen Brossamer EE 101L
Professor: Joel Kubby
Submitted: 3/5/15
2
Introduction
In this experiment we explore the properties of operational amplifiers and their
response to DC and AC signals. Ideal op-amps have five key characteristics. First, the
input impedance is infinite which forbids any current flowing into either of the input
terminals. Second, the output impedance is zero enabling the op-amp to drive any load
impedance to any voltage. Additionally, ideal op-amps have infinite gain for the
differential input signal and zero gain on the common-mode input signal. Lastly, ideal
op-amps have infinite bandwidth and can reproduce extremely fast signals.
These idyllic properties culminate, in a negative feedback system, to impose what is
called the summing point constraint. Under this condition, the output voltage attains a
value such that the differential input voltage and input current are forced to zero. In
general, an op-amp produces an output voltage that is the difference between the two
input terminals multiplied by the gain v .
We investigate three types of op-amp circuits which can perform mathematical
operations on input signals. The first is an inverting amplifier, shown in Fig.1, which
inverts and amplifies the input signal. In this type of circuit the non-inverting terminal is
grounded which, due to the summing point constraint, turns the inverting terminal in to a
virtual ground.
3
Figure 1: Inverting op-amp circuit. Note the resistor fR bridging the output and input
to generate negative feedback.
The gain of the inverter is calculated utilizing the summing point constraint to set the
input current 1
in
in
vi
R equal to current
2out
f
vi
R
and solving for
fout
v
in in
RvA
v R
. (1)
The second type of circuit is an integrator, shown in Fig. 2, which produces an
output voltage proportional to the time integral of the input signal.
Figure 2: Integrating op-amp circuit. Note the capacitor now provides the negative feedback.
4
With 1
invi
R and the voltage across the capacitor equal to 1
0
1t
cv t i t dtC
the
summing point constraint is used to find out cv v t which results in
0
1
t
out inv t v t dtRC
. (2)
Here it can be seen that the output voltage is 1RC
times the time integral of the input
voltage.
The third type of circuit is a differentiator. This circuit, shown in Fig.3, produces an
output voltage proportional to the time derivative of the input signal.
Figure 3: Differentiating op-amp circuit. Note the capacitor is now regulating the input signal.
Here
1
indv ti t C
dt and 2
outvi
R
. Again, using the summing point constraint we find
in
out
dv tv t RC
dt . (3)
Here the output voltage is RC times the time derivative of the input voltage.
5
1. Fundamental Properties of an Op-Amp
1.1. DC Amplification
In the first part of the experiment we construct an inverting op-amp circuit and
investigate its response to DC voltage.
1.1.1. Procedure
We used a Jameco WBU-202-R breadboard and a National 741 op-amp to
construct the inverting circuit. Additionally, two Yageo carbon resistors with values
1 5.1 5%R k (green, brown, red, gold) and 2 10 5%R k (brown, black, orange,
gold) were implemented as shown in Fig. 4.
Figure 4: Diagram of the inverting amplifier circuit.
Next, an Agilent E3631A power supply was used to supply a DC voltage to the op-
amp with 15ccV V and 15eeV V . An identical power supply was used to provide
the input voltage inV . We took special care to ensure that the entire setup was
commonly grounded. This input voltage was varied from 5inV V to 5inV V in 1V
6
increments. For each input voltage, the output voltage outV was recorded with an
Agilent 34401A digital multimeter (DMM). This process was repeated for 15inV V
to 15inV V .
1.1.2. Results
The recorded data for outV within both voltage ranges 5 5inV V V and
15 15inV V V are shown in Tables 1 and 2 respectively.
Table 1: DC response of inverting
amplifier circuit 5 5inV V V .
Table 2: DC response of inverting
amplifier circuit 15 15inV V V .
Plotting outV versus inV further depicted the response of the circuit. In Fig.5 (next
page) we plotted the smaller range 5 5inV V V and observed a linear relation
between outV and inV . Fitting this data with a trend line yielded
1.9948 0.0109out inV V V . The gain of the circuit correlates to the slope of the
fitted line 1.9948vA .
Vin (V) Vout (V)
-5.00 10.045
-4.00 7.983
-3.00 5.968
-2.00 3.980
-1.00 1.990
0.00 0.001
1.00 -1.998
2.00 -3.978
3.00 -5.967
4.00 -7.958
5.00 -9.946
Vin (V) Vout (V) Vin (V) Vout (V)
-15.00 14.155 15.00 -13.497
-14.00 14.158 14.00 -13.500
-13.00 14.160 13.00 -13.504
-12.00 14.163 12.00 -13.508
-11.00 14.165 11.00 -13.512
-10.00 14.168 10.00 -13.516
-9.00 14.171 9.00 -13.520
-8.00 14.174 8.00 -13.525
-7.00 13.923 7.00 -13.529
-6.00 12.090 6.00 -11.930
-5.00 10.045 5.00 -9.946
-4.00 7.983 4.00 -7.958
-3.00 5.968 3.00 -5.967
-2.00 3.980 2.00 -3.978
-1.00 1.990 1.00 -1.998
0.00 0.001
7
Figure 5: Output voltage outV as a function of DC input voltage inV , for 5 5inV V V .
Figure 6: Output voltage outV as a function of DC input voltage inV , for 15 15inV V V .
y = -1.9948x + 0.0109
-11.0
-9.0
-7.0
-5.0
-3.0
-1.0
1.0
3.0
5.0
7.0
9.0
11.0
-6.0 -5.0 -4.0 -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0
Vo
ut
Vin
Vout vs. Vin
Vout
Linear (Vout)
-15.0
-13.0
-11.0
-9.0
-7.0
-5.0
-3.0
-1.0
1.0
3.0
5.0
7.0
9.0
11.0
13.0
15.0
-16.0 -14.0 -12.0 -10.0 -8.0 -6.0 -4.0 -2.0 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0
Vo
ut
Vin
Vout vs. Vin
Vout
8
In Fig.6 (previous page) we plotted the larger range 15 15inV V V and
observed that outV reaches a minimum and maximum value at 7.0inV V while
maintaining the linear relationship within the smaller range.
1.1.3. Conclusion
By comparing the calculated gain from Eqn. 1
2
1
10.041.988
5.05v
R kA
R k
to the gain deduced from the linear fit of the data in Fig. 5
1.9948vA ,
we conclude that the experimental results behaved as the theory predicted.
In Fig. 6 it can be seen that when the input voltage 7 7inV V V the output
voltage reaches a minimum and maximum value and the theory no longer holds.
This result is due to the limitations imposed by the supply voltages which power the
op-amp, ccV and eeV . If the input voltage is such that it would drive the output voltage
beyond the op-amp saturation voltage, the output signal is clipped.
1.2. Input Resistance
In this part of the experiment we determine the input resistance of the circuit.
1.2.1. Procedure
Utilizing the same circuit depicted in Fig.4 we set 3inV V and used the DMM to
measure and record the input current 1i which flowed through the resistor 1R . This
9
was accomplished by opening the circuit immediately after 1R and connecting the
probes of the DMM.
1.2.2. Results
We measured that the input current was 1 0.593i mA . Using Ohm’s law we
calculated the input resistance to be 1
3.0 5059.020.593
ininput
v VRi mA
.
1.2.3. Conclusion
We find that the experimental value 5059inputR is consistent with the
anticipated value of 1 5.05R k . The value is 0.2% larger than expected because
the non-idyllic op-amp reduced the measured current 1i by a miniscule amount.
1.3. AC Amplification
Here we test the response of the inverting circuit to AC input signals. Then we
construct an integrating op-amp circuit and characterize how it responds to AC
signals.
1.3.1. Procedure
Still using the inverting circuit from Fig. 4, we replaced the DC input voltage with
an Agilent 33120A function generator. It was set to input a sinusoidal signal with
amplitude 1.0inV V at a frequency of 100Hz . To monitor inV and outV we used a
Tektronix DPO2000 oscilloscope with inV on Channel 1 and outV on Channel 2.
Setting the timescale so that we could view a few periods, we observed the
amplification between inV and outV and noted the phase difference between them.
10
We then drove the amplifier beyond its saturation point, by increasing the amplitude
of inV and observed outV on the scope.
Next, we constructed an integrator circuit. This was done using the same Jameco
WBU-202-R breadboard and National 741 op-amp. The capacitor used was a
Murata-103, rated at 50V with capacitance 10C nF . Additionally, two Yageo
carbon resistors with values 1 39 5%R k (orange, white, orange, gold) and
2 10 5%R M (brown, black, blue, gold) were used. These parts were assembled
as shown in Fig. 7.
Figure 7: Schematic of integrating circuit. By placing 2R in parallel with C we
compensate for non-idealities. In practice there is an imbalance in the input currents
1 2 0i i which manifests itself as a non-zero DC offset signal on one of the inputs.
With 2R in parallel a finite DC gain is imposed and this offset no longer results in a
ramp but rather a constant output offset that is an amplified version of the input offset.
11
Using the oscilloscope to monitor inV on Channel 1 and outV on Channel 2 we
used the function generator to produce a sinusoidal input signal with an amplitude of
1V and a frequency 100f Hz . We observed the amplitude and phase difference of
outV with respect to inV . We then varied the frequency from 1Hz to 10kHz and
measured the amplification outv
in
vA
v and phase difference for each step.
1.3.2. Results
With the function generator inputting a sinusoidal signal of amplitude 1.0inV V at
a frequency of 100Hz in to the inverting circuit, we captured a scope image (Fig.8)
depicting inV and outV . We observed that the gain was 2vA and the phase
difference was 180o .
Figure 8: Scope capture of inverting circuit showing inv (ch1/yellow), set to 1V
and 100Hz on the function generator, and outv (ch2/blue). Note that the scope
reads amplitude from peak-to-peak (P-P), giving the absolute magnitude of the signal. Thus, 1V input from the function generator is 2V on the scope.
12
Increasing the amplitude of inV we drove the amplifier beyond its saturation point
and saw that outV becomes clipped (Fig.9).
Figure 9: Scope capture of inverting circuit showing inv (ch1/yellow), set to 10V
and 100Hz on the function generator, and outv (ch2/blue).
With the function generator inputting a sinusoidal signal of amplitude 1.0inV V at
a frequency of 100Hz in to the integrating circuit, we captured a scope image (Fig.10)
depicting inV and outV . In this trace we see that 90o and that the amplification,
using absolute max voltages, was 4outv
in
VA
V . Then varying the frequency we
recorded the amplification and phase difference, relative to inV , as shown in Table 3.
13
Figure 10: Scope trace of integrating circuit depicting inv (ch1/yellow), set to 1V
and 100Hz on the function generator, and outv (ch2/blue).
Table 3: Recorded data from the integrating circuit for 1 10f kHz . Note that the
absolute values of the gain measurements (amplification) were used to enable conversion to decibels.
f (Hz) log(f) V1 (V) V2 (v) Av 20log(A) (dB) Δt (ms) ΔΦ
1.010 0.004 2.60 28.00 10.769 20.644 464.0 168.7
2.013 0.304 2.60 28.00 10.769 20.644 224.0 162.3
5.007 0.700 2.40 28.00 11.667 21.339 84.0 151.4
10.020 1.001 2.60 28.00 10.769 20.644 38.40 138.5
20.060 1.302 2.60 28.00 10.769 20.644 17.20 124.2
50.560 1.704 2.40 14.80 6.167 15.801 5.00 91.0
99.320 1.997 2.60 7.40 2.846 9.085 2.50 89.4
202.2 2.306 2.40 3.80 1.583 3.991 1.28 93.2
399.1 2.601 2.00 2.00 1.000 0.000 0.664 95.4
800.6 2.903 2.00 1.20 0.600 -4.437 0.322 92.8
1598.0 3.204 1.96 0.64 0.327 -9.722 0.165 94.9
3195.0 3.504 1.88 0.40 0.213 -13.442 0.0788 90.6
6406.0 3.807 1.92 0.12 0.063 -24.082 0.0788 181.7
10020.0 4.001 1.92 0.06 0.031 -30.103 0.0788 284.2
14
By plotting decibels ( 20 vLog A ) as a function of decade ( Log f ) we can
deduce the cutoff frequency, how quickly the circuit reduces its output amplification
as a function of frequency, and the maximum gain as limited by the op-amp
powering voltages ccV and eeV .
Figure 11: Decibels as a function of decade for the integrating circuit.
1.3.3. Conclusion
Examining the trace in Fig. 8 for the inverting circuit we conclude that the gain
exhibited by the circuit 2vA is consistent with the expected value of
2
1
10.04 1.995.05v
R kAR k
. Similarly, the trace in Fig. 10 shows that the
integrator also demonstrated behavior consistent with expectation. We notice that
the amplitude of outv follows Eq.2 turning what can be viewed as a sine wave in to a
cosine function with a phase difference of 90o . With this trace we can see that
y = -18.529x + 47.705
-35.0
-30.0
-25.0
-20.0
-15.0
-10.0
-5.0
0.0
5.0
10.0
15.0
20.0
25.0
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50
20Log(A
v)
(dB
)
Log(f)
20Log(A) vs. Log(f)
20Log(A)
Fit
Linear (Fit)
15
the circuit does indeed act as an integrator if we arbitrarily take the vertical center
line to be 0t . At this point in the trace inv looks like a sine wave starting at zero.
Following Eq.2 we anticipate that the integral of the sine function is a negative
cosine function but since this is an inverting op-amp, outv is in fact a positive cosine
function at 0t .
Additionally, looking at the plot from Fig.11 for the integrator, we see that the line
fitted to the linear part of the data had a slope of 18.529dBdecade
. This was
consistent with the anticipated 20dBdecade
which was expexted after the input
frequency inf surpassed the cutoff frequency 0 50f Hz . This effectively creates a
low pass filter. The slight discrepancy can be attributed to error arising from
resolution of the voltage and time scales used on the scope at the low frequencies.
Furthermore, we note that the amplification plateaus for low frequency as the
capacitor acts like an open circuit. In this low frequency regime the amplification is
equal to that of the DC amplification and is limited by the powering voltages of the
op-amp ccV and eeV .
2. Design of an Integrator
Here we design an integrating or differentiating circuit to meet specific criteria.
We chose design an integrator.
2.1. Fixed Frequency Operation
The integrator needed to integrate an AC signal of frequency 1f kHz with an
amplitude of 1inv V to produce an output signal 1outv V .
16
2.1.1. Procedure
Using the same capacitor from the previous integrator we first determined the
required resistance values for 1R and 2R . Using complex impedances 1 1Z R and
1
22
1Z j CR
in the gain equation we found
2
1
1
1
outv
in
c
v RA
jv R
, (4)
where corresponds to our frequency of interest 1f kHz and c corresponds to
the cutoff frequency 0 80f Hz . Setting the gain equal to one we calculated the
required resistances:
1
1 2 1 10 15.923R kHz nF k
1
2 2 80 10 212.2R Hz nF k
.
We then constructed an integrator circuit. This was done using the same Jameco
WBU-202-R breadboard and National 741 op-amp as previously used. The capacitor
used was a Murata-103, rated at 50V with capacitance 10C nF . Additionally, four
Yageo carbon resistors were used. We used an equivalent series resistance to
attain 1 A B CR R R R where: 10 5%AR k (brown, black, orange, gold),
5.1 5%BR k (green, brown, red, gold), 1.0 5%CR k (brown, black, red, gold).
The last resistor used was 2 220 5%R k (red, red, yellow, gold). These parts were
assembled as shown in Fig. 12.
17
Figure 12: Integrator designed for fixed frequency operation.
After construction we supplied the op-amp with power as before and monitored
inV on Channel 1 and outV on Channel 2 . Then inputting an AC signal of 1f kHz we
verified its operation. We then varied the frequency and observed what happened.
2.1.2. Results
We saved the oscilloscope trace for 1f kHz which can be seen in Fig. 13.
18
Figure 13: Designed integrator operation at 1f kHz . Note that the scope reads
amplitude from peak-to-peak (P-P), giving the absolute magnitude of the signal. Thus,
1V input from the function generator is 2V on the scope
Then, varying the frequency to 500f Hz we saved another scope trace (Fig. 14).
Figure 14: Designed integrator operation at 500f Hz .
19
2.1.3. Conclusion
Examining Fig. 13, we see that the integrator performed as expected and
produced an output amplitude equal to the input amplitude. By varying the frequency
the amplification changed. For lower frequencies the amplitude of outv increased
(Fig. 14) and for higher frequencies it decreased. This is consistent with the
operation of the integrator in the previous experiment.
2.2. Tunable Integrator
In this part of the experiment we aimed to modify our circuit from Fig. 12 so that it
would integrate a range of AC signal of frequencies 100f Hz to 1000f Hz
having an amplitude of 1inv V and produce an output signal 1outv V .
2.2.1. Procedure
Using the same circuit from Fig. 12 we replaced 1R with a potentiometer pR . To
determine which potentiometer to use we calculated the required resistance values
for 1R corresponding to the minimum and maximum frequencies. These were:
1
2 100 10 159pR Hz nF k
1
2 1000 10 1591pR Hz nF
.
We selected the 100k potentiometer (Bourns 104l) and inserted it in place of 1R .
We supplied the op-amp with power as before and monitored inV on Channel 1 and
outV on Channel 2 while varying the frequency over the specified range. We adjusted
20
the potentiometer so that the gain was maintained at 1vA . For each step in the
range we recorded the gain and phase difference of outv with respect to inv .
2.2.2. Results
The recorded data are shown in Table 4.
Table 4: Recorded data for the tunable integrating circuit.
The gain and phase difference of outv relative to inv are further illustrated by
plotting them as functions of frequency, Figs. 15 & 16 respectively.
Figure 15: Gain as a function of frequency for tunable integrator.
f (Hz) V1 (V) V2 (V) Av ΔΦ
100 2.0 2.68 1.34 -125
200 2.0 2.04 1.02 -111
300 2.0 2.04 1.02 -104
400 2.0 2.00 1.00 -102
500 2.0 2.00 1.00 -100
600 2.0 2.04 1.02 -98
700 2.0 2.00 1.00 -97.45
800 2.0 2.00 1.00 -97
900 2.0 2.04 1.02 -96
1000 2.0 2.04 1.02 -95.54
0.80
0.90
1.00
1.10
1.20
1.30
1.40
1.50
0 200 400 600 800 1000 1200
Ga
in
Frequency (Hz)
Gain vs. Frequency
21
Figure 16: Phase difference as a function of frequency for tunable integrator.
2.2.3. Conclusion
The tunable integrating circuit worked as designed. The gain was held constant
(Fig.15) except at the lowest frequencies due to the potentiometer maxing out at
100k . This issue would be resolved with a larger value potentiometer.
In Fig. 16 we see that outv lags inv and that the magnitude of the phase difference
decreases with increasing frequency. By holding the gain steady the phase
difference compensated for the changes in frequency, as anticipated.
-130
-125
-120
-115
-110
-105
-100
-95
-90
0 100 200 300 400 500 600 700 800 900 1000 1100
ΔΦ
(d
egr
ee
s)
Frequency (Hz)
Phase Difference vs. Frequency
22
References
1. “Lab 3: Transient Response of RC/RL Circuits”, J. Kubby, 2015
UCSC, Baskin School of Engineering, EE Department
EE-101L: Electronic Circuits
2. “Electrical Engineering” A. Hambley, 5th edition, 2011