EE 466/586 VLSI Design Partha Pande School of EECS Washington State University [email protected].
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Transcript of EE 466/586 VLSI Design Partha Pande School of EECS Washington State University [email protected].
![Page 1: EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu.](https://reader036.fdocuments.in/reader036/viewer/2022062422/56649f265503460f94c3db5c/html5/thumbnails/1.jpg)
EE 466/586EE 466/586VLSI DesignVLSI DesignPartha Pande
School of EECSWashington State University
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Lecture 18Implementation Methods
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The Design Productivity Challenge
Source: sematech97
A growing gap between design complexity and design productivity1981
Logic Transistors per Chip (K) Productivity (Trans./Staff-Month)
19831985198719891991199319951997199920012003200520072009
58%/Yr. compoundComplexity growth rate
21%/Yr. compoundProductivity growth rate
198
1
10
Log
ic T
ran
sist
ors
pe
r C
hip
(K
)
Pro
du
ctiv
ity (
Tra
ns.
/Sta
ff-M
on
th)
100
1,000
10,000
100,000
1,000,000
10,000,000
1
XX
X XX
X
x
100
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
10
2.5m
.35m
.10m
198
3
198
5
198
7
198
9
199
1
199
3
199
5
199
7
199
9
200
1
200
3
200
5
200
7
200
9
Transistor/Staff Month
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A Simple Processor
MEMORY
DATAPATH
CONTROL
INPUT-OUTPUT
INP
UT
/OU
TP
UT
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Simple Processor (Cont’d)Datapath
•All computations are performed•Combinational & Arithmetic operations
Control Module •Sequential circuit•FSM
Memory module•Data storage
Interconnect• Integrating the whole system
I/O circuitry•Connects to outside world
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A System-on-a-Chip: ExampleA System-on-a-Chip: Example
Courtesy: Philips
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Implementation Approach
Flexibility (Programmable design)•Reuse of single design for multiple applications•Upgrade in the field
Hard-wired•Totally fixed at the manufacturing time
Flexibility comes at the cost of higher energy dissipation
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Impact of Implementation ChoicesImpact of Implementation ChoicesE
nerg
y E
ffic
ienc
y (i
n M
OP
S/m
W)
Flexibility(or application scope)
0.1-1
1-10
10-100
100-1000
None Fullyflexible
Somewhatflexible
Har
dwire
d cu
stom
Con
figur
able
/Par
amet
eriz
able
Dom
ain
-spe
cific
pro
cess
or(e
.g.
DS
P)
Em
bedd
ed m
icro
proc
ess
or
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Implementation ChoicesImplementation Choices
Custom
Standard CellsCompiled Cells Macro Cells
Cell-based
Pre-diffused(Gate Arrays)
Pre-wired(FPGA's)
Array-based
Semicustom
Digital Circuit Implementation Approaches
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Custom Circuit Design
Performance or Design density is of prime importance
•Long time to marketCan be justified in limited situations
•Custom block can be reused many time (e.g. memory blocks)•Cost can be amortized over large volumes
Design automation•Very critical components are designed manually
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The Custom Approach The Custom Approach
Intel 4004
Courtesy Intel
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Transition to Automation and Regular StructuresTransition to Automation and Regular Structures
Intel 4004 (‘71)Intel 4004 (‘71)Intel 8080Intel 8080 Intel 8085Intel 8085
Intel 8286Intel 8286 Intel 8486Intel 8486Courtesy Intel
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Cell-based Design Standardizes the design entry level at the logic gateLibrary of logic gates
•Inverter, AND/NAND, OR/NOR, Flip-flops•More complex functions, AOI…..
Design generation•Schematic using the cells•Higher level description language (VHDL, Verilog)
All cells have identical heightsWidths of the cells may varyStandard cell design can be combined with other layout methodologies
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Cell-based Design (or standard cells)
Routing channel requirements arereduced by presenceof more interconnectLayersFeed Through cells – Connect between cells in different rows without having to route around a complete rowFunctional
module(RAM,multiplier,…)
Routingchannel
Logic cellFeedthrough cell
Row
s o
f ce
lls
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Standard Cell — ExampleStandard Cell — Example
[Brodersen92]
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Standard Cell – The New GenerationStandard Cell – The New Generation
Cell-structurehidden underinterconnect layers
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Standard Cell - ExampleStandard Cell - Example
3-input NAND cell(from ST Microelectronics):C = Load capacitanceT = input rise/fall time
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Macrocells
Complex blocks than random logic functions (Multipliers, DSPs …)Complex cells – Macro cells
Macro cells
Hard Macro
Soft Macro
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Hard & Soft Macro
Hard Macro - Design of a logic function on a chip that specifies how the required logic elements are interconnected and specifies the physical pathwaysand wiring patterns between the components.
Soft Macro - Design of a logic function on a chip that specifies how the required logic elements are interconnected,but not the physical wiring pattern.
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Hard MacroModules
25632 (or 8192 bit) SRAMGenerated by hard-macro module generator
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“Soft” MacroModules
Synopsys DesignCompiler
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“Intellectual Property”
A Protocol Processor for Wireless
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Semicustom Design Flow
HDLHDL
Logic SynthesisLogic Synthesis
FloorplanningFloorplanning
PlacementPlacement
RoutingRouting
Tape-out
Circuit ExtractionCircuit Extraction
Pre-Layout Simulation
Pre-Layout Simulation
Post-Layout Simulation
Post-Layout Simulation
StructuralStructural
PhysicalPhysical
BehavioralBehavioralDesign Capture
Des
ign
Iter
atio
nD
esig
n It
erat
ion
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The “Design Closure” Problem
Courtesy Synopsys
Iterative Removal of Timing Violations (white lines)
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Integrating Synthesis with Physical Design
Physical SynthesisPhysical Synthesis
RTL (Timing) Constraints
Place-and-RouteOptimization
Place-and-RouteOptimization
Artwork
Netlist with Place-and-Route Info
MacromodulesFixed netlists