eDRIVEsim is an advanced real-time, hardware-in-the-loop (HIL) simulator and control prototyping platform specifically designed for motor drives, power electronics, and electromechanical systems.

eDRIVEsim software is based upon Opal RT’s RT-LAB - the real-time technology that has revolutionized the way model-based design is performed. RT-LAB’s flexibility and scalability allows it to be used in virtually any simulation or control system application, and to add computing-power where and when it is needed.

eDRIVEsim also uses Simulink as a front-end graphical modeling environment, and comes with a full range of software tools and libraries for the real-time modeling and simulation of power converters and motor drives (e.g. PMSM, BLDC, IM).

eDRIVEsim uses both the latest Intel® multi-core X86 processors and Xilinx FPGA chips as real-time targets, in addition to high speed Opal-RT OP5000 FPGA-based inputs and outputs (I/O), making it the ideal real-time platform for designing advan-ced control systems and performing HIL testing of controllers and ECUs used in high-speed electric motors, power converters, hybrid drives and distributed energy generation and distribution systems.

eDRIVEsim is available in a 19-inch rack mount chassis or a compact MX STATION portable chassis.

Key FeaturesSimulates AC motor drives and tests their controllers in a HIL setup (see Figure 1) Ready-to-use and user-designed Simulink models can be executed on Intel® Core™ 2 Duo, Core™ 2 Quad, or on eDRIVEsim’s Xilinx-based FPGA board for sub-microsecond simulation step sizeSupport for up to four CPUs allows for simulation of very complex multi-drive and AC-fed systems. Upgradeable to eMEGAsim 8-CPU power grid simulators Support for DQ and JMAG finite-element-based PMSM motor models Sampling period as low as 7-10 microseconds on Intel CPU, depending on model size and characteristics1-2 microseconds total input-output latency for models implemented on FPGA (eDRIVEsim OP4120)

FPGA-controlled I/Os processed with a resolution of 10 nanosecondsI/O library for all functions needed to simulate and control power electronics and motor drives including PWM, quadrature encoders, timed DI/O, and frequency/duty measurementCircuit models can be designed as block-diagrams in MATLAB/Simulink®. SimPowerSys-tem and ARTEMIS optional.Interact with real-time targets through Opal RT’s TestDRIVE® LabVIEW graphical user interfaceOn-line modification of model set points and parameters without the need for recompilationSupport for multi-rate models Data logging feature displays and saves signals in real-time for post-processing and analysis

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Figure 1. Hardware-in-the-loop setup with eDrIVesim

Windows Host PC

Hardware-in-the-Loop Simulator and Control Prototyping System for Motor Drives and Power Electronics

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Figure 2. Very small latency & time step withthe FPGA real-time target

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3 eDrIVesim OP4130Intel Core-2 Quad-processor and 1 Xilinx FPGA board dedicated solely to I/O mana-gement. Quad-core processor enables the simulation of complex multi-drive systems

eDrIVesim OP4120Intel Core 2 Duo processor, one Xilinx FPGA board dedicated solely to I/O management, and an additional Opal-RT’s OP5130 Virtex-II Pro FPGA board for use as a real-time target. eDRIVEsim OP4120 provides increased processing power to achieve model uptate at every 250 nanos and a very low input to output latency of 1 to 2 microseconds, required for maximum accuracy (see Figure 2).

eDrIVesim OP4110Intel Core 2 Duo processor and one Xilinx FPGA board dedicated solely to I/O management.

Figure 2. Very small latency & time step with the FPGa real-time target

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Figure 3. sample ap-plications that can be simulated with eDrIVesim

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Simulink With Opal-RT’s eDRIVESim you can develop the circuit of the application (motor drive, power conversion system) in Simulink®, with basic components taken from different libraries.

CPU real-time target Blocks from Opal-RT’s specialized modeling libraries RTeDrive™, RT-Events™ and ARTEMIS (with SimPowerSystems®) blocksets can be included in your Simulink model to run on the CPU real-time target.

FPGA real-time target In addition, with eDRIVEsim OP4120, you can incorporate sub-systems designed with blocks from the Xilinx Blockset for Simulink into your model. This allows that part of the model to be executed on the eDRIVEsim OP4120’s Xilinx FPGA chip allowing testing of fast controllers and protection systems, and achieving a low level of latency unprecedented in the simulation of high speed motors and high switching frequency converters. Models can be connected to external equipment (e.g. ECU, motor controller, etc), simply by dragging-and-dropping any input or output needed (e.g. A/D, D/A, DIO, Encoder, etc) from the extensive list of I/O blocks available in the

RT-LAB I/O library. After compilation, the Simulink part of the model is downloaded to the Core-2 Duo or Quad processor, while the Xilinx part is downloaded to the OP5130 FPGA (in the eDRIVEsim OP4120). The resulting real-time target is ready to be connected to the physical equipment to be controlled or tested, by the means of analog and digital I/Os.

Distributed processing Using RT-LAB distributed and parallel processing scheduler, models can be easily distributed on multiples processing cores. One core is dedicated to the commu-nication with the host PC, data logging, as well as running other slower parts of the model (slow dynamics). Remaining cores are fully dedicated to model compu-tation with time steps as low as 5 microseconds, all in addition to the ultra-low latency part running on the FPGA itself.

Motor drives and JMAG-RT eDRIVEsim can run accurate motor models with model data (induc-tance and torque map) generated from your motor design software like JMAG-RT® (from JRI Solutions, Ltd.)

PerFOrmanCeWith eDRIVEsim OP4110 and OP4130 real-time systems, typical AC mo-tor drive, including the motor and a 6-switch inverter (from RT-Events and RTeDrive toolboxes) can be simulated at a time step in the range of 10-20 microseconds, depending on the model characteristics and I/O used. This makes these eDRIVEsim configurations ideal for testing motor drives (and other electrical applications) with a switching frequency up to 10 kHz, and a rotation speed up to 6000 RPM.

With the eDRIVEsim OP4130, multiple drives and other complex power converters can be simulated on four processing cores.

Using Opal-RT’s OP5130 FPGA board, eDRIVEsim 4120 can achieve total latency below 1.5 microseconds by executing models on the FPGA chip (Figure 1.2).

HIl sImulatOr anD raPID COntrOl PrOtOtyPInG system

TyPICAL APPLICATIONSeDRIVEsim is designed to conduct controller testing through HIL simulation of various electric and power electronic systems (Figure 3).

Typical applications include: • PMSM, BLDC, and IM motor drives • Automotive and transportation : Hybrid powertrain, auxiliary power systems, power steering, train traction and ship propulsion systems • Rectifiers and battery chargers • Wind energy systems and power grid • Industrial drives, multi-level converters, distributed energy generation systems etc.

eDRIVEsim can also be used for fast control prototyping to implement control algorithms and to test them in real-time, in both fully digital mode or in HIL mode by connecting the prototyped controller I/Os to the virtual plant or a real-plant.

Figure 4. The currents of a PMSM motor drive HIL simulation with eDRIVEsim closely match actual motor currents including the distortion caused by dead time

relateD PrODuCts• eMEGAsim : 8 to 64 processor real-time simulator for the study of electromagnetic transients in very large power systems • RT-Events : Simulink blockset for RT Simulation of hybrid events-based systems • RTeDrive : Simulink blockset for motor drive simulation (included in eDRIVEsim) • RT-LAB : Real-time software platform

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Figure 3. sample ap-plications that can be simulated with eDrIVesim

sImulatIOn aCCuraCyeDRIVEsim simulation accuracy has been validated and demonstrated by comparing eDRIVEsim OP4100 HIL results with an actual test bench (Figure 4).

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Figure 5. High fidelity JMAG-RT motor model are supported by eDRIVEsim

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teCHnICal sPeCIFICatIOns OP4110 OP4120 OP4130 Unit/Description

Processor & OS Manufacturer Intel Intel Intel Model C.2 Duo (1) C.2 Duo (1) C.2 Quad (2) Clock 2.4 GHz 2.4 GHz 2.4 GHz RTOS QNX QNX QNX

FPGA Boards FPGA Brand Xilinx Xilinx Xilinx FPGA Model Virtex-II Pro Virtex-II Pro Virtex-II Pro Refer to Xilinx Virtex-II Pro datasheet for detailed specifications Clock 100 100 100 MHz OP5110 Board • • • FPGA PCI board for reconfigurable processing and I/O OP5130 Board n/a • Option FPGA OPXI 4U board for reconfigurable processing and I/O

Chassis HILBox • • • Dimensions: 432x178x508 mm; Weight: 23 Kg MX Station Option Option n/a Dimensions: 381x127x 305 mm; Weight:12.5 Kg

Software Modules RT-LAB • • • Real-Time software to run Simulink models on distributed x86 processors and FPGAs RT-Events Option Option • Simulink blockset for the RT simulation of hybrid dynamic systems with events RTeDrive • Option • Simulink Blockset of converter and motor models to simulate motor drives in RT ARTEMIS Option Option Option Simulink solver toolbox to simulate AC-fed circuits, used solely with SimPowerSys RT-LAB.XSGdev n/a • Option S/W tool to design FPGA algorithms with Xilinx Blockset and run them on Xilinx FPGA RT-LAB.XSGrun n/a • Option Runtime license to execute user or OPAL-RT developed FPGA functions XSGeDRIVE.run n/a • Option Simulink blockset designed with Xilinx blocks to simulate motor drives on FPGA RT-LAB.JMAG Option Option Option Interface to JMAG-RT finite element tool to run high fidelity motor model on CPU RT-LAB.JMAG.FPGA Option Option Option Interface to JMAG-RT finite element tool to run high fidelity motor model on FPGA

Inputs and Outputs (Additional I/O can be added) Analog Inputs 8/16 16 16 16 bits; 2.5 microsecond update time; ±1 V (18V nominal) to ± 100 V input range Analog Outputs 8/16 16 16 16 bits; 1 microsecond update time; ± 16 V output range Digital Inputs, timed 8/16 16 16 Opto-coupled; fiber optics are optional (see accessories) Digital Inputs, timed 8/16 16 16 Opto-coupled; fiber optics are optional (see accessories)

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RT-LAB, eDRIVEsim, eMEGASim, RT-Events, RTeDrive, RT-LAB.XSG, RT-LAB.JMAG, ARTEMIS, TestDRIVE are trademarks of Opal-RT Technologies Inc. Intel, Xilinx, Intel Core 2 Duo, Intel Core 2 Quad, JMAG, JMAG-RT, MATLAB, Simu-link, LabVIEW are tradmarks or registered trademarks of their respective companies

(1) Core™ 2 Duo (2) Core™ 2 Quad

aCCessOrIesOPxxxx SCXI screw terminal OP5949 Active Signal Monitor Panel OP5232 Amplitude Modulation Board (Resolver, LVDT/RVDT) OP5231 Fiber Optic 16Tx & 16Rx DIO board MXStation A chassis with a smaller size (381x127 x_305 mm) It be used for the OP4110 and OP4120 only (Figure 6), instead of the HILBOX 19”rack mount chassis which can be used for all models.

For more information : Toll Free North America 1-877-935-2323 Tel 1-514-935-2323 Fax : 1-514-935-4994 e-mail : info@opal-rt.com

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